| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveIntervalUnion.cpp | 160 LiveInterval *VReg = LiveUnionI.value();
161 if (VReg != RecentReg && !isSeenInterference(VReg)) {
162 RecentReg = VReg;
163 InterferingVRegs->push_back(VReg);
|
| CallingConvLower.cpp | 260 Register VReg = MF.addLiveIn(PReg, RC);
261 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
|
| SwiftErrorValueTracking.cpp | 37 auto VReg = MF->getRegInfo().createVirtualRegister(RC);
38 VRegDefMap[Key] = VReg;
39 VRegUpwardsUse[Key] = VReg;
40 return VReg;
46 const Value *Val, Register VReg) {
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg;
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
60 VRegDefUses[Key] = VReg;
61 setCurrentVReg(MBB, Val, VReg);
62 return VReg;
[all...] |
| LiveRangeEdit.cpp | 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
57 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
66 LIS.getInterval(VReg).markNotSpillable();
67 return VReg;
411 unsigned VReg = LI->reg();
413 TheDelegate->LRE_WillShrinkVirtReg(VReg);
423 if (VReg == RegsBeingSpilled[i])
[all...] |
| RenameIndependentSubregs.cpp | 98 /// Rewrite Machine Operands to use the new vreg belonging to their class.
132 // Create a new VReg for each class.
245 unsigned VReg = Intervals[ID]->reg();
246 MO.setReg(VReg);
248 if (MO.isTied() && Reg != VReg) {
254 MI->getOperand(TiedIdx).setReg(VReg);
262 // classes than the original vreg.
312 // violate this principle as the splitted vreg may not have a definition on
351 // After assigning the new vreg we may not have any other sublanes living
|
| MIRPrinter.cpp | 302 yaml::VirtualRegisterDefinition VReg;
303 VReg.ID = I;
306 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
309 printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
310 MF.VirtualRegisters.push_back(VReg);
|
| MachineCSE.cpp | 852 Register VReg = MI->getOperand(0).getReg();
853 Register NewReg = MRI->cloneVirtualRegister(VReg);
854 if (!isProfitableToCSE(NewReg, VReg, CMBB, MI))
|
| RegAllocPBQP.cpp | 161 /// Finds the initial set of vreg intervals to allocate.
167 /// Spill the given VReg.
168 void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
333 Register VReg = G.getNodeMetadata(NId).getVReg();
334 LiveInterval &LI = LIS.getInterval(VReg);
604 Register VReg = Worklist.back();
607 LiveInterval &VRegLI = LIS.getInterval(VReg);
617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
623 // Compute an initial allowed set for the current vreg.
654 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller)
[all...] |
| TailDuplicator.cpp | 196 unsigned VReg = SSAUpdateVRs[i];
197 SSAUpdate.Initialize(VReg);
201 MachineInstr *DefMI = MRI->getVRegDef(VReg);
205 SSAUpdate.AddAvailableValue(DefBB, VReg);
210 SSAUpdateVals.find(VReg);
218 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegNumbering.cpp | 79 LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg()
92 unsigned VReg = Register::index2VirtReg(VRegIdx);
94 if (MRI.use_empty(VReg))
97 if (MFI.isVRegStackified(VReg)) {
98 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg "
100 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++);
103 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg) {
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n")
[all...] |
| WebAssemblyReplacePhysRegs.cpp | 87 unsigned VReg = WebAssembly::NoRegister;
91 if (VReg == WebAssembly::NoRegister) {
92 VReg = MRI.createVirtualRegister(RC);
96 FI->setFrameBaseVreg(VReg);
98 dbgs() << "replacing preg " << PReg << " with " << VReg << " ("
99 << Register::virtReg2Index(VReg) << ")\n";
103 MO.setReg(VReg);
|
| WebAssemblyRegColoring.cpp | 64 // Compute the total spill weight for VReg.
67 unsigned VReg) {
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
101 unsigned VReg = Register::index2VirtReg(I);
102 if (MFI.isVRegStackified(VReg))
105 if (MRI->use_empty(VReg))
108 LiveInterval *LI = &Liveness->getInterval(VReg);
110 LI->setWeight(computeWeight(MRI, MBFI, VReg));
163 LLVM_DEBUG(dbgs() << "Assigning vreg" << Register::virtReg2Index(LI->reg())
164 << " to vreg" << Register::virtReg2Index(New) << "\n")
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| Utils.h | 164 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
165 Optional<APInt> getConstantVRegVal(Register VReg,
168 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
170 Optional<int64_t> getConstantVRegSExtVal(Register VReg,
177 Register VReg;
179 /// If \p VReg is defined by a statically evaluable chain of
189 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
193 const ConstantInt *getConstantIntVRegVal(Register VReg,
195 const ConstantFP* getConstantFPVRegVal(Register VReg,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| NVPTXInstPrinter.cpp | 71 unsigned VReg = RegNo & 0x0FFFFFFF;
72 OS << VReg;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InstructionSelect.cpp | 238 // that the size of the now-constrained vreg is unchanged and that it has a
241 unsigned VReg = Register::index2VirtReg(I);
244 if (!MRI.def_empty(VReg))
245 MI = &*MRI.def_instr_begin(VReg);
246 else if (!MRI.use_empty(VReg))
247 MI = &*MRI.use_instr_begin(VReg);
251 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
254 "VReg has no regclass after selection", *MI);
258 const LLT Ty = MRI.getType(VReg);
262 "VReg's low-level type and register class have different sizes", *MI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 103 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
104 // the CopyToReg'd destination register instead of creating a new vreg.
208 // is a vreg in the same register class, use the CopyToReg'd destination
209 // register instead of creating a new vreg.
283 Register VReg = MRI->createVirtualRegister(RC);
285 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
286 return VReg;
309 Register VReg = getVR(Op, VRBaseMap);
317 // shrink VReg's register class within reason. For example, if VReg == GR3
[all...] |
| SDNodeDbgValue.h | 36 VREG = 3 ///< Value is a virtual register.
64 /// Returns the Virtual Register for a VReg
66 assert(kind == VREG);
67 return u.VReg;
76 static SDDbgOperand fromVReg(unsigned VReg) {
77 return SDDbgOperand(VReg, VREG);
92 case VREG:
109 unsigned VReg; ///< Valid for registers.
121 assert((Kind == VREG || Kind == FRAMEIX) &
[all...] |
| FunctionLoweringInfo.cpp | 381 /// consecutive vreg numbers and return the first assigned number.
544 Register &VReg = I.first->second;
546 VReg = MRI.createVirtualRegister(RC);
547 assert(VReg && "null vreg in exception pointer table!");
548 return VReg;
552 FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
567 return VirtReg2Value.lookup(Vreg);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 68 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
89 const Value *getValueFromVirtualReg(Register Vreg);
103 // copy from vreg.
104 VReg,
|
| CallingConvLower.h | 168 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT)
169 : VReg(VReg), PReg(PReg), VT(VT) {}
170 Register VReg;
|
| RegAllocPBQP.h | 93 /// Holds a vector of the allowed physical regs for a vreg.
148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) {
149 VRegToNodeId[VReg.id()] = NId;
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const {
153 auto VRegItr = VRegToNodeId.find(VReg);
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
202 void setVReg(Register VReg) { this->VReg = VReg; }
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/ |
| MIParser.h | 39 bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
44 Register VReg;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SILowerSGPRSpills.cpp | 359 Register VReg =
362 TRI->isAGPR(MRI, VReg))) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 265 Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);
268 CurDAG->getCopyToReg(CopyFromRegOp, dl, VReg, CopyFromRegOp);
271 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL));
294 Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);
296 SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op);
298 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 441 // Create vreg = A2_tfrsi #Acc; mem[hw] = vreg
444 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
445 MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)
460 .addReg(VReg, RegState::Kill);
|
