1 //===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file a TargetTransformInfo::Concept conforming object specific to the 10 /// PPC target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H 18 19 #include "PPCTargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/BasicTTIImpl.h" 22 #include "llvm/CodeGen/TargetLowering.h" 23 24 namespace llvm { 25 26 class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> { 27 typedef BasicTTIImplBase<PPCTTIImpl> BaseT; 28 typedef TargetTransformInfo TTI; 29 friend BaseT; 30 31 const PPCSubtarget *ST; 32 const PPCTargetLowering *TLI; 33 34 const PPCSubtarget *getST() const { return ST; } 35 const PPCTargetLowering *getTLI() const { return TLI; } 36 bool mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, 37 SmallPtrSetImpl<const Value *> &Visited); 38 39 public: 40 explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F) 41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 42 TLI(ST->getTargetLowering()) {} 43 44 Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, 45 IntrinsicInst &II) const; 46 47 /// \name Scalar TTI Implementations 48 /// @{ 49 50 using BaseT::getIntImmCost; 51 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, 52 TTI::TargetCostKind CostKind); 53 54 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, 55 const APInt &Imm, Type *Ty, 56 TTI::TargetCostKind CostKind, 57 Instruction *Inst = nullptr); 58 InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 59 const APInt &Imm, Type *Ty, 60 TTI::TargetCostKind CostKind); 61 62 InstructionCost getUserCost(const User *U, ArrayRef<const Value *> Operands, 63 TTI::TargetCostKind CostKind); 64 65 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); 66 bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, 67 AssumptionCache &AC, 68 TargetLibraryInfo *LibInfo, 69 HardwareLoopInfo &HWLoopInfo); 70 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, 71 DominatorTree *DT, AssumptionCache *AC, 72 TargetLibraryInfo *LibInfo); 73 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info); 74 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 75 TTI::UnrollingPreferences &UP); 76 void getPeelingPreferences(Loop *L, ScalarEvolution &SE, 77 TTI::PeelingPreferences &PP); 78 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, 79 TargetTransformInfo::LSRCost &C2); 80 bool isNumRegsMajorCostOfLSR(); 81 bool shouldBuildRelLookupTables() const; 82 /// @} 83 84 /// \name Vector TTI Implementations 85 /// @{ 86 bool useColdCCForColdCall(Function &F); 87 bool enableAggressiveInterleaving(bool LoopHasReductions); 88 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, 89 bool IsZeroCmp) const; 90 bool enableInterleavedAccessVectorization(); 91 92 enum PPCRegisterClass { 93 GPRRC, FPRRC, VRRC, VSXRC 94 }; 95 unsigned getNumberOfRegisters(unsigned ClassID) const; 96 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; 97 const char* getRegisterClassName(unsigned ClassID) const; 98 TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; 99 unsigned getCacheLineSize() const override; 100 unsigned getPrefetchDistance() const override; 101 unsigned getMaxInterleaveFactor(unsigned VF); 102 InstructionCost vectorCostAdjustment(InstructionCost Cost, unsigned Opcode, 103 Type *Ty1, Type *Ty2); 104 InstructionCost getArithmeticInstrCost( 105 unsigned Opcode, Type *Ty, 106 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, 107 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, 108 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, 109 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 110 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, 111 ArrayRef<const Value *> Args = ArrayRef<const Value *>(), 112 const Instruction *CxtI = nullptr); 113 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, 114 ArrayRef<int> Mask, int Index, Type *SubTp); 115 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 116 TTI::CastContextHint CCH, 117 TTI::TargetCostKind CostKind, 118 const Instruction *I = nullptr); 119 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, 120 const Instruction *I = nullptr); 121 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 122 CmpInst::Predicate VecPred, 123 TTI::TargetCostKind CostKind, 124 const Instruction *I = nullptr); 125 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, 126 unsigned Index); 127 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, 128 MaybeAlign Alignment, unsigned AddressSpace, 129 TTI::TargetCostKind CostKind, 130 const Instruction *I = nullptr); 131 InstructionCost getInterleavedMemoryOpCost( 132 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 133 Align Alignment, unsigned AddressSpace, 134 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 135 bool UseMaskForCond = false, bool UseMaskForGaps = false); 136 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 137 TTI::TargetCostKind CostKind); 138 bool areFunctionArgsABICompatible(const Function *Caller, 139 const Function *Callee, 140 SmallPtrSetImpl<Argument *> &Args) const; 141 /// @} 142 }; 143 144 } // end namespace llvm 145 146 #endif 147
Indexes created Sun Jun 21 00:25:28 UTC 2026