| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 518 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
541 bool isFPImmLegal(const APFloat &Imm, EVT VT,
546 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
550 EVT VT) const override;
623 EVT VT) const override;
626 bool generateFMAsInMachineCombiner(EVT VT,
645 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
649 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
670 getPreferredVectorAction(MVT VT) const override;
700 bool isIntDivCheap(EVT VT, AttributeList Attr) const override
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 95 MVT ArgVT = Ins[i].VT;
108 MVT VT = Outs[i].VT;
110 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
122 MVT VT = Outs[i].VT;
124 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
135 MVT ArgVT = Outs[i].VT;
[all...] |
| ValueTypes.cpp | 38 EVT VT;
39 VT.LLVMTy = IntegerType::get(Context, BitWidth);
40 assert(VT.isExtended() && "Type is not extended!");
41 return VT;
44 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
48 VectorType::get(VT.getTypeForEVT(Context), NumElements, IsScalable);
53 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) {
55 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), EC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MVELaneInterleavingPass.cpp | 156 auto *VT = cast<FixedVectorType>(Start->getType());
288 unsigned NumElts = VT->getNumElements();
289 unsigned BaseElts = VT->getScalarSizeInBits() == 16
291 : (VT->getScalarSizeInBits() == 8 ? 16 : 0);
297 VT->getScalarSizeInBits() * 2) {
302 if (I->getOperand(0)->getType() != VT) {
307 if (I->getType() != VT) {
|
| ARMSelectionDAGInfo.cpp | 199 EVT VT = MVT::i32;
258 VT = getRemainingValueType(BytesLeft);
260 Loads[i] = DAG.getLoad(VT, dl, Chain,
275 VT = getRemainingValueType(BytesLeft);
|
| ARMCallLowering.cpp | 70 EVT VT = TLI.getValueType(DL, T, true);
71 if (!VT.isSimple() || VT.isVector() ||
72 !(VT.isInteger() || VT.isFloatingPoint()))
75 unsigned VTSize = VT.getSimpleVT().getSizeInBits();
79 return VT.isFloatingPoint();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelDAGToDAG.cpp | 283 EVT VT = Node->getValueType(0);
286 if (VT == MVT::i32) {
319 EVT VT = Node->getValueType(0);
320 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
323 CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
326 ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VT, TFI, Imm));
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 104 Record *VT = VTs->getElementAsRecord(i);
106 O << "LocVT == " << getEnumName(getValueType(VT));
|
| CodeGenTarget.cpp | 717 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
718 if (MVT(VT).isOverloaded()) {
719 OverloadedVTs.push_back(VT);
730 MVT::SimpleValueType VT;
735 VT = OverloadedVTs[MatchTy];
741 VT == MVT::iAny || VT == MVT::vAny) &&
744 VT = getValueType(TyEl->getValueAsDef("VT"));
[all...] |
| /src/external/bsd/byacc/dist/test/btyacc/ |
| ok_syntax1.tab.h | 20 #define VT 272
|
| /src/external/bsd/byacc/dist/test/yacc/ |
| ok_syntax1.tab.h | 17 #define VT 272
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 107 MVT VT = Node->getSimpleValueType(ResNo);
110 if (TLI->isTypeLegal(VT))
111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
130 MVT VT = Node->getSimpleValueType(Op.getResNo());
131 if (VT == MVT::Other || VT == MVT::Glue)
160 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
166 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
170 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
449 MVT VT, bool isDivergent, const DebugLoc &DL)
[all...] |
| ResourcePriorityQueue.cpp | 97 MVT VT = ScegN->getSimpleValueType(i);
98 if (TLI->isTypeLegal(VT)
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
136 if (TLI->isTypeLegal(VT)
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
331 MVT VT = SU->getNode()->getSimpleValueType(i);
332 if (TLI->isTypeLegal(VT)
333 && TLI->getRegClassFor(VT)
334 && TLI->getRegClassFor(VT)->getID() == RCId
[all...] |
| SelectionDAGPrinter.cpp | 98 EVT VT = Op.getValueType();
99 if (VT == MVT::Glue)
101 else if (VT == MVT::Other)
|
| LegalizeDAG.cpp | 97 EVT getSetCCResultType(EVT VT) const {
98 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
257 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
259 unsigned NumMaskElts = VT.getVectorNumElements();
296 EVT VT = CFP->getValueType(0);
299 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
301 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
305 EVT OrigVT = VT;
[all...] |
| /src/external/bsd/ntp/dist/include/ |
| ascii.h | 54 #define VT 11
|
| /src/external/apache2/llvm/dist/clang/lib/AST/ |
| PrintfFormatString.cpp | 732 const VectorType *VT = QT->getAs<VectorType>();
733 if (VT) {
734 QT = VT->getElementType();
736 VectorNumElts = OptionalAmount(VT->getNumElements());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPULowerKernelArguments.cpp | 136 auto *VT = dyn_cast<FixedVectorType>(ArgTy);
137 bool IsV3 = VT && VT->getNumElements() == 3;
168 V4Ty = FixedVectorType::get(VT->getElementType(), 4);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 226 EVT VT = Node->getValueType(0);
227 assert(VT.isVector() && "Should only be called for vectors.");
256 ISD::SUB, DL, VT, {CurDAG->getConstant(0, DL, VT), C});
258 SDValue NewNode = CurDAG->getNode(ISD::SUB, DL, VT, X, NegC);
|
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 693 const VectorType *VT = cast<VectorType>(Ty);
694 ResultType = llvm::FixedVectorType::get(ConvertType(VT->getElementType()),
695 VT->getNumElements());
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| MachineValueType.h | 448 "Simple vector VT not representable by simple integer vector VT!");
452 /// Return a VT for a vector type whose attributes match ourselves
457 "Simple vector VT not representable by simple integer vector VT!");
470 /// Return a VT for a vector type with the same element type but
1043 /// Return true if we know at compile time this has more bits than VT.
1044 bool knownBitsGT(MVT VT) const {
1045 return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits());
1049 /// bits as VT
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 41 unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT);
107 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT();
110 if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) {
124 MVT VT = LD->getMemoryVT().getSimpleVT();
138 switch (VT.SimpleTy) {
159 SDNode *ResNode = CurDAG->getMachineNode(Opcode, SDLoc(N), VT,
169 MVT VT) {
180 switch (VT.SimpleTy) {
340 EVT VT = ST->getValue().getValueType()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 228 EVT VT = Node->getValueType(0);
229 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
232 CurDAG->SelectNodeTo(Node, Opc, VT, TFI);
235 ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyAsmPrinter.cpp | 111 static char getInvokeSig(wasm::ValType VT) {
112 switch (VT) {
137 for (auto VT : Sig->Returns)
138 Ret += getInvokeSig(VT);
191 MVT VT = TLI.getRegisterType(GV->getParent()->getContext(), VTs[0]);
193 wasm::ValType Type = WebAssembly::toValType(VT);
|
| /src/sys/arch/amiga/dev/ |
| kbdmap.h | 43 #define VT 11
|
