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    Searched defs:ValueVT (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FunctionLoweringInfo.cpp 394 EVT ValueVT = ValueVTs[Value];
395 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
397 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
LegalizeTypesGeneric.cpp 256 EVT ValueVT = LD->getValueType(0);
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
281 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
466 EVT ValueVT = St->getValue().getValueType();
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
478 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
LegalizeVectorTypes.cpp 4916 EVT ValueVT = StVal.getValueType();
4918 ValueVT.getVectorElementType(),
SelectionDAGBuilder.cpp 156 MVT PartVT, EVT ValueVT, const Value *V,
161 /// larger than ValueVT then AssertOp can be used to specify whether the extra
162 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
166 MVT PartVT, EVT ValueVT, const Value *V,
172 PartVT, ValueVT, CC))
175 if (ValueVT.isVector())
176 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
184 if (ValueVT.isInteger()) {
186 unsigned ValueBits = ValueVT.getSizeInBits();
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 148 EVT ValueVT = LD->getValueType(0);
149 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
153 ValueVT = MVT::i32;
157 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT,
169 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other,
471 EVT ValueVT = Value.getValueType();
518 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 5721 MVT ValueVT = Node->getSimpleValueType(0);
5727 if (!ValueVT.isVector() || !MaskVT.isVector())
5730 unsigned NumElts = ValueVT.getVectorNumElements();
5731 MVT ValueSVT = ValueVT.getVectorElementType();
5764 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() &&
5795 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other);
5818 MVT ValueVT = Value.getSimpleValueType();
5823 if (!ValueVT.isVector())
5826 unsigned NumElts = ValueVT.getVectorNumElements();
5827 MVT ValueSVT = ValueVT.getVectorElementType()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 8528 EVT ValueVT = Val.getValueType();
8529 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) {
8541 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
8543 EVT ValueEltVT = ValueVT.getVectorElementType();
8545 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize();
8568 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
8570 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) {
8580 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
8583 EVT ValueEltVT = ValueVT.getVectorElementType();
8585 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 4216 EVT ValueVT = Val.getValueType();
4217 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4219 unsigned ValueBits = ValueVT.getSizeInBits();
4232 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4234 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4236 unsigned ValueBits = ValueVT.getSizeInBits();
4242 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);

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