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      1 /*	$NetBSD: smu72_discrete.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2017 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef SMU72_DISCRETE_H
     27 #define SMU72_DISCRETE_H
     28 
     29 #include "smu72.h"
     30 
     31 #if !defined(SMC_MICROCODE)
     32 #pragma pack(push, 1)
     33 #endif
     34 
     35 struct SMIO_Pattern {
     36 	uint16_t Voltage;
     37 	uint8_t  Smio;
     38 	uint8_t  padding;
     39 };
     40 
     41 typedef struct SMIO_Pattern SMIO_Pattern;
     42 
     43 struct SMIO_Table {
     44 	SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
     45 };
     46 
     47 typedef struct SMIO_Table SMIO_Table;
     48 
     49 struct SMU72_Discrete_GraphicsLevel {
     50 	SMU_VoltageLevel MinVoltage;
     51 
     52 	uint32_t    SclkFrequency;
     53 
     54 	uint8_t     pcieDpmLevel;
     55 	uint8_t     DeepSleepDivId;
     56 	uint16_t    ActivityLevel;
     57 
     58 	uint32_t    CgSpllFuncCntl3;
     59 	uint32_t    CgSpllFuncCntl4;
     60 	uint32_t    SpllSpreadSpectrum;
     61 	uint32_t    SpllSpreadSpectrum2;
     62 	uint32_t    CcPwrDynRm;
     63 	uint32_t    CcPwrDynRm1;
     64 	uint8_t     SclkDid;
     65 	uint8_t     DisplayWatermark;
     66 	uint8_t     EnabledForActivity;
     67 	uint8_t     EnabledForThrottle;
     68 	uint8_t     UpHyst;
     69 	uint8_t     DownHyst;
     70 	uint8_t     VoltageDownHyst;
     71 	uint8_t     PowerThrottle;
     72 };
     73 
     74 typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
     75 
     76 struct SMU72_Discrete_ACPILevel {
     77 	uint32_t    Flags;
     78 	SMU_VoltageLevel MinVoltage;
     79 	uint32_t    SclkFrequency;
     80 	uint8_t     SclkDid;
     81 	uint8_t     DisplayWatermark;
     82 	uint8_t     DeepSleepDivId;
     83 	uint8_t     padding;
     84 	uint32_t    CgSpllFuncCntl;
     85 	uint32_t    CgSpllFuncCntl2;
     86 	uint32_t    CgSpllFuncCntl3;
     87 	uint32_t    CgSpllFuncCntl4;
     88 	uint32_t    SpllSpreadSpectrum;
     89 	uint32_t    SpllSpreadSpectrum2;
     90 	uint32_t    CcPwrDynRm;
     91 	uint32_t    CcPwrDynRm1;
     92 };
     93 
     94 typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
     95 
     96 struct SMU72_Discrete_Ulv {
     97 	uint32_t    CcPwrDynRm;
     98 	uint32_t    CcPwrDynRm1;
     99 	uint16_t    VddcOffset;
    100 	uint8_t     VddcOffsetVid;
    101 	uint8_t     VddcPhase;
    102 	uint32_t    Reserved;
    103 };
    104 
    105 typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
    106 
    107 struct SMU72_Discrete_MemoryLevel {
    108 	SMU_VoltageLevel MinVoltage;
    109 	uint32_t    MinMvdd;
    110 
    111 	uint32_t    MclkFrequency;
    112 
    113 	uint8_t     EdcReadEnable;
    114 	uint8_t     EdcWriteEnable;
    115 	uint8_t     RttEnable;
    116 	uint8_t     StutterEnable;
    117 
    118 	uint8_t     StrobeEnable;
    119 	uint8_t     StrobeRatio;
    120 	uint8_t     EnabledForThrottle;
    121 	uint8_t     EnabledForActivity;
    122 
    123 	uint8_t     UpHyst;
    124 	uint8_t     DownHyst;
    125 	uint8_t     VoltageDownHyst;
    126 	uint8_t     padding;
    127 
    128 	uint16_t    ActivityLevel;
    129 	uint8_t     DisplayWatermark;
    130 	uint8_t     padding1;
    131 
    132 	uint32_t    MpllFuncCntl;
    133 	uint32_t    MpllFuncCntl_1;
    134 	uint32_t    MpllFuncCntl_2;
    135 	uint32_t    MpllAdFuncCntl;
    136 	uint32_t    MpllDqFuncCntl;
    137 	uint32_t    MclkPwrmgtCntl;
    138 	uint32_t    DllCntl;
    139 	uint32_t    MpllSs1;
    140 	uint32_t    MpllSs2;
    141 };
    142 
    143 typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
    144 
    145 struct SMU72_Discrete_LinkLevel {
    146 	uint8_t     PcieGenSpeed;           /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
    147 	uint8_t     PcieLaneCount;          /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
    148 	uint8_t     EnabledForActivity;
    149 	uint8_t     SPC;
    150 	uint32_t    DownThreshold;
    151 	uint32_t    UpThreshold;
    152 	uint32_t    Reserved;
    153 };
    154 
    155 typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
    156 
    157 /* MC ARB DRAM Timing registers. */
    158 struct SMU72_Discrete_MCArbDramTimingTableEntry {
    159 	uint32_t McArbDramTiming;
    160 	uint32_t McArbDramTiming2;
    161 	uint8_t  McArbBurstTime;
    162 	uint8_t  padding[3];
    163 };
    164 
    165 typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
    166 
    167 struct SMU72_Discrete_MCArbDramTimingTable {
    168 	SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
    169 };
    170 
    171 typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
    172 
    173 /* UVD VCLK/DCLK state (level) definition. */
    174 struct SMU72_Discrete_UvdLevel {
    175 	uint32_t VclkFrequency;
    176 	uint32_t DclkFrequency;
    177 	SMU_VoltageLevel MinVoltage;
    178 	uint8_t  VclkDivider;
    179 	uint8_t  DclkDivider;
    180 	uint8_t  padding[2];
    181 };
    182 
    183 typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
    184 
    185 /* Clocks for other external blocks (VCE, ACP, SAMU). */
    186 struct SMU72_Discrete_ExtClkLevel {
    187 	uint32_t Frequency;
    188 	SMU_VoltageLevel MinVoltage;
    189 	uint8_t  Divider;
    190 	uint8_t  padding[3];
    191 };
    192 
    193 typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
    194 
    195 struct SMU72_Discrete_StateInfo {
    196 	uint32_t SclkFrequency;
    197 	uint32_t MclkFrequency;
    198 	uint32_t VclkFrequency;
    199 	uint32_t DclkFrequency;
    200 	uint32_t SamclkFrequency;
    201 	uint32_t AclkFrequency;
    202 	uint32_t EclkFrequency;
    203 	uint16_t MvddVoltage;
    204 	uint16_t padding16;
    205 	uint8_t  DisplayWatermark;
    206 	uint8_t  McArbIndex;
    207 	uint8_t  McRegIndex;
    208 	uint8_t  SeqIndex;
    209 	uint8_t  SclkDid;
    210 	int8_t   SclkIndex;
    211 	int8_t   MclkIndex;
    212 	uint8_t  PCIeGen;
    213 
    214 };
    215 
    216 typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
    217 
    218 struct SMU72_Discrete_DpmTable {
    219 	/* Multi-DPM controller settings */
    220 	SMU72_PIDController                  GraphicsPIDController;
    221 	SMU72_PIDController                  MemoryPIDController;
    222 	SMU72_PIDController                  LinkPIDController;
    223 
    224 	uint32_t                            SystemFlags;
    225 
    226 	/* SMIO masks for voltage and phase controls */
    227 	uint32_t                            VRConfig;
    228 	uint32_t                            SmioMask1;
    229 	uint32_t                            SmioMask2;
    230 	SMIO_Table                          SmioTable1;
    231 	SMIO_Table                          SmioTable2;
    232 
    233 	uint32_t                            VddcLevelCount;
    234 	uint32_t                            VddciLevelCount;
    235 	uint32_t                            VddGfxLevelCount;
    236 	uint32_t                            MvddLevelCount;
    237 
    238 	uint16_t                            VddcTable[SMU72_MAX_LEVELS_VDDC];
    239 	uint16_t                            VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
    240 	uint16_t                            VddciTable[SMU72_MAX_LEVELS_VDDCI];
    241 
    242 	uint8_t                             BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
    243 	uint8_t                             BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
    244 	uint8_t                             BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
    245 
    246 	uint8_t                             BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
    247 	uint8_t                             BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
    248 	uint8_t                             BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
    249 
    250 	uint8_t                             GraphicsDpmLevelCount;
    251 	uint8_t                             MemoryDpmLevelCount;
    252 	uint8_t                             LinkLevelCount;
    253 	uint8_t                             MasterDeepSleepControl;
    254 
    255 	uint8_t                             UvdLevelCount;
    256 	uint8_t                             VceLevelCount;
    257 	uint8_t                             AcpLevelCount;
    258 	uint8_t                             SamuLevelCount;
    259 
    260 	uint8_t                             ThermOutGpio;
    261 	uint8_t                             ThermOutPolarity;
    262 	uint8_t                             ThermOutMode;
    263 	uint8_t                             DPMFreezeAndForced;
    264 	uint32_t                            Reserved[4];
    265 
    266 	/* State table entries for each DPM state */
    267 	SMU72_Discrete_GraphicsLevel        GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
    268 	SMU72_Discrete_MemoryLevel          MemoryACPILevel;
    269 	SMU72_Discrete_MemoryLevel          MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
    270 	SMU72_Discrete_LinkLevel            LinkLevel[SMU72_MAX_LEVELS_LINK];
    271 	SMU72_Discrete_ACPILevel            ACPILevel;
    272 	SMU72_Discrete_UvdLevel             UvdLevel[SMU72_MAX_LEVELS_UVD];
    273 	SMU72_Discrete_ExtClkLevel          VceLevel[SMU72_MAX_LEVELS_VCE];
    274 	SMU72_Discrete_ExtClkLevel          AcpLevel[SMU72_MAX_LEVELS_ACP];
    275 	SMU72_Discrete_ExtClkLevel          SamuLevel[SMU72_MAX_LEVELS_SAMU];
    276 	SMU72_Discrete_Ulv                  Ulv;
    277 
    278 	uint32_t                            SclkStepSize;
    279 	uint32_t                            Smio[SMU72_MAX_ENTRIES_SMIO];
    280 
    281 	uint8_t                             UvdBootLevel;
    282 	uint8_t                             VceBootLevel;
    283 	uint8_t                             AcpBootLevel;
    284 	uint8_t                             SamuBootLevel;
    285 
    286 	uint8_t                             GraphicsBootLevel;
    287 	uint8_t                             GraphicsVoltageChangeEnable;
    288 	uint8_t                             GraphicsThermThrottleEnable;
    289 	uint8_t                             GraphicsInterval;
    290 
    291 	uint8_t                             VoltageInterval;
    292 	uint8_t                             ThermalInterval;
    293 	uint16_t                            TemperatureLimitHigh;
    294 
    295 	uint16_t                            TemperatureLimitLow;
    296 	uint8_t                             MemoryBootLevel;
    297 	uint8_t                             MemoryVoltageChangeEnable;
    298 
    299 	uint16_t                            BootMVdd;
    300 	uint8_t                             MemoryInterval;
    301 	uint8_t                             MemoryThermThrottleEnable;
    302 
    303 	uint16_t                            VoltageResponseTime;
    304 	uint16_t                            PhaseResponseTime;
    305 
    306 	uint8_t                             PCIeBootLinkLevel;
    307 	uint8_t                             PCIeGenInterval;
    308 	uint8_t                             DTEInterval;
    309 	uint8_t                             DTEMode;
    310 
    311 	uint8_t                             SVI2Enable;
    312 	uint8_t                             VRHotGpio;
    313 	uint8_t                             AcDcGpio;
    314 	uint8_t                             ThermGpio;
    315 
    316 	uint16_t                            PPM_PkgPwrLimit;
    317 	uint16_t                            PPM_TemperatureLimit;
    318 
    319 	uint16_t                            DefaultTdp;
    320 	uint16_t                            TargetTdp;
    321 
    322 	uint16_t                            FpsHighThreshold;
    323 	uint16_t                            FpsLowThreshold;
    324 
    325 	uint16_t                            BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
    326 	uint16_t                            BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
    327 
    328 	uint8_t                             DTEAmbientTempBase;
    329 	uint8_t                             DTETjOffset;
    330 	uint8_t                             GpuTjMax;
    331 	uint8_t                             GpuTjHyst;
    332 
    333 	SMU_VoltageLevel                    BootVoltage;
    334 
    335 	uint32_t                            BAPM_TEMP_GRADIENT;
    336 
    337 	uint32_t                            LowSclkInterruptThreshold;
    338 	uint32_t                            VddGfxReChkWait;
    339 
    340 	uint8_t                             ClockStretcherAmount;
    341 
    342 	uint8_t                             Sclk_CKS_masterEn0_7;
    343 	uint8_t                             Sclk_CKS_masterEn8_15;
    344 	uint8_t                             padding[1];
    345 
    346 	uint8_t                             Sclk_voltageOffset[8];
    347 
    348 	SMU_ClockStretcherDataTable         ClockStretcherDataTable;
    349 	SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
    350 };
    351 
    352 typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
    353 
    354 /* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
    355 #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
    356 #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
    357 
    358 struct SMU72_Discrete_MCRegisterAddress {
    359 	uint16_t s0;
    360 	uint16_t s1;
    361 };
    362 
    363 typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
    364 
    365 struct SMU72_Discrete_MCRegisterSet {
    366 	uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
    367 };
    368 
    369 typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
    370 
    371 struct SMU72_Discrete_MCRegisters {
    372 	uint8_t                             last;
    373 	uint8_t                             reserved[3];
    374 	SMU72_Discrete_MCRegisterAddress     address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
    375 	SMU72_Discrete_MCRegisterSet         data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
    376 };
    377 
    378 typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
    379 
    380 
    381 /* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
    382 
    383 struct SMU72_Discrete_FanTable {
    384 	uint16_t FdoMode;
    385 	int16_t  TempMin;
    386 	int16_t  TempMed;
    387 	int16_t  TempMax;
    388 	int16_t  Slope1;
    389 	int16_t  Slope2;
    390 	int16_t  FdoMin;
    391 	int16_t  HystUp;
    392 	int16_t  HystDown;
    393 	int16_t  HystSlope;
    394 	int16_t  TempRespLim;
    395 	int16_t  TempCurr;
    396 	int16_t  SlopeCurr;
    397 	int16_t  PwmCurr;
    398 	uint32_t RefreshPeriod;
    399 	int16_t  FdoMax;
    400 	uint8_t  TempSrc;
    401 	int8_t   FanControl_GL_Flag;
    402 };
    403 
    404 typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
    405 
    406 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
    407 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
    408 
    409 struct SMU7_MclkDpmScoreboard {
    410 
    411 	uint32_t PercentageBusy;
    412 
    413 	int32_t  PIDError;
    414 	int32_t  PIDIntegral;
    415 	int32_t  PIDOutput;
    416 
    417 	uint32_t SigmaDeltaAccum;
    418 	uint32_t SigmaDeltaOutput;
    419 	uint32_t SigmaDeltaLevel;
    420 
    421 	uint32_t UtilizationSetpoint;
    422 
    423 	uint8_t  TdpClampMode;
    424 	uint8_t  TdcClampMode;
    425 	uint8_t  ThermClampMode;
    426 	uint8_t  VoltageBusy;
    427 
    428 	int8_t   CurrLevel;
    429 	int8_t   TargLevel;
    430 	uint8_t  LevelChangeInProgress;
    431 	uint8_t  UpHyst;
    432 
    433 	uint8_t  DownHyst;
    434 	uint8_t  VoltageDownHyst;
    435 	uint8_t  DpmEnable;
    436 	uint8_t  DpmRunning;
    437 
    438 	uint8_t  DpmForce;
    439 	uint8_t  DpmForceLevel;
    440 	uint8_t  DisplayWatermark;
    441 	uint8_t  McArbIndex;
    442 
    443 	uint32_t MinimumPerfMclk;
    444 
    445 	uint8_t  AcpiReq;
    446 	uint8_t  AcpiAck;
    447 	uint8_t  MclkSwitchInProgress;
    448 	uint8_t  MclkSwitchCritical;
    449 
    450 	uint8_t  IgnoreVBlank;
    451 	uint8_t  TargetMclkIndex;
    452 	uint8_t  TargetMvddIndex;
    453 	uint8_t  MclkSwitchResult;
    454 
    455 	uint16_t VbiFailureCount;
    456 	uint8_t  VbiWaitCounter;
    457 	uint8_t  EnabledLevelsChange;
    458 
    459 	uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
    460 	uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
    461 
    462 	void     (*TargetStateCalculator)(uint8_t);
    463 	void     (*SavedTargetStateCalculator)(uint8_t);
    464 
    465 	uint16_t AutoDpmInterval;
    466 	uint16_t AutoDpmRange;
    467 
    468 	uint16_t VbiTimeoutCount;
    469 	uint16_t MclkSwitchingTime;
    470 
    471 	uint8_t  fastSwitch;
    472 	uint8_t  Save_PIC_VDDGFX_EXIT;
    473 	uint8_t  Save_PIC_VDDGFX_ENTER;
    474 	uint8_t  padding;
    475 
    476 };
    477 
    478 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
    479 
    480 struct SMU7_UlvScoreboard {
    481 	uint8_t     EnterUlv;
    482 	uint8_t     ExitUlv;
    483 	uint8_t     UlvActive;
    484 	uint8_t     WaitingForUlv;
    485 	uint8_t     UlvEnable;
    486 	uint8_t     UlvRunning;
    487 	uint8_t     UlvMasterEnable;
    488 	uint8_t     padding;
    489 	uint32_t    UlvAbortedCount;
    490 	uint32_t    UlvTimeStamp;
    491 };
    492 
    493 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
    494 
    495 struct VddgfxSavedRegisters {
    496 	uint32_t GPU_DBG[3];
    497 	uint32_t MEC_BaseAddress_Hi;
    498 	uint32_t MEC_BaseAddress_Lo;
    499 	uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
    500 	uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
    501 	uint32_t CP_INT_CNTL;
    502 };
    503 
    504 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
    505 
    506 struct SMU7_VddGfxScoreboard {
    507 	uint8_t     VddGfxEnable;
    508 	uint8_t     VddGfxActive;
    509 	uint8_t     VPUResetOccured;
    510 	uint8_t     padding;
    511 
    512 	uint32_t    VddGfxEnteredCount;
    513 	uint32_t    VddGfxAbortedCount;
    514 
    515 	uint32_t    VddGfxVid;
    516 
    517 	VddgfxSavedRegisters SavedRegisters;
    518 };
    519 
    520 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
    521 
    522 struct SMU7_TdcLimitScoreboard {
    523 	uint8_t  Enable;
    524 	uint8_t  Running;
    525 	uint16_t Alpha;
    526 	uint32_t FilteredIddc;
    527 	uint32_t IddcLimit;
    528 	uint32_t IddcHyst;
    529 	SMU7_HystController_Data HystControllerData;
    530 };
    531 
    532 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
    533 
    534 struct SMU7_PkgPwrLimitScoreboard {
    535 	uint8_t  Enable;
    536 	uint8_t  Running;
    537 	uint16_t Alpha;
    538 	uint32_t FilteredPkgPwr;
    539 	uint32_t Limit;
    540 	uint32_t Hyst;
    541 	uint32_t LimitFromDriver;
    542 	SMU7_HystController_Data HystControllerData;
    543 };
    544 
    545 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
    546 
    547 struct SMU7_BapmScoreboard {
    548 	uint32_t source_powers[SMU72_DTE_SOURCES];
    549 	uint32_t source_powers_last[SMU72_DTE_SOURCES];
    550 	int32_t entity_temperatures[SMU72_NUM_GPU_TES];
    551 	int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
    552 	int32_t Limit;
    553 	int32_t Hyst;
    554 	int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
    555 	int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
    556 	uint16_t ConfigTDPPowerScalar;
    557 	uint16_t FanSpeedPowerScalar;
    558 	uint16_t OverDrivePowerScalar;
    559 	uint16_t OverDriveLimitScalar;
    560 	uint16_t FinalPowerScalar;
    561 	uint8_t VariantID;
    562 	uint8_t spare997;
    563 
    564 	SMU7_HystController_Data HystControllerData;
    565 
    566 	int32_t temperature_gradient_slope;
    567 	int32_t temperature_gradient;
    568 	uint32_t measured_temperature;
    569 };
    570 
    571 
    572 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
    573 
    574 struct SMU7_AcpiScoreboard {
    575 	uint32_t SavedInterruptMask[2];
    576 	uint8_t LastACPIRequest;
    577 	uint8_t CgBifResp;
    578 	uint8_t RequestType;
    579 	uint8_t Padding;
    580 	SMU72_Discrete_ACPILevel D0Level;
    581 };
    582 
    583 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
    584 
    585 struct SMU72_Discrete_PmFuses {
    586 	/* dw1  */
    587 	uint8_t SviLoadLineEn;
    588 	uint8_t SviLoadLineVddC;
    589 	uint8_t SviLoadLineTrimVddC;
    590 	uint8_t SviLoadLineOffsetVddC;
    591 
    592 	/* dw2 */
    593 	uint16_t TDC_VDDC_PkgLimit;
    594 	uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
    595 	uint8_t TDC_MAWt;
    596 
    597 	/* dw3 */
    598 	uint8_t TdcWaterfallCtl;
    599 	uint8_t LPMLTemperatureMin;
    600 	uint8_t LPMLTemperatureMax;
    601 	uint8_t Reserved;
    602 
    603 	/* dw4-dw7  */
    604 	uint8_t LPMLTemperatureScaler[16];
    605 
    606 	/* dw8-dw9  */
    607 	int16_t FuzzyFan_ErrorSetDelta;
    608 	int16_t FuzzyFan_ErrorRateSetDelta;
    609 	int16_t FuzzyFan_PwmSetDelta;
    610 	uint16_t Reserved6;
    611 
    612 	/* dw10-dw14  */
    613 	uint8_t GnbLPML[16];
    614 
    615 	/* dw15 */
    616 	uint8_t GnbLPMLMaxVid;
    617 	uint8_t GnbLPMLMinVid;
    618 	uint8_t Reserved1[2];
    619 
    620 	/* dw16 */
    621 	uint16_t BapmVddCBaseLeakageHiSidd;
    622 	uint16_t BapmVddCBaseLeakageLoSidd;
    623 };
    624 
    625 typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
    626 
    627 struct SMU7_Discrete_Log_Header_Table {
    628 	uint32_t    version;
    629 	uint32_t    asic_id;
    630 	uint16_t    flags;
    631 	uint16_t    entry_size;
    632 	uint32_t    total_size;
    633 	uint32_t    num_of_entries;
    634 	uint8_t     type;
    635 	uint8_t     mode;
    636 	uint8_t     filler_0[2];
    637 	uint32_t    filler_1[2];
    638 };
    639 
    640 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
    641 
    642 struct SMU7_Discrete_Log_Cntl {
    643 	uint8_t             Enabled;
    644 	uint8_t             Type;
    645 	uint8_t             padding[2];
    646 	uint32_t            BufferSize;
    647 	uint32_t            SamplesLogged;
    648 	uint32_t            SampleSize;
    649 	uint32_t            AddrL;
    650 	uint32_t            AddrH;
    651 };
    652 
    653 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
    654 
    655 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
    656 
    657 struct SMU7_Discrete_Cac_Collection_Table {
    658 	uint32_t temperature;
    659 	uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
    660 };
    661 
    662 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
    663 
    664 struct SMU7_Discrete_Cac_Verification_Table {
    665 	uint32_t VddcTotalPower;
    666 	uint32_t VddcLeakagePower;
    667 	uint32_t VddcConstantPower;
    668 	uint32_t VddcGfxDynamicPower;
    669 	uint32_t VddcUvdDynamicPower;
    670 	uint32_t VddcVceDynamicPower;
    671 	uint32_t VddcAcpDynamicPower;
    672 	uint32_t VddcPcieDynamicPower;
    673 	uint32_t VddcDceDynamicPower;
    674 	uint32_t VddcCurrent;
    675 	uint32_t VddcVoltage;
    676 	uint32_t VddciTotalPower;
    677 	uint32_t VddciLeakagePower;
    678 	uint32_t VddciConstantPower;
    679 	uint32_t VddciDynamicPower;
    680 	uint32_t Vddr1TotalPower;
    681 	uint32_t Vddr1LeakagePower;
    682 	uint32_t Vddr1ConstantPower;
    683 	uint32_t Vddr1DynamicPower;
    684 	uint32_t spare[4];
    685 	uint32_t temperature;
    686 };
    687 
    688 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
    689 
    690 struct SMU7_Discrete_Pm_Status_Table {
    691 	/* Thermal entities */
    692 	int32_t T_meas_max;
    693 	int32_t T_meas_acc;
    694 	int32_t T_calc_max;
    695 	int32_t T_calc_acc;
    696 	uint32_t P_scalar_acc;
    697 	uint32_t P_calc_max;
    698 	uint32_t P_calc_acc;
    699 
    700 	/*Voltage domains */
    701 	uint32_t I_calc_max;
    702 	uint32_t I_calc_acc;
    703 	uint32_t I_calc_acc_vddci;
    704 	uint32_t V_calc_noload_acc;
    705 	uint32_t V_calc_load_acc;
    706 	uint32_t V_calc_noload_acc_vddci;
    707 	uint32_t P_meas_acc;
    708 	uint32_t V_meas_noload_acc;
    709 	uint32_t V_meas_load_acc;
    710 	uint32_t I_meas_acc;
    711 	uint32_t P_meas_acc_vddci;
    712 	uint32_t V_meas_noload_acc_vddci;
    713 	uint32_t V_meas_load_acc_vddci;
    714 	uint32_t I_meas_acc_vddci;
    715 
    716 	/*Frequency */
    717 	uint16_t Sclk_dpm_residency[8];
    718 	uint16_t Uvd_dpm_residency[8];
    719 	uint16_t Vce_dpm_residency[8];
    720 	uint16_t Mclk_dpm_residency[4];
    721 
    722 	/*Chip */
    723 	uint32_t P_vddci_acc;
    724 	uint32_t P_vddr1_acc;
    725 	uint32_t P_nte1_acc;
    726 	uint32_t PkgPwr_max;
    727 	uint32_t PkgPwr_acc;
    728 	uint32_t MclkSwitchingTime_max;
    729 	uint32_t MclkSwitchingTime_acc;
    730 	uint32_t FanPwm_acc;
    731 	uint32_t FanRpm_acc;
    732 
    733 	uint32_t AccCnt;
    734 };
    735 
    736 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
    737 
    738 /*FIXME THESE NEED TO BE UPDATED */
    739 #define SMU7_SCLK_CAC 0x561
    740 #define SMU7_MCLK_CAC 0xF9
    741 #define SMU7_VCLK_CAC 0x2DE
    742 #define SMU7_DCLK_CAC 0x2DE
    743 #define SMU7_ECLK_CAC 0x25E
    744 #define SMU7_ACLK_CAC 0x25E
    745 #define SMU7_SAMCLK_CAC 0x25E
    746 #define SMU7_DISPCLK_CAC 0x100
    747 #define SMU7_CAC_CONSTANT 0x2EE3430
    748 #define SMU7_CAC_CONSTANT_SHIFT 18
    749 
    750 #define SMU7_VDDCI_MCLK_CONST        1765
    751 #define SMU7_VDDCI_MCLK_CONST_SHIFT  16
    752 #define SMU7_VDDCI_VDDCI_CONST       50958
    753 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
    754 #define SMU7_VDDCI_CONST             11781
    755 
    756 #define SMU7_12C_VDDCI_MCLK_CONST        1623
    757 #define SMU7_12C_VDDCI_MCLK_CONST_SHIFT  15
    758 #define SMU7_12C_VDDCI_VDDCI_CONST       40088
    759 #define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
    760 #define SMU7_12C_VDDCI_CONST             20856
    761 
    762 #define SMU7_VDDCI_STROBE_PWR        1331
    763 
    764 #define SMU7_VDDR1_CONST            693
    765 #define SMU7_VDDR1_CAC_WEIGHT       20
    766 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
    767 #define SMU7_VDDR1_STROBE_PWR       512
    768 
    769 #define SMU7_AREA_COEFF_UVD 0xA78
    770 #define SMU7_AREA_COEFF_VCE 0x190A
    771 #define SMU7_AREA_COEFF_ACP 0x22D1
    772 #define SMU7_AREA_COEFF_SAMU 0x534
    773 
    774 /*ThermOutMode values */
    775 #define SMU7_THERM_OUT_MODE_DISABLE       0x0
    776 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
    777 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
    778 
    779 #if !defined(SMC_MICROCODE)
    780 #pragma pack(pop)
    781 #endif
    782 
    783 
    784 #endif
    785 
    786