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    Searched defs:VecReg (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 2691 Register VecReg = MI.getOperand(1).getReg();
2700 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI);
2716 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) ||
2742 .addReg(VecReg)
2752 .addReg(VecReg)
AMDGPURegisterBankInfo.cpp 1902 Register VecReg = MI.getOperand(1).getReg();
1910 LLT VecTy = MRI.getType(VecReg);
1946 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg);
1984 Register VecReg = MI.getOperand(1).getReg();
1992 LLT VecTy = MRI.getType(VecReg);
2033 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg);
SIInstrInfo.cpp 1814 Register VecReg = MI.getOperand(0).getReg();
1817 assert(VecReg == MI.getOperand(1).getReg());
1821 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1823 .addReg(VecReg, RegState::ImplicitDefine)
1824 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1842 Register VecReg = MI.getOperand(0).getReg();
1855 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1857 .addReg(VecReg, RegState::ImplicitDefine)
1858 .addReg(VecReg,
1882 Register VecReg = MI.getOperand(1).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 2261 Register VecReg = MI.getOperand(1).getReg();
2262 LLT VecTy = MRI.getType(VecReg);
2286 Register VecReg = MI.getOperand(1).getReg();
2287 LLT VecTy = MRI.getType(VecReg);

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