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    Searched defs:Vs (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXUtilities.cpp 285 std::vector<unsigned> Vs;
286 bool retval = findAllNVVMAnnotation(&F, "align", Vs);
289 for (int i = 0, e = Vs.size(); i < e; i++) {
290 unsigned v = Vs[i];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAddressingModes.h 277 unsigned u, Vs, Imm;
283 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
285 Imm = Vs & 0xff;
290 if (Vs == u)
291 return (((Vs == V) ? 1 : 2) << 8) | Imm;
294 if (Vs == (u | (u << 8)))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 2419 SDValue Vs[4];
2421 Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2422 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2425 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2426 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2427 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2428 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});

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