1 /* $NetBSD: dcn20_dwb.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* Copyright 2012-17 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #ifndef __DC_DWBC_DCN20_H__ 27 #define __DC_DWBC_DCN20_H__ 28 29 #define TO_DCN20_DWBC(dwbc_base) \ 30 container_of(dwbc_base, struct dcn20_dwbc, base) 31 32 /* DCN */ 33 #define BASE_INNER(seg) \ 34 DCE_BASE__INST0_SEG ## seg 35 36 #define BASE(seg) \ 37 BASE_INNER(seg) 38 39 #define SR(reg_name)\ 40 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 41 mm ## reg_name 42 43 #define SRI(reg_name, block, id)\ 44 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 45 mm ## block ## id ## _ ## reg_name 46 47 #define SRI2(reg_name, block, id)\ 48 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 49 mm ## reg_name 50 51 #define SRII(reg_name, block, id)\ 52 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 53 mm ## block ## id ## _ ## reg_name 54 55 #define SF(reg_name, field_name, post_fix)\ 56 .field_name = reg_name ## __ ## field_name ## post_fix 57 58 59 #define DWBC_COMMON_REG_LIST_DCN2_0(inst) \ 60 SRI2(WB_ENABLE, CNV, inst),\ 61 SRI2(WB_EC_CONFIG, CNV, inst),\ 62 SRI2(CNV_MODE, CNV, inst),\ 63 SRI2(CNV_WINDOW_START, CNV, inst),\ 64 SRI2(CNV_WINDOW_SIZE, CNV, inst),\ 65 SRI2(CNV_UPDATE, CNV, inst),\ 66 SRI2(CNV_SOURCE_SIZE, CNV, inst),\ 67 SRI2(CNV_TEST_CNTL, CNV, inst),\ 68 SRI2(CNV_TEST_CRC_RED, CNV, inst),\ 69 SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\ 70 SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\ 71 SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\ 72 SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\ 73 SRI2(WBSCL_MODE, WBSCL, inst),\ 74 SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\ 75 SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\ 76 SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\ 77 SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\ 78 SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\ 79 SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\ 80 SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\ 81 SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\ 82 SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\ 83 SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\ 84 SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\ 85 SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\ 86 SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\ 87 SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\ 88 SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\ 89 SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\ 90 SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\ 91 SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\ 92 SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\ 93 SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\ 94 SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\ 95 SRI2(WBSCL_DEBUG, WBSCL, inst),\ 96 SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\ 97 SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\ 98 SRI2(WB_DEBUG_CTRL, CNV, inst),\ 99 SRI2(WB_DBG_MODE, CNV, inst),\ 100 SRI2(WB_HW_DEBUG, CNV, inst),\ 101 SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\ 102 SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\ 103 SRI2(WB_SOFT_RESET, CNV, inst),\ 104 SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\ 105 SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst) 106 107 #define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ 108 SF(WB_ENABLE, WB_ENABLE, mask_sh),\ 109 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ 110 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ 111 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ 112 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\ 113 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ 114 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\ 115 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ 116 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\ 117 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\ 118 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\ 119 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\ 120 SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\ 121 SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\ 122 SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\ 123 SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\ 124 SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ 125 SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ 126 SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ 127 SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ 128 SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ 129 SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ 130 SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ 131 SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ 132 SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ 133 SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ 134 SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\ 135 SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\ 136 SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\ 137 SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\ 138 SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\ 139 SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\ 140 SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\ 141 SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\ 142 SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\ 143 SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\ 144 SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\ 145 SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\ 146 SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\ 147 SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\ 148 SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\ 149 SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\ 150 SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\ 151 SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\ 152 SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\ 153 SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\ 154 SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\ 155 SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\ 156 SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\ 157 SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\ 158 SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\ 159 SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\ 160 SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ 161 SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\ 162 SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\ 163 SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\ 164 SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ 165 SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\ 166 SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\ 167 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ 168 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ 169 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ 170 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ 171 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\ 172 SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\ 173 SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\ 174 SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\ 175 SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\ 176 SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\ 177 SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\ 178 SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\ 179 SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\ 180 SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\ 181 SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\ 182 SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\ 183 SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\ 184 SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\ 185 SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\ 186 SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\ 187 SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\ 188 SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\ 189 SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ 190 SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ 191 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\ 192 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\ 193 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\ 194 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\ 195 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\ 196 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\ 197 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\ 198 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\ 199 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\ 200 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\ 201 SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\ 202 SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\ 203 SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\ 204 SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\ 205 SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\ 206 SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\ 207 SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\ 208 SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\ 209 SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\ 210 SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\ 211 SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\ 212 SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\ 213 SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\ 214 SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ 215 SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ 216 SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\ 217 SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\ 218 SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\ 219 SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\ 220 SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\ 221 SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\ 222 SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\ 223 SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\ 224 SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\ 225 SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\ 226 SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\ 227 SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\ 228 SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\ 229 SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh) 230 231 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \ 232 type WB_ENABLE;\ 233 type DISPCLK_R_WB_GATE_DIS;\ 234 type DISPCLK_G_WB_GATE_DIS;\ 235 type DISPCLK_G_WBSCL_GATE_DIS;\ 236 type WB_TEST_CLK_SEL;\ 237 type WB_LB_LS_DIS;\ 238 type WB_LB_SD_DIS;\ 239 type WB_LUT_LS_DIS;\ 240 type WBSCL_LB_MEM_PWR_MODE_SEL;\ 241 type WBSCL_LB_MEM_PWR_DIS;\ 242 type WBSCL_LB_MEM_PWR_FORCE;\ 243 type WBSCL_LB_MEM_PWR_STATE;\ 244 type WB_RAM_PW_SAVE_MODE;\ 245 type WBSCL_LUT_MEM_PWR_STATE;\ 246 type CNV_OUT_BPC;\ 247 type CNV_FRAME_CAPTURE_RATE;\ 248 type CNV_WINDOW_CROP_EN;\ 249 type CNV_STEREO_TYPE;\ 250 type CNV_INTERLACED_MODE;\ 251 type CNV_EYE_SELECTION;\ 252 type CNV_STEREO_POLARITY;\ 253 type CNV_INTERLACED_FIELD_ORDER;\ 254 type CNV_STEREO_SPLIT;\ 255 type CNV_NEW_CONTENT;\ 256 type CNV_FRAME_CAPTURE_EN_CURRENT;\ 257 type CNV_FRAME_CAPTURE_EN;\ 258 type CNV_WINDOW_START_X;\ 259 type CNV_WINDOW_START_Y;\ 260 type CNV_WINDOW_WIDTH;\ 261 type CNV_WINDOW_HEIGHT;\ 262 type CNV_UPDATE_PENDING;\ 263 type CNV_UPDATE_TAKEN;\ 264 type CNV_UPDATE_LOCK;\ 265 type CNV_SOURCE_WIDTH;\ 266 type CNV_SOURCE_HEIGHT;\ 267 type CNV_TEST_CRC_EN;\ 268 type CNV_TEST_CRC_CONT_EN;\ 269 type CNV_TEST_CRC_RED_MASK;\ 270 type CNV_TEST_CRC_SIG_RED;\ 271 type CNV_TEST_CRC_GREEN_MASK;\ 272 type CNV_TEST_CRC_SIG_GREEN;\ 273 type CNV_TEST_CRC_BLUE_MASK;\ 274 type CNV_TEST_CRC_SIG_BLUE;\ 275 type WB_DEBUG_EN;\ 276 type WB_DEBUG_SEL;\ 277 type WB_DBG_MODE_EN;\ 278 type WB_DBG_DIN_FMT;\ 279 type WB_DBG_36MODE;\ 280 type WB_DBG_CMAP;\ 281 type WB_DBG_PXLRATE_ERROR;\ 282 type WB_DBG_SOURCE_WIDTH;\ 283 type WB_HW_DEBUG;\ 284 type CNV_TEST_DEBUG_INDEX;\ 285 type CNV_TEST_DEBUG_WRITE_EN;\ 286 type CNV_TEST_DEBUG_DATA;\ 287 type WB_SOFT_RESET;\ 288 type WBSCL_COEF_RAM_TAP_PAIR_IDX;\ 289 type WBSCL_COEF_RAM_PHASE;\ 290 type WBSCL_COEF_RAM_FILTER_TYPE;\ 291 type WBSCL_COEF_RAM_SEL;\ 292 type WBSCL_COEF_RAM_SEL_CURRENT;\ 293 type WBSCL_COEF_RAM_RD_SEL;\ 294 type WBSCL_COEF_RAM_EVEN_TAP_COEF;\ 295 type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\ 296 type WBSCL_COEF_RAM_ODD_TAP_COEF;\ 297 type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\ 298 type WBSCL_MODE;\ 299 type WBSCL_OUT_BIT_DEPTH;\ 300 type WBSCL_V_NUM_OF_TAPS_Y_RGB;\ 301 type WBSCL_V_NUM_OF_TAPS_CBCR;\ 302 type WBSCL_H_NUM_OF_TAPS_Y_RGB;\ 303 type WBSCL_H_NUM_OF_TAPS_CBCR;\ 304 type WBSCL_DEST_HEIGHT;\ 305 type WBSCL_DEST_WIDTH;\ 306 type WBSCL_H_SCALE_RATIO;\ 307 type WBSCL_H_INIT_FRAC_Y_RGB;\ 308 type WBSCL_H_INIT_INT_Y_RGB;\ 309 type WBSCL_H_INIT_FRAC_CBCR;\ 310 type WBSCL_H_INIT_INT_CBCR;\ 311 type WBSCL_V_SCALE_RATIO;\ 312 type WBSCL_V_INIT_FRAC_Y_RGB;\ 313 type WBSCL_V_INIT_INT_Y_RGB;\ 314 type WBSCL_V_INIT_FRAC_CBCR;\ 315 type WBSCL_V_INIT_INT_CBCR;\ 316 type WBSCL_ROUND_OFFSET_Y_RGB;\ 317 type WBSCL_ROUND_OFFSET_CBCR;\ 318 type WBSCL_DATA_OVERFLOW_FLAG;\ 319 type WBSCL_DATA_OVERFLOW_ACK;\ 320 type WBSCL_DATA_OVERFLOW_MASK;\ 321 type WBSCL_DATA_OVERFLOW_INT_STATUS;\ 322 type WBSCL_DATA_OVERFLOW_INT_TYPE;\ 323 type WBSCL_HOST_CONFLICT_FLAG;\ 324 type WBSCL_HOST_CONFLICT_ACK;\ 325 type WBSCL_HOST_CONFLICT_MASK;\ 326 type WBSCL_HOST_CONFLICT_INT_STATUS;\ 327 type WBSCL_HOST_CONFLICT_INT_TYPE;\ 328 type WBSCL_TEST_CRC_EN;\ 329 type WBSCL_TEST_CRC_CONT_EN;\ 330 type WBSCL_TEST_CRC_RED_MASK;\ 331 type WBSCL_TEST_CRC_SIG_RED;\ 332 type WBSCL_TEST_CRC_GREEN_MASK;\ 333 type WBSCL_TEST_CRC_SIG_GREEN;\ 334 type WBSCL_TEST_CRC_BLUE_MASK;\ 335 type WBSCL_TEST_CRC_SIG_BLUE;\ 336 type WBSCL_BACKPRESSURE_CNT_EN;\ 337 type WB_MCIF_Y_MAX_BACKPRESSURE;\ 338 type WB_MCIF_C_MAX_BACKPRESSURE;\ 339 type WBSCL_CLAMP_UPPER_Y_RGB;\ 340 type WBSCL_CLAMP_LOWER_Y_RGB;\ 341 type WBSCL_CLAMP_UPPER_CBCR;\ 342 type WBSCL_CLAMP_LOWER_CBCR;\ 343 type WBSCL_OUTSIDE_PIX_STRATEGY;\ 344 type WBSCL_BLACK_COLOR_G_Y;\ 345 type WBSCL_BLACK_COLOR_B_CB;\ 346 type WBSCL_BLACK_COLOR_R_CR;\ 347 type WBSCL_DEBUG;\ 348 type WBSCL_TEST_DEBUG_INDEX;\ 349 type WBSCL_TEST_DEBUG_WRITE_EN;\ 350 type WBSCL_TEST_DEBUG_DATA;\ 351 type WIDTH_WARMUP;\ 352 type HEIGHT_WARMUP;\ 353 type GMC_WARM_UP_ENABLE;\ 354 type DATA_VALUE_WARMUP;\ 355 type MODE_WARMUP;\ 356 type DATA_DEPTH_WARMUP; \ 357 358 struct dcn20_dwbc_registers { 359 /* DCN2.0 */ 360 uint32_t WB_ENABLE; 361 uint32_t WB_EC_CONFIG; 362 uint32_t CNV_MODE; 363 uint32_t CNV_WINDOW_START; 364 uint32_t CNV_WINDOW_SIZE; 365 uint32_t CNV_UPDATE; 366 uint32_t CNV_SOURCE_SIZE; 367 uint32_t CNV_TEST_CNTL; 368 uint32_t CNV_TEST_CRC_RED; 369 uint32_t CNV_TEST_CRC_GREEN; 370 uint32_t CNV_TEST_CRC_BLUE; 371 uint32_t WB_DEBUG_CTRL; 372 uint32_t WB_DBG_MODE; 373 uint32_t WB_HW_DEBUG; 374 uint32_t CNV_TEST_DEBUG_INDEX; 375 uint32_t CNV_TEST_DEBUG_DATA; 376 uint32_t WB_SOFT_RESET; 377 uint32_t WBSCL_COEF_RAM_SELECT; 378 uint32_t WBSCL_COEF_RAM_TAP_DATA; 379 uint32_t WBSCL_MODE; 380 uint32_t WBSCL_TAP_CONTROL; 381 uint32_t WBSCL_DEST_SIZE; 382 uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO; 383 uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB; 384 uint32_t WBSCL_HORZ_FILTER_INIT_CBCR; 385 uint32_t WBSCL_VERT_FILTER_SCALE_RATIO; 386 uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB; 387 uint32_t WBSCL_VERT_FILTER_INIT_CBCR; 388 uint32_t WBSCL_ROUND_OFFSET; 389 uint32_t WBSCL_OVERFLOW_STATUS; 390 uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS; 391 uint32_t WBSCL_TEST_CNTL; 392 uint32_t WBSCL_TEST_CRC_RED; 393 uint32_t WBSCL_TEST_CRC_GREEN; 394 uint32_t WBSCL_TEST_CRC_BLUE; 395 uint32_t WBSCL_BACKPRESSURE_CNT_EN; 396 uint32_t WB_MCIF_BACKPRESSURE_CNT; 397 uint32_t WBSCL_CLAMP_Y_RGB; 398 uint32_t WBSCL_CLAMP_CBCR; 399 uint32_t WBSCL_OUTSIDE_PIX_STRATEGY; 400 uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR; 401 uint32_t WBSCL_DEBUG; 402 uint32_t WBSCL_TEST_DEBUG_INDEX; 403 uint32_t WBSCL_TEST_DEBUG_DATA; 404 uint32_t WB_WARM_UP_MODE_CTL1; 405 uint32_t WB_WARM_UP_MODE_CTL2; 406 }; 407 408 409 struct dcn20_dwbc_mask { 410 DWBC_REG_FIELD_LIST_DCN2_0(uint32_t) 411 }; 412 413 struct dcn20_dwbc_shift { 414 DWBC_REG_FIELD_LIST_DCN2_0(uint8_t) 415 }; 416 417 struct dcn20_dwbc { 418 struct dwbc base; 419 const struct dcn20_dwbc_registers *dwbc_regs; 420 const struct dcn20_dwbc_shift *dwbc_shift; 421 const struct dcn20_dwbc_mask *dwbc_mask; 422 }; 423 424 void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20, 425 struct dc_context *ctx, 426 const struct dcn20_dwbc_registers *dwbc_regs, 427 const struct dcn20_dwbc_shift *dwbc_shift, 428 const struct dcn20_dwbc_mask *dwbc_mask, 429 int inst); 430 431 bool dwb2_disable(struct dwbc *dwbc); 432 433 bool dwb2_is_enabled(struct dwbc *dwbc); 434 435 void dwb2_set_stereo(struct dwbc *dwbc, 436 struct dwb_stereo_params *stereo_params); 437 438 void dwb2_set_new_content(struct dwbc *dwbc, 439 bool is_new_content); 440 441 void dwb2_config_dwb_cnv(struct dwbc *dwbc, 442 struct dc_dwb_params *params); 443 444 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params); 445 446 bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20, 447 uint32_t src_height, 448 uint32_t dest_height, 449 struct scaling_taps num_taps, 450 enum dwb_subsample_position subsample_position); 451 452 bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20, 453 uint32_t src_width, 454 uint32_t dest_width, 455 struct scaling_taps num_taps); 456 457 458 #endif 459 460 461
Indexes created Thu Sep 25 02:09:54 GMT 2025