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    Searched defs:WR1 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/arm/ti/
ti_omapmusb.c 77 #define WR1(sc, reg, val) \
107 WR1(sc, MUSB2_REG_INTUSB, intusb);
  /src/sys/arch/evbppc/nintendo/dev/
avenc.c 59 #define WR1 avenc_write_1
206 WR1(tag, addr, 0x6a, 1);
207 WR1(tag, addr, 0x65, 3);
208 WR1(tag, addr, 0x01, video_fmt);
209 WR1(tag, addr, 0x00, 0);
210 WR1(tag, addr, 0x02, 7);
215 WR1(tag, addr, 0x0a, 0);
216 WR1(tag, addr, 0x03, 1);
218 WR1(tag, addr, 0x04, 1);
221 WR1(tag, addr, 0x03, 1)
    [all...]
  /src/sys/arch/powerpc/mpc5200/
mpc5200_ac97.c 185 WR1(struct mpcac97_softc *sc, bus_size_t o, uint8_t v)
318 WR1(sc, PSC_CR, CMD_RESET_RX);
319 WR1(sc, PSC_CR, CMD_RESET_TX);
320 WR1(sc, PSC_CR, CMD_RESET_ERR);
321 WR1(sc, PSC_CR, CMD_RESET_MR);
327 WR1(sc, PSC_TFCNTL, MPCAC97_TFGRAN);
429 WR1(sc, PSC_CR, CMD_TX_DISABLE | CMD_RX_DISABLE);
430 WR1(sc, PSC_OP1, AC97_OP_RES); /* RES -> low */
432 WR1(sc, PSC_OP0, AC97_OP_RES); /* RES -> high */
434 WR1(sc, PSC_CR, CMD_TX_ENABLE | CMD_RX_ENABLE)
    [all...]
  /src/sys/arch/luna68k/dev/
sioreg.h 74 #define WR1 0x01
  /src/sys/arch/luna68k/stand/boot/
sioreg.h 93 #define WR1 0x01

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