1 /* $NetBSD: x1226reg.h,v 1.4 2013/08/07 19:38:45 soren Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima for the NetBSD project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Shigeyuki Fukushima. 21 * 4. The name of Shigeyuki Fukushima may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Xicor X1226 RTC registers 40 */ 41 42 #ifndef _DEV_I2C_X1226REG_H_ 43 #define _DEV_I2C_X1226REG_H_ 44 45 /* 46 * Xicor X1226 RTC I2C Address: 47 * 48 * 110 1111 49 */ 50 #define X1226_ADDRMASK 0x3ff 51 #define X1226_ADDR 0x6f 52 53 /* XICOR X1226 Device Identifier */ 54 #define X1226_DEVID_CCR 0x6f 55 #define X1226_DEVID_EEPROM 0x57 56 57 /* Watchdog RTC registers */ 58 #define X1226_REG_Y2K 0x37 /* bcd century (19/20) */ 59 #define X1226_REG_DW 0x36 /* bcd ay of week (0-6) */ 60 #define X1226_REG_YR 0x35 /* bcd year (0-99) */ 61 #define X1226_REG_MO 0x34 /* bcd onth (1-12) */ 62 #define X1226_REG_DT 0x33 /* bcd ay (1-31) */ 63 #define X1226_REG_HR 0x32 /* bcd our (0-23) */ 64 #define X1226_REG_MN 0x31 /* bcd inute (0-59) */ 65 #define X1226_REG_SC 0x30 /* bcd econd (0-59) */ 66 #define X1226_REG_RTC_BASE 0x30 67 #define X1226_REG_RTC_SIZE ((X1226_REG_Y2K - X1226_REG_RTC_BASE) + 1) 68 /* Watchdog RTC registers mask */ 69 #define X1226_REG_Y2K_MASK 0x39 70 #define X1226_REG_DW_MASK 0x07 71 #define X1226_REG_YR_MASK 0xff 72 #define X1226_REG_MO_MASK 0x1f 73 #define X1226_REG_DT_MASK 0x3f 74 #define X1226_REG_HR12_MASK 0x1f 75 #define X1226_REG_HR24_MASK 0x3f 76 #define X1226_REG_MN_MASK 0x7f 77 #define X1226_REG_SC_MASK 0x7f 78 79 #define X1226_REG_SR 0x3f 80 #define X1226_CTRL_DTR 0x13 81 #define X1226_CTRL_ATR 0x12 82 #define X1226_CTRL_INT 0x11 83 #define X1226_CTRL_BL 0x10 84 85 /* NVRAM size (512 x 8 bit) */ 86 #define X1226_NVRAM_START 0x0040 87 #define X1226_NVRAM_END 0x00FF 88 #define X1226_NVRAM_SIZE ((X1226_NVRAM_END - X1226_NVRAM_START) + 1) 89 90 /* XICOR X1226 RTC flags */ 91 #define X1226_FLAG_SR_RTCF 0x01 92 #define X1226_FLAG_SR_WEL 0x02 93 #define X1226_FLAG_SR_RWEL 0x04 94 #define X1226_FLAG_SR_AL0 0x20 95 #define X1226_FLAG_SR_AL1 0x40 96 #define X1226_FLAG_SR_BAT 0x80 97 #define X1226_FLAG_HR_12HPM 0x20 98 #define X1226_FLAG_HR_24H 0x80 99 100 101 #endif /* _DEV_I2C_X1226REG_H_ */ 102
Indexes created Thu Sep 25 16:09:42 GMT 2025