1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file a TargetTransformInfo::Concept conforming object specific to the 10 /// X86 target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H 18 19 #include "X86TargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/BasicTTIImpl.h" 22 23 namespace llvm { 24 25 class InstCombiner; 26 27 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> { 28 typedef BasicTTIImplBase<X86TTIImpl> BaseT; 29 typedef TargetTransformInfo TTI; 30 friend BaseT; 31 32 const X86Subtarget *ST; 33 const X86TargetLowering *TLI; 34 35 const X86Subtarget *getST() const { return ST; } 36 const X86TargetLowering *getTLI() const { return TLI; } 37 38 const FeatureBitset InlineFeatureIgnoreList = { 39 // This indicates the CPU is 64 bit capable not that we are in 64-bit 40 // mode. 41 X86::Feature64Bit, 42 43 // These features don't have any intrinsics or ABI effect. 44 X86::FeatureNOPL, 45 X86::FeatureCMPXCHG16B, 46 X86::FeatureLAHFSAHF, 47 48 // Codegen control options. 49 X86::FeatureFast11ByteNOP, 50 X86::FeatureFast15ByteNOP, 51 X86::FeatureFastBEXTR, 52 X86::FeatureFastHorizontalOps, 53 X86::FeatureFastLZCNT, 54 X86::FeatureFastScalarFSQRT, 55 X86::FeatureFastSHLDRotate, 56 X86::FeatureFastScalarShiftMasks, 57 X86::FeatureFastVectorShiftMasks, 58 X86::FeatureFastVariableShuffle, 59 X86::FeatureFastVectorFSQRT, 60 X86::FeatureLEAForSP, 61 X86::FeatureLEAUsesAG, 62 X86::FeatureLZCNTFalseDeps, 63 X86::FeatureBranchFusion, 64 X86::FeatureMacroFusion, 65 X86::FeaturePadShortFunctions, 66 X86::FeaturePOPCNTFalseDeps, 67 X86::FeatureSSEUnalignedMem, 68 X86::FeatureSlow3OpsLEA, 69 X86::FeatureSlowDivide32, 70 X86::FeatureSlowDivide64, 71 X86::FeatureSlowIncDec, 72 X86::FeatureSlowLEA, 73 X86::FeatureSlowPMADDWD, 74 X86::FeatureSlowPMULLD, 75 X86::FeatureSlowSHLD, 76 X86::FeatureSlowTwoMemOps, 77 X86::FeatureSlowUAMem16, 78 X86::FeaturePreferMaskRegisters, 79 X86::FeatureInsertVZEROUPPER, 80 X86::FeatureUseGLMDivSqrtCosts, 81 82 // Perf-tuning flags. 83 X86::FeatureHasFastGather, 84 X86::FeatureSlowUAMem32, 85 86 // Based on whether user set the -mprefer-vector-width command line. 87 X86::FeaturePrefer128Bit, 88 X86::FeaturePrefer256Bit, 89 90 // CPU name enums. These just follow CPU string. 91 X86::ProcIntelAtom, 92 X86::ProcIntelSLM, 93 }; 94 95 public: 96 explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F) 97 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 98 TLI(ST->getTargetLowering()) {} 99 100 /// \name Scalar TTI Implementations 101 /// @{ 102 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); 103 104 /// @} 105 106 /// \name Cache TTI Implementation 107 /// @{ 108 llvm::Optional<unsigned> getCacheSize( 109 TargetTransformInfo::CacheLevel Level) const override; 110 llvm::Optional<unsigned> getCacheAssociativity( 111 TargetTransformInfo::CacheLevel Level) const override; 112 /// @} 113 114 /// \name Vector TTI Implementations 115 /// @{ 116 117 unsigned getNumberOfRegisters(unsigned ClassID) const; 118 TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; 119 unsigned getLoadStoreVecRegBitWidth(unsigned AS) const; 120 unsigned getMaxInterleaveFactor(unsigned VF); 121 InstructionCost getArithmeticInstrCost( 122 unsigned Opcode, Type *Ty, 123 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, 124 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, 125 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, 126 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 127 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, 128 ArrayRef<const Value *> Args = ArrayRef<const Value *>(), 129 const Instruction *CxtI = nullptr); 130 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, 131 ArrayRef<int> Mask, int Index, 132 VectorType *SubTp); 133 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 134 TTI::CastContextHint CCH, 135 TTI::TargetCostKind CostKind, 136 const Instruction *I = nullptr); 137 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 138 CmpInst::Predicate VecPred, 139 TTI::TargetCostKind CostKind, 140 const Instruction *I = nullptr); 141 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, 142 unsigned Index); 143 InstructionCost getScalarizationOverhead(VectorType *Ty, 144 const APInt &DemandedElts, 145 bool Insert, bool Extract); 146 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, 147 MaybeAlign Alignment, unsigned AddressSpace, 148 TTI::TargetCostKind CostKind, 149 const Instruction *I = nullptr); 150 InstructionCost 151 getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, 152 unsigned AddressSpace, 153 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency); 154 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, 155 const Value *Ptr, bool VariableMask, 156 Align Alignment, 157 TTI::TargetCostKind CostKind, 158 const Instruction *I); 159 InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, 160 const SCEV *Ptr); 161 162 Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, 163 IntrinsicInst &II) const; 164 Optional<Value *> 165 simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, 166 APInt DemandedMask, KnownBits &Known, 167 bool &KnownBitsComputed) const; 168 Optional<Value *> simplifyDemandedVectorEltsIntrinsic( 169 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, 170 APInt &UndefElts2, APInt &UndefElts3, 171 std::function<void(Instruction *, unsigned, APInt, APInt &)> 172 SimplifyAndSetOp) const; 173 174 unsigned getAtomicMemIntrinsicMaxElementSize() const; 175 176 InstructionCost 177 getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 178 TTI::TargetCostKind CostKind); 179 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 180 TTI::TargetCostKind CostKind); 181 182 InstructionCost getArithmeticReductionCost( 183 unsigned Opcode, VectorType *Ty, bool IsPairwiseForm, 184 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency); 185 186 InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned); 187 188 InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, 189 bool IsPairwiseForm, bool IsUnsigned, 190 TTI::TargetCostKind CostKind); 191 192 InstructionCost getInterleavedMemoryOpCost( 193 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 194 Align Alignment, unsigned AddressSpace, 195 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 196 bool UseMaskForCond = false, bool UseMaskForGaps = false); 197 InstructionCost getInterleavedMemoryOpCostAVX512( 198 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 199 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 200 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 201 bool UseMaskForCond = false, bool UseMaskForGaps = false); 202 InstructionCost getInterleavedMemoryOpCostAVX2( 203 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 204 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 205 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 206 bool UseMaskForCond = false, bool UseMaskForGaps = false); 207 208 InstructionCost getIntImmCost(int64_t); 209 210 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, 211 TTI::TargetCostKind CostKind); 212 213 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, 214 const Instruction *I = nullptr); 215 216 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, 217 const APInt &Imm, Type *Ty, 218 TTI::TargetCostKind CostKind, 219 Instruction *Inst = nullptr); 220 InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 221 const APInt &Imm, Type *Ty, 222 TTI::TargetCostKind CostKind); 223 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, 224 TargetTransformInfo::LSRCost &C2); 225 bool canMacroFuseCmp(); 226 bool isLegalMaskedLoad(Type *DataType, Align Alignment); 227 bool isLegalMaskedStore(Type *DataType, Align Alignment); 228 bool isLegalNTLoad(Type *DataType, Align Alignment); 229 bool isLegalNTStore(Type *DataType, Align Alignment); 230 bool isLegalMaskedGather(Type *DataType, Align Alignment); 231 bool isLegalMaskedScatter(Type *DataType, Align Alignment); 232 bool isLegalMaskedExpandLoad(Type *DataType); 233 bool isLegalMaskedCompressStore(Type *DataType); 234 bool hasDivRemOp(Type *DataType, bool IsSigned); 235 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty); 236 bool areInlineCompatible(const Function *Caller, 237 const Function *Callee) const; 238 bool areFunctionArgsABICompatible(const Function *Caller, 239 const Function *Callee, 240 SmallPtrSetImpl<Argument *> &Args) const; 241 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, 242 bool IsZeroCmp) const; 243 bool enableInterleavedAccessVectorization(); 244 245 private: 246 InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy, 247 bool VariableMask, Align Alignment, 248 unsigned AddressSpace); 249 InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy, 250 const Value *Ptr, Align Alignment, 251 unsigned AddressSpace); 252 253 int getGatherOverhead() const; 254 int getScatterOverhead() const; 255 256 /// @} 257 }; 258 259 } // end namespace llvm 260 261 #endif 262
Indexes created Wed Sep 23 00:26:21 UTC 2026