1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that XCore uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H 15 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H 16 17 #include "XCore.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 23 // Forward delcarations 24 class XCoreSubtarget; 25 26 namespace XCoreISD { 27 enum NodeType : unsigned { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 // Branch and link (call) 32 BL, 33 34 // pc relative address 35 PCRelativeWrapper, 36 37 // dp relative address 38 DPRelativeWrapper, 39 40 // cp relative address 41 CPRelativeWrapper, 42 43 // Load word from stack 44 LDWSP, 45 46 // Store word to stack 47 STWSP, 48 49 // Corresponds to retsp instruction 50 RETSP, 51 52 // Corresponds to LADD instruction 53 LADD, 54 55 // Corresponds to LSUB instruction 56 LSUB, 57 58 // Corresponds to LMUL instruction 59 LMUL, 60 61 // Corresponds to MACCU instruction 62 MACCU, 63 64 // Corresponds to MACCS instruction 65 MACCS, 66 67 // Corresponds to CRC8 instruction 68 CRC8, 69 70 // Jumptable branch. 71 BR_JT, 72 73 // Jumptable branch using long branches for each entry. 74 BR_JT32, 75 76 // Offset from frame pointer to the first (possible) on-stack argument 77 FRAME_TO_ARGS_OFFSET, 78 79 // Exception handler return. The stack is restored to the first 80 // followed by a jump to the second argument. 81 EH_RETURN, 82 83 // Memory barrier. 84 MEMBARRIER 85 }; 86 } 87 88 //===--------------------------------------------------------------------===// 89 // TargetLowering Implementation 90 //===--------------------------------------------------------------------===// 91 class XCoreTargetLowering : public TargetLowering 92 { 93 public: 94 explicit XCoreTargetLowering(const TargetMachine &TM, 95 const XCoreSubtarget &Subtarget); 96 97 using TargetLowering::isZExtFree; 98 bool isZExtFree(SDValue Val, EVT VT2) const override; 99 100 101 unsigned getJumpTableEncoding() const override; 102 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override { 103 return MVT::i32; 104 } 105 106 /// LowerOperation - Provide custom lowering hooks for some operations. 107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 108 109 /// ReplaceNodeResults - Replace the results of node with an illegal result 110 /// type with new values built out of custom code. 111 /// 112 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 113 SelectionDAG &DAG) const override; 114 115 /// getTargetNodeName - This method returns the name of a target specific 116 // DAG node. 117 const char *getTargetNodeName(unsigned Opcode) const override; 118 119 MachineBasicBlock * 120 EmitInstrWithCustomInserter(MachineInstr &MI, 121 MachineBasicBlock *MBB) const override; 122 123 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 124 Type *Ty, unsigned AS, 125 Instruction *I = nullptr) const override; 126 127 /// If a physical register, this returns the register that receives the 128 /// exception address on entry to an EH pad. 129 Register 130 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 131 return XCore::R0; 132 } 133 134 /// If a physical register, this returns the register that receives the 135 /// exception typeid on entry to a landing pad. 136 Register 137 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 138 return XCore::R1; 139 } 140 141 private: 142 const TargetMachine &TM; 143 const XCoreSubtarget &Subtarget; 144 145 // Lower Operand helpers 146 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, 147 bool isVarArg, 148 const SmallVectorImpl<ISD::InputArg> &Ins, 149 const SDLoc &dl, SelectionDAG &DAG, 150 SmallVectorImpl<SDValue> &InVals) const; 151 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 152 CallingConv::ID CallConv, bool isVarArg, 153 bool isTailCall, 154 const SmallVectorImpl<ISD::OutputArg> &Outs, 155 const SmallVectorImpl<SDValue> &OutVals, 156 const SmallVectorImpl<ISD::InputArg> &Ins, 157 const SDLoc &dl, SelectionDAG &DAG, 158 SmallVectorImpl<SDValue> &InVals) const; 159 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 160 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, 161 SelectionDAG &DAG) const; 162 SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL, 163 SDValue Chain, SDValue Base, 164 int64_t Offset, 165 SelectionDAG &DAG) const; 166 167 // Lower Operand specifics 168 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 169 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 170 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 171 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 172 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 173 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 174 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 175 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 176 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 177 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 178 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 179 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 180 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 181 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 182 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 183 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 184 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 185 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 186 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 187 SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 188 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 189 190 MachineMemOperand::Flags getTargetMMOFlags( 191 const Instruction &I) const override; 192 193 // Inline asm support 194 std::pair<unsigned, const TargetRegisterClass *> 195 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 196 StringRef Constraint, MVT VT) const override; 197 198 // Expand specifics 199 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; 200 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const; 201 202 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 203 204 void computeKnownBitsForTargetNode(const SDValue Op, 205 KnownBits &Known, 206 const APInt &DemandedElts, 207 const SelectionDAG &DAG, 208 unsigned Depth = 0) const override; 209 210 SDValue 211 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 212 const SmallVectorImpl<ISD::InputArg> &Ins, 213 const SDLoc &dl, SelectionDAG &DAG, 214 SmallVectorImpl<SDValue> &InVals) const override; 215 216 SDValue 217 LowerCall(TargetLowering::CallLoweringInfo &CLI, 218 SmallVectorImpl<SDValue> &InVals) const override; 219 220 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 221 const SmallVectorImpl<ISD::OutputArg> &Outs, 222 const SmallVectorImpl<SDValue> &OutVals, 223 const SDLoc &dl, SelectionDAG &DAG) const override; 224 225 bool 226 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 227 bool isVarArg, 228 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, 229 LLVMContext &Context) const override; 230 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 231 return true; 232 } 233 }; 234 } 235 236 #endif 237
Indexes created Thu Oct 15 00:24:41 UTC 2026