1 /* $NetBSD: tegra124_xusbpadreg.h,v 1.3 2017/09/22 20:23:22 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_TEGRA124_XUSBPADREG_H 30 #define _ARM_TEGRA_TEGRA124_XUSBPADREG_H 31 32 #define XUSB_PADCTL_BOOT_MEDIA_REG 0x000 33 #define XUSB_PADCTL_USB2_PAD_MUX_REG 0x004 34 #define XUSB_PADCTL_USB2_PORT_CAP_REG 0x008 35 #define XUSB_PADCTL_SNPS_OC_MAP_REG 0x00c 36 #define XUSB_PADCTL_USB2_OC_MAP_REG 0x010 37 #define XUSB_PADCTL_SS_PORT_MAP_REG 0x014 38 #define XUSB_PADCTL_OC_DET_REG 0x018 39 #define XUSB_PADCTL_ELPG_PROGRAM_REG 0x01c 40 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_REG 0x020 41 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_REG 0x024 42 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_REG 0x028 43 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_REG 0x02c 44 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_REG 0x030 45 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_REG 0x034 46 #define XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG 0x038 47 #define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_REG 0x03c 48 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REG 0x040 49 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REG 0x044 50 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL3_REG 0x048 51 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL4_REG 0x04c 52 #define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL1_REG 0x050 53 #define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL1_REG 0x054 54 #define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL2_REG 0x058 55 #define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL2_REG 0x05c 56 #define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL3_REG 0x060 57 #define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL3_REG 0x064 58 #define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL4_REG 0x068 59 #define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL4_REG 0x06c 60 #define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL1_REG 0x070 61 #define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL1_REG 0x074 62 #define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL2_REG 0x078 63 #define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL2_REG 0x07c 64 #define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL3_REG 0x080 65 #define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL3_REG 0x084 66 #define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL4_REG 0x088 67 #define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL4_REG 0x08c 68 #define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL5_REG 0x090 69 #define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL5_REG 0x094 70 #define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL6_REG 0x098 71 #define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL6_REG 0x09c 72 #define XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG 0x0a0 73 #define XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG 0x0a4 74 #define XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG 0x0a8 75 #define XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG 0x0ac 76 #define XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG 0x0b0 77 #define XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG 0x0b4 78 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG 0x0b8 79 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_REG 0x0bc 80 #define XUSB_PADCTL_HSIC_PAD0_CTL0_REG 0x0c0 81 #define XUSB_PADCTL_HSIC_PAD1_CTL0_REG 0x0c4 82 #define XUSB_PADCTL_HSIC_PAD0_CTL1_REG 0x0c8 83 #define XUSB_PADCTL_HSIC_PAD1_CTL1_REG 0x0cc 84 #define XUSB_PADCTL_HSIC_PAD0_CTL2_REG 0x0d0 85 #define XUSB_PADCTL_HSIC_PAD1_CTL2_REG 0x0d4 86 #define XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_REG 0x0d8 87 #define XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_REG 0x0dc 88 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_REG 0x0e0 89 #define XUSB_PADCTL_WAKE_CTRL_REG 0x0e4 90 #define XUSB_PADCTL_PM_SPARE_REG 0x0e8 91 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL1_REG 0x0ec 92 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL1_REG 0x0f0 93 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL1_REG 0x0f4 94 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL2_REG 0x0f8 95 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL2_REG 0x0fc 96 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL2_REG 0x100 97 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL3_REG 0x104 98 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL3_REG 0x108 99 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL3_REG 0x10c 100 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL4_REG 0x110 101 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL4_REG 0x114 102 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL4_REG 0x118 103 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL5_REG 0x11c 104 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL5_REG 0x120 105 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL5_REG 0x124 106 #define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL6_REG 0x128 107 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL6_REG 0x12c 108 #define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL6_REG 0x130 109 #define XUSB_PADCTL_USB3_PAD_MUX_REG 0x134 110 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG 0x138 111 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_REG 0x13c 112 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3_REG 0x140 113 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL4_REG 0x144 114 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG 0x148 115 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2_REG 0x14c 116 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3_REG 0x150 117 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4_REG 0x154 118 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5_REG 0x158 119 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6_REG 0x15c 120 121 #define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD2 __BIT(22) 122 #define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD1 __BIT(21) 123 #define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD0 __BIT(20) 124 #define XUSB_PADCTL_OC_DET_OC_DETECTED3 __BIT(19) 125 #define XUSB_PADCTL_OC_DET_OC_DETECTED2 __BIT(18) 126 #define XUSB_PADCTL_OC_DET_OC_DETECTED1 __BIT(17) 127 #define XUSB_PADCTL_OC_DET_OC_DETECTED0 __BIT(16) 128 #define XUSB_PADCTL_OC_DET_VBUS_ENABLE1 __BIT(9) 129 #define XUSB_PADCTL_OC_DET_VBUS_ENABLE0 __BIT(8) 130 #define XUSB_PADCTL_OC_DET_VBUS_ENABLE2 __BIT(4) 131 132 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN __BIT(26) 133 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY __BIT(25) 134 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN __BIT(24) 135 #define XUSB_PADCTL_ELPG_PROGRAM_SSP1_ELPG_VCORE_DOWN __BIT(22) 136 #define XUSB_PADCTL_ELPG_PROGRAM_SSP1_ELPG_CLAMP_EN_EARLY __BIT(21) 137 #define XUSB_PADCTL_ELPG_PROGRAM_SSP1_ELPG_CLAMP_EN __BIT(20) 138 #define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN __BIT(18) 139 #define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY __BIT(17) 140 #define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN __BIT(16) 141 142 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI __BIT(21) 143 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 __BIT(20) 144 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD __BIT(19) 145 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW __BITS(15,14) 146 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(pad) ((pad >= 1) ? 0x0 : 0x3) 147 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW __BITS(11,6) 148 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL 0x0e 149 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL __BITS(5,0) 150 151 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP __BITS(10,9) 152 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ __BITS(6,3) 153 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR __BIT(2) 154 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP __BIT(1) 155 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP __BIT(0) 156 157 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK __BIT(13) 158 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD __BIT(12) 159 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL __BITS(4,2) 160 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x5 161 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL __BITS(1,0) 162 163 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0 __BITS(27,26) 164 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_PCIE 0 165 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_USB3_SS 1 166 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA 2 167 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 __BIT(6) 168 169 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET __BIT(27) 170 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE __BIT(24) 171 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD __BIT(3) 172 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST __BIT(1) 173 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ __BIT(0) 174 175 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD __BIT(1) 176 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ __BIT(0) 177 178 #endif /* _ARM_TEGRA_TEGRA124_XUSBPADREG_H */ 179
Indexes created Sun Sep 21 14:09:52 GMT 2025