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      1 /*	$NetBSD: zynq_usbreg.h,v 1.2 2024/02/08 11:31:00 andvar Exp $	*/
      2 /*-
      3  * Copyright (c) 2015  Genetec Corporation.  All rights reserved.
      4  * Written by Hashimoto Kenichi for Genetec Corporation.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     16  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef _ARM_XILINX_ZYNQUSBREG_H
     29 #define _ARM_XILINX_ZYNQUSBREG_H
     30 
     31 #define	ZYNQUSB_ID		0x0000
     32 #define	 ZYNQUSB_ID_ID		__BITS(5,0)
     33 #define	 ZYNQUSB_ID_NID		__BITS(13,8)
     34 #define	 ZYNQUSB_ID_TAG		__BITS(20,16)
     35 #define	 ZYNQUSB_ID_REVISION	__BITS(24,21)
     36 #define	 ZYNQUSB_ID_VERSION	__BITS(28,25)
     37 #define	 ZYNQUSB_ID_CIVERSION	__BITS(31,29)
     38 #define	ZYNQUSB_HWGENERAL	0x0004
     39 #define	ZYNQUSB_HWHOST		0x0008
     40 #define	 HWHOST_HC		__BIT(0)
     41 #define	 HWHOST_NPORT		__BITS(3,1)
     42 #define	ZYNQUSB_HWDEVICE	0x000c
     43 #define	 HWDEVICE_DC		__BIT(0)
     44 #define	 HWDEVICE_DEVEP		__BITS(5,1)
     45 #define	ZYNQUSB_HWTXBUF		0x0010
     46 #define	ZYNQUSB_HWRXBUF		0x0014
     47 
     48 #define	ZYNQUSB_EHCIREGS	0x0100
     49 
     50 #define	ZYNQUSB_ULPIVIEW	0x0170
     51 #define	 ULPI_WU		__BIT(31)
     52 #define	 ULPI_RUN		__BIT(30)
     53 #define	 ULPI_RW		__BIT(29)
     54 #define	 ULPI_SS		__BIT(27)
     55 #define	 ULPI_PORT		__BITS(26,24)
     56 #define	 ULPI_ADDR		__BITS(23,16)
     57 #define	 ULPI_DATRD		__BITS(15,8)
     58 #define	 ULPI_DATWR		__BITS(7,0)
     59 
     60 #define	ZYNQUSB_OTGSC		0x01A4
     61 #define	 OTGSC_DPIE		__BIT(30)
     62 #define	 OTGSC_1MSE		__BIT(29)
     63 #define	 OTGSC_BSEIE		__BIT(28)
     64 #define	 OTGSC_BSVIE		__BIT(27)
     65 #define	 OTGSC_ASVIE		__BIT(26)
     66 #define	 OTGSC_AVVIE		__BIT(25)
     67 #define	 OTGSC_IDIE		__BIT(24)
     68 #define	 OTGSC_DPIS		__BIT(22)
     69 #define	 OTGSC_1MSS		__BIT(21)
     70 #define	 OTGSC_BSEIS		__BIT(20)
     71 #define	 OTGSC_BSVIS		__BIT(19)
     72 #define	 OTGSC_ASVIS		__BIT(18)
     73 #define	 OTGSC_AVVIS		__BIT(17)
     74 #define	 OTGSC_IDIS		__BIT(16)
     75 #define	 OTGSC_DPS		__BIT(14)
     76 #define	 OTGSC_1MST		__BIT(13)
     77 #define	 OTGSC_BSE		__BIT(12)
     78 #define	 OTGSC_BSV		__BIT(11)
     79 #define	 OTGSC_ASV		__BIT(10)
     80 #define	 OTGSC_AVV		__BIT( 9)
     81 #define	 OTGSC_ID		__BIT( 8)
     82 #define  OTGSC_HABA		__BIT( 7)
     83 #define  OTGSC_HADP		__BIT( 6)
     84 #define	 OTGSC_IDPU		__BIT( 5)
     85 #define	 OTGSC_DP		__BIT( 4)
     86 #define	 OTGSC_OT		__BIT( 3)
     87 #define  OTGSC_HAAR		__BIT( 2)
     88 #define	 OTGSC_VC		__BIT( 1)
     89 #define	 OTGSC_VD		__BIT( 0)
     90 #define	ZYNQUSB_USBMODE		0x01A8
     91 #define	 USBMODE_CM		__BITS(1,0)
     92 #define	 USBMODE_CM_IDLE	__SHIFTIN(0, USBMODE_CM)
     93 #define	 USBMODE_CM_DEVICE	__SHIFTIN(2, USBMODE_CM)
     94 #define	 USBMODE_CM_HOST	__SHIFTIN(3, USBMODE_CM)
     95 
     96 #define	ZYNQUSB_EHCI_SIZE	0x200
     97 
     98 /* extension to PORTSCx register of EHCI. */
     99 #define	PORTSC_PTS		__BITS(31,30)
    100 #define	PORTSC_PTS_UTMI		__SHIFTIN(0, PORTSC_PTS)
    101 #define	PORTSC_PTS_PHILIPS	__SHIFTIN(1, PORTSC_PTS)
    102 #define	PORTSC_PTS_ULPI		__SHIFTIN(2, PORTSC_PTS)
    103 #define	PORTSC_PTS_SERIAL	__SHIFTIN(3, PORTSC_PTS)
    104 #define	PORTSC_STS		__BIT(29)	/* serial transceiver select */
    105 #define	PORTSC_PTW		__BIT(28)	/* parallel transceiver width */
    106 #define	PORTSC_PTW_8		0
    107 #define	PORTSC_PTW_16		PORTSC_PTW
    108 #define	PORTSC_PSPD		__BITS(26,27)	/* port speed (RO) */
    109 #define	PORTSC_PFSC		__BIT(24)	/* port force full speed */
    110 #define	PORTSC_PHCD		__BIT(23)	/* PHY low power suspend */
    111 
    112 #endif /* _ARM_XILINX_ZYNQUSBREG_H */
    113