1 /* $NetBSD: cacheops.c,v 1.16 2026/03/29 20:56:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_m68k_arch.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: cacheops.c,v 1.16 2026/03/29 20:56:00 thorpej Exp $"); 36 37 #include <sys/types.h> 38 #include <machine/cpu.h> 39 #include <m68k/cacheops.h> 40 #ifdef M68K_CACHEOPS_MACHDEP 41 #include <machine/cacheops_machdep.h> 42 #endif 43 44 /* XXX MMU and cache operations should not be intermingled. */ 45 #if defined(M68K_MMU_MOTOROLA) || defined(M68K_MMU_HP) 46 void 47 _TBIA(void) 48 { 49 50 #ifdef M68K_CACHEOPS_MACHDEP_TBIA 51 if (TBIA_md()) 52 return; 53 #endif 54 55 switch (cputype) { 56 default: 57 #ifdef M68020 58 case CPU_68020: 59 TBIA_20(); 60 break; 61 #endif 62 #ifdef M68030 63 case CPU_68030: 64 TBIA_30(); 65 break; 66 #endif 67 #ifdef M68040 68 case CPU_68040: 69 TBIA_40(); 70 break; 71 #endif 72 #ifdef M68060 73 case CPU_68060: 74 TBIA_60(); 75 break; 76 #endif 77 } 78 } 79 80 void 81 _TBIAS(void) 82 { 83 84 #ifdef M68K_CACHEOPS_MACHDEP_TBIAS 85 if (TBIAS_md()) 86 return; 87 #endif 88 89 switch (cputype) { 90 default: 91 #ifdef M68020 92 case CPU_68020: 93 TBIAS_20(); 94 break; 95 #endif 96 #ifdef M68030 97 case CPU_68030: 98 TBIAS_30(); 99 break; 100 #endif 101 #ifdef M68040 102 case CPU_68040: 103 TBIAS_40(); 104 break; 105 #endif 106 #ifdef M68060 107 case CPU_68060: 108 TBIAS_60(); 109 break; 110 #endif 111 } 112 } 113 114 void 115 _TBIAU(void) 116 { 117 118 #ifdef M68K_CACHEOPS_MACHDEP_TBIAU 119 if (TBIAU_md()) 120 return; 121 #endif 122 123 switch (cputype) { 124 default: 125 #ifdef M68020 126 case CPU_68020: 127 TBIAU_20(); 128 break; 129 #endif 130 #ifdef M68030 131 case CPU_68030: 132 TBIAU_30(); 133 break; 134 #endif 135 #ifdef M68040 136 case CPU_68040: 137 TBIAU_40(); 138 break; 139 #endif 140 #ifdef M68060 141 case CPU_68060: 142 TBIAU_60(); 143 break; 144 #endif 145 } 146 } 147 148 void 149 _TBIS(vaddr_t va) 150 { 151 152 #ifdef M68K_CACHEOPS_MACHDEP_TBIS 153 if (TBIS_md(va)) 154 return; 155 #endif 156 157 switch (cputype) { 158 default: 159 #ifdef M68020 160 case CPU_68020: 161 TBIS_20(va); 162 break; 163 #endif 164 #ifdef M68030 165 case CPU_68030: 166 TBIS_30(va); 167 break; 168 #endif 169 #ifdef M68040 170 case CPU_68040: 171 TBIS_40(va); 172 break; 173 #endif 174 #ifdef M68060 175 case CPU_68060: 176 TBIS_60(va); 177 break; 178 #endif 179 } 180 } 181 #endif /* M68K_MMU_MOTOROLA || M68K_MMU_HP */ 182 183 void 184 _ICIA(void) 185 { 186 187 switch (cputype) { 188 default: 189 #ifdef M68020 190 case CPU_68020: 191 ICIA_20(); 192 break; 193 #endif 194 #ifdef M68030 195 case CPU_68030: 196 ICIA_30(); 197 break; 198 #endif 199 #ifdef M68040 200 case CPU_68040: 201 ICIA_40(); 202 break; 203 #endif 204 #ifdef M68060 205 case CPU_68060: 206 ICIA_60(); 207 break; 208 #endif 209 } 210 } 211 212 void 213 _ICPA(void) 214 { 215 216 switch (cputype) { 217 default: 218 #ifdef M68020 219 case CPU_68020: 220 ICPA_20(); 221 break; 222 #endif 223 #ifdef M68030 224 case CPU_68030: 225 ICPA_30(); 226 break; 227 #endif 228 #ifdef M68040 229 case CPU_68040: 230 ICPA_40(); 231 break; 232 #endif 233 #ifdef M68060 234 case CPU_68060: 235 ICPA_60(); 236 break; 237 #endif 238 } 239 } 240 241 void 242 _DCIA(void) 243 { 244 245 #ifdef M68K_CACHEOPS_MACHDEP_DCIA 246 if (DCIA_md()) 247 return; 248 #endif 249 250 switch (cputype) { 251 default: 252 #ifdef M68020 253 case CPU_68020: 254 DCIA_20(); 255 break; 256 #endif 257 #ifdef M68030 258 case CPU_68030: 259 DCIA_30(); 260 break; 261 #endif 262 #ifdef M68040 263 case CPU_68040: 264 DCIA_40(); 265 break; 266 #endif 267 #ifdef M68060 268 case CPU_68060: 269 DCIA_60(); 270 break; 271 #endif 272 } 273 } 274 275 void 276 _DCIS(void) 277 { 278 279 #ifdef M68K_CACHEOPS_MACHDEP_DCIS 280 if (DCIS_md()) 281 return; 282 #endif 283 284 switch (cputype) { 285 default: 286 #ifdef M68020 287 case CPU_68020: 288 DCIS_20(); 289 break; 290 #endif 291 #ifdef M68030 292 case CPU_68030: 293 DCIS_30(); 294 break; 295 #endif 296 #ifdef M68040 297 case CPU_68040: 298 DCIS_40(); 299 break; 300 #endif 301 #ifdef M68060 302 case CPU_68060: 303 DCIS_60(); 304 break; 305 #endif 306 } 307 } 308 309 void 310 _DCIU(void) 311 { 312 313 #ifdef M68K_CACHEOPS_MACHDEP_DCIU 314 if (DCIU_md()) 315 return; 316 #endif 317 318 switch (cputype) { 319 default: 320 #ifdef M68020 321 case CPU_68020: 322 DCIU_20(); 323 break; 324 #endif 325 #ifdef M68030 326 case CPU_68030: 327 DCIU_30(); 328 break; 329 #endif 330 #ifdef M68040 331 case CPU_68040: 332 DCIU_40(); 333 break; 334 #endif 335 #ifdef M68060 336 case CPU_68060: 337 DCIU_60(); 338 break; 339 #endif 340 } 341 } 342 343 void 344 _PCIA(void) 345 { 346 347 #ifdef M68K_CACHEOPS_MACHDEP_PCIA 348 if (PCIA_md()) 349 return; 350 #endif 351 352 switch (cputype) { 353 default: 354 #ifdef M68020 355 case CPU_68020: 356 PCIA_20(); 357 break; 358 #endif 359 #ifdef M68030 360 case CPU_68030: 361 PCIA_30(); 362 break; 363 #endif 364 #ifdef M68040 365 case CPU_68040: 366 PCIA_40(); 367 break; 368 #endif 369 #ifdef M68060 370 case CPU_68060: 371 PCIA_60(); 372 break; 373 #endif 374 } 375 } 376 377 void 378 _DCIAS(paddr_t pa) 379 { 380 381 switch (cputype) { 382 default: 383 #ifdef M68020 384 case CPU_68020: 385 DCIAS_20(pa); 386 break; 387 #endif 388 #ifdef M68030 389 case CPU_68030: 390 DCIAS_30(pa); 391 break; 392 #endif 393 #ifdef M68040 394 case CPU_68040: 395 DCIAS_40(pa); 396 break; 397 #endif 398 #ifdef M68060 399 case CPU_68060: 400 DCIAS_60(pa); 401 break; 402 #endif 403 } 404 } 405
Indexes created Thu Aug 13 00:25:44 UTC 2026