1 /* $NetBSD: devreg.c,v 1.8 2009/03/18 10:22:36 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: devreg.c,v 1.8 2009/03/18 10:22:36 cegger Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sh3/exception.h> 35 #include <sh3/cache_sh3.h> 36 #include <sh3/cache_sh4.h> 37 #include <sh3/mmu_sh3.h> 38 #include <sh3/mmu_sh4.h> 39 40 #include <sh3/ubcreg.h> 41 #include <sh3/rtcreg.h> 42 #include <sh3/tmureg.h> 43 44 /* MMU */ 45 uint32_t __sh_PTEH; 46 uint32_t __sh_TTB; 47 uint32_t __sh_TEA; 48 uint32_t __sh_TRA; 49 uint32_t __sh_EXPEVT; 50 uint32_t __sh_INTEVT; 51 52 /* UBC */ 53 uint32_t __sh_BARA; 54 uint32_t __sh_BAMRA; 55 uint32_t __sh_BASRA; 56 uint32_t __sh_BBRA; 57 uint32_t __sh_BARB; 58 uint32_t __sh_BAMRB; 59 uint32_t __sh_BASRB; 60 uint32_t __sh_BBRB; 61 uint32_t __sh_BDRB; 62 uint32_t __sh_BDMRB; 63 uint32_t __sh_BRCR; 64 65 /* RTC */ 66 uint32_t __sh_R64CNT; 67 uint32_t __sh_RSECCNT; 68 uint32_t __sh_RMINCNT; 69 uint32_t __sh_RHRCNT; 70 uint32_t __sh_RWKCNT; 71 uint32_t __sh_RDAYCNT; 72 uint32_t __sh_RMONCNT; 73 uint32_t __sh_RYRCNT; 74 uint32_t __sh_RSECAR; 75 uint32_t __sh_RMINAR; 76 uint32_t __sh_RHRAR; 77 uint32_t __sh_RWKAR; 78 uint32_t __sh_RDAYAR; 79 uint32_t __sh_RMONAR; 80 uint32_t __sh_RCR1; 81 uint32_t __sh_RCR2; 82 83 /* TMU */ 84 uint32_t __sh_TOCR; 85 uint32_t __sh_TSTR; 86 uint32_t __sh_TCOR0; 87 uint32_t __sh_TCNT0; 88 uint32_t __sh_TCR0; 89 uint32_t __sh_TCOR1; 90 uint32_t __sh_TCNT1; 91 uint32_t __sh_TCR1; 92 uint32_t __sh_TCOR2; 93 uint32_t __sh_TCNT2; 94 uint32_t __sh_TCR2; 95 uint32_t __sh_TCPR2; 96 97 #define SH3REG(x) __sh_ ## x = SH3_ ## x 98 #define SH4REG(x) __sh_ ## x = SH4_ ## x 99 100 #define SHREG(x) \ 101 do { \ 102 /* Exception */ \ 103 SH ## x ## REG(TRA); \ 104 SH ## x ## REG(EXPEVT); \ 105 SH ## x ## REG(INTEVT); \ 106 /* UBC */ \ 107 SH ## x ## REG(BARA); \ 108 SH ## x ## REG(BAMRA); \ 109 SH ## x ## REG(BASRA); \ 110 SH ## x ## REG(BBRA); \ 111 SH ## x ## REG(BARB); \ 112 SH ## x ## REG(BAMRB); \ 113 SH ## x ## REG(BASRB); \ 114 SH ## x ## REG(BBRB); \ 115 SH ## x ## REG(BDRB); \ 116 SH ## x ## REG(BDMRB); \ 117 SH ## x ## REG(BRCR); \ 118 /* MMU */ \ 119 SH ## x ## REG(PTEH); \ 120 SH ## x ## REG(TEA); \ 121 SH ## x ## REG(TTB); \ 122 /* RTC */ \ 123 SH ## x ## REG(R64CNT); \ 124 SH ## x ## REG(RSECCNT); \ 125 SH ## x ## REG(RMINCNT); \ 126 SH ## x ## REG(RHRCNT); \ 127 SH ## x ## REG(RWKCNT); \ 128 SH ## x ## REG(RDAYCNT); \ 129 SH ## x ## REG(RMONCNT); \ 130 SH ## x ## REG(RYRCNT); \ 131 SH ## x ## REG(RSECAR); \ 132 SH ## x ## REG(RMINAR); \ 133 SH ## x ## REG(RHRAR); \ 134 SH ## x ## REG(RWKAR); \ 135 SH ## x ## REG(RDAYAR); \ 136 SH ## x ## REG(RMONAR); \ 137 SH ## x ## REG(RCR1); \ 138 SH ## x ## REG(RCR2); \ 139 /* TMU */ \ 140 SH ## x ## REG(TOCR); \ 141 SH ## x ## REG(TSTR); \ 142 SH ## x ## REG(TCOR0); \ 143 SH ## x ## REG(TCNT0); \ 144 SH ## x ## REG(TCR0); \ 145 SH ## x ## REG(TCOR1); \ 146 SH ## x ## REG(TCNT1); \ 147 SH ## x ## REG(TCR1); \ 148 SH ## x ## REG(TCOR2); \ 149 SH ## x ## REG(TCNT2); \ 150 SH ## x ## REG(TCR2); \ 151 SH ## x ## REG(TCPR2); \ 152 } while (/*CONSTCOND*/0) 153 154 void 155 sh_devreg_init(void) 156 { 157 158 if (CPU_IS_SH3) 159 SHREG(3); 160 161 if (CPU_IS_SH4) 162 SHREG(4); 163 164 } 165