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      1 // SPDX-License-Identifier: GPL-2.0-only
      2 /*
      3  * Device Tree Source for OMAP34XX/OMAP36XX clock data
      4  *
      5  * Copyright (C) 2013 Texas Instruments, Inc.
      6  */
      7 &cm_clocks {
      8 	security_l4_ick2: security_l4_ick2 {
      9 		#clock-cells = <0>;
     10 		compatible = "fixed-factor-clock";
     11 		clocks = <&l4_ick>;
     12 		clock-mult = <1>;
     13 		clock-div = <1>;
     14 	};
     15 
     16 	aes1_ick: aes1_ick@a14 {
     17 		#clock-cells = <0>;
     18 		compatible = "ti,omap3-interface-clock";
     19 		clocks = <&security_l4_ick2>;
     20 		ti,bit-shift = <3>;
     21 		reg = <0x0a14>;
     22 	};
     23 
     24 	rng_ick: rng_ick@a14 {
     25 		#clock-cells = <0>;
     26 		compatible = "ti,omap3-interface-clock";
     27 		clocks = <&security_l4_ick2>;
     28 		reg = <0x0a14>;
     29 		ti,bit-shift = <2>;
     30 	};
     31 
     32 	sha11_ick: sha11_ick@a14 {
     33 		#clock-cells = <0>;
     34 		compatible = "ti,omap3-interface-clock";
     35 		clocks = <&security_l4_ick2>;
     36 		reg = <0x0a14>;
     37 		ti,bit-shift = <1>;
     38 	};
     39 
     40 	des1_ick: des1_ick@a14 {
     41 		#clock-cells = <0>;
     42 		compatible = "ti,omap3-interface-clock";
     43 		clocks = <&security_l4_ick2>;
     44 		reg = <0x0a14>;
     45 		ti,bit-shift = <0>;
     46 	};
     47 
     48 	cam_mclk: cam_mclk@f00 {
     49 		#clock-cells = <0>;
     50 		compatible = "ti,gate-clock";
     51 		clocks = <&dpll4_m5x2_ck>;
     52 		ti,bit-shift = <0>;
     53 		reg = <0x0f00>;
     54 		ti,set-rate-parent;
     55 	};
     56 
     57 	cam_ick: cam_ick@f10 {
     58 		#clock-cells = <0>;
     59 		compatible = "ti,omap3-no-wait-interface-clock";
     60 		clocks = <&l4_ick>;
     61 		reg = <0x0f10>;
     62 		ti,bit-shift = <0>;
     63 	};
     64 
     65 	csi2_96m_fck: csi2_96m_fck@f00 {
     66 		#clock-cells = <0>;
     67 		compatible = "ti,gate-clock";
     68 		clocks = <&core_96m_fck>;
     69 		reg = <0x0f00>;
     70 		ti,bit-shift = <1>;
     71 	};
     72 
     73 	security_l3_ick: security_l3_ick {
     74 		#clock-cells = <0>;
     75 		compatible = "fixed-factor-clock";
     76 		clocks = <&l3_ick>;
     77 		clock-mult = <1>;
     78 		clock-div = <1>;
     79 	};
     80 
     81 	pka_ick: pka_ick@a14 {
     82 		#clock-cells = <0>;
     83 		compatible = "ti,omap3-interface-clock";
     84 		clocks = <&security_l3_ick>;
     85 		reg = <0x0a14>;
     86 		ti,bit-shift = <4>;
     87 	};
     88 
     89 	icr_ick: icr_ick@a10 {
     90 		#clock-cells = <0>;
     91 		compatible = "ti,omap3-interface-clock";
     92 		clocks = <&core_l4_ick>;
     93 		reg = <0x0a10>;
     94 		ti,bit-shift = <29>;
     95 	};
     96 
     97 	des2_ick: des2_ick@a10 {
     98 		#clock-cells = <0>;
     99 		compatible = "ti,omap3-interface-clock";
    100 		clocks = <&core_l4_ick>;
    101 		reg = <0x0a10>;
    102 		ti,bit-shift = <26>;
    103 	};
    104 
    105 	mspro_ick: mspro_ick@a10 {
    106 		#clock-cells = <0>;
    107 		compatible = "ti,omap3-interface-clock";
    108 		clocks = <&core_l4_ick>;
    109 		reg = <0x0a10>;
    110 		ti,bit-shift = <23>;
    111 	};
    112 
    113 	mailboxes_ick: mailboxes_ick@a10 {
    114 		#clock-cells = <0>;
    115 		compatible = "ti,omap3-interface-clock";
    116 		clocks = <&core_l4_ick>;
    117 		reg = <0x0a10>;
    118 		ti,bit-shift = <7>;
    119 	};
    120 
    121 	ssi_l4_ick: ssi_l4_ick {
    122 		#clock-cells = <0>;
    123 		compatible = "fixed-factor-clock";
    124 		clocks = <&l4_ick>;
    125 		clock-mult = <1>;
    126 		clock-div = <1>;
    127 	};
    128 
    129 	sr1_fck: sr1_fck@c00 {
    130 		#clock-cells = <0>;
    131 		compatible = "ti,wait-gate-clock";
    132 		clocks = <&sys_ck>;
    133 		reg = <0x0c00>;
    134 		ti,bit-shift = <6>;
    135 	};
    136 
    137 	sr2_fck: sr2_fck@c00 {
    138 		#clock-cells = <0>;
    139 		compatible = "ti,wait-gate-clock";
    140 		clocks = <&sys_ck>;
    141 		reg = <0x0c00>;
    142 		ti,bit-shift = <7>;
    143 	};
    144 
    145 	sr_l4_ick: sr_l4_ick {
    146 		#clock-cells = <0>;
    147 		compatible = "fixed-factor-clock";
    148 		clocks = <&l4_ick>;
    149 		clock-mult = <1>;
    150 		clock-div = <1>;
    151 	};
    152 
    153 	dpll2_fck: dpll2_fck@40 {
    154 		#clock-cells = <0>;
    155 		compatible = "ti,divider-clock";
    156 		clocks = <&core_ck>;
    157 		ti,bit-shift = <19>;
    158 		ti,max-div = <7>;
    159 		reg = <0x0040>;
    160 		ti,index-starts-at-one;
    161 	};
    162 
    163 	dpll2_ck: dpll2_ck@4 {
    164 		#clock-cells = <0>;
    165 		compatible = "ti,omap3-dpll-clock";
    166 		clocks = <&sys_ck>, <&dpll2_fck>;
    167 		reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
    168 		ti,low-power-stop;
    169 		ti,lock;
    170 		ti,low-power-bypass;
    171 	};
    172 
    173 	dpll2_m2_ck: dpll2_m2_ck@44 {
    174 		#clock-cells = <0>;
    175 		compatible = "ti,divider-clock";
    176 		clocks = <&dpll2_ck>;
    177 		ti,max-div = <31>;
    178 		reg = <0x0044>;
    179 		ti,index-starts-at-one;
    180 	};
    181 
    182 	iva2_ck: iva2_ck@0 {
    183 		#clock-cells = <0>;
    184 		compatible = "ti,wait-gate-clock";
    185 		clocks = <&dpll2_m2_ck>;
    186 		reg = <0x0000>;
    187 		ti,bit-shift = <0>;
    188 	};
    189 
    190 	modem_fck: modem_fck@a00 {
    191 		#clock-cells = <0>;
    192 		compatible = "ti,omap3-interface-clock";
    193 		clocks = <&sys_ck>;
    194 		reg = <0x0a00>;
    195 		ti,bit-shift = <31>;
    196 	};
    197 
    198 	sad2d_ick: sad2d_ick@a10 {
    199 		#clock-cells = <0>;
    200 		compatible = "ti,omap3-interface-clock";
    201 		clocks = <&l3_ick>;
    202 		reg = <0x0a10>;
    203 		ti,bit-shift = <3>;
    204 	};
    205 
    206 	mad2d_ick: mad2d_ick@a18 {
    207 		#clock-cells = <0>;
    208 		compatible = "ti,omap3-interface-clock";
    209 		clocks = <&l3_ick>;
    210 		reg = <0x0a18>;
    211 		ti,bit-shift = <3>;
    212 	};
    213 
    214 	mspro_fck: mspro_fck@a00 {
    215 		#clock-cells = <0>;
    216 		compatible = "ti,wait-gate-clock";
    217 		clocks = <&core_96m_fck>;
    218 		reg = <0x0a00>;
    219 		ti,bit-shift = <23>;
    220 	};
    221 };
    222 
    223 &cm_clockdomains {
    224 	cam_clkdm: cam_clkdm {
    225 		compatible = "ti,clockdomain";
    226 		clocks = <&cam_ick>, <&csi2_96m_fck>;
    227 	};
    228 
    229 	iva2_clkdm: iva2_clkdm {
    230 		compatible = "ti,clockdomain";
    231 		clocks = <&iva2_ck>;
    232 	};
    233 
    234 	dpll2_clkdm: dpll2_clkdm {
    235 		compatible = "ti,clockdomain";
    236 		clocks = <&dpll2_ck>;
    237 	};
    238 
    239 	wkup_clkdm: wkup_clkdm {
    240 		compatible = "ti,clockdomain";
    241 		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
    242 			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
    243 			 <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
    244 	};
    245 
    246 	d2d_clkdm: d2d_clkdm {
    247 		compatible = "ti,clockdomain";
    248 		clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
    249 	};
    250 
    251 	core_l4_clkdm: core_l4_clkdm {
    252 		compatible = "ti,clockdomain";
    253 		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
    254 			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
    255 			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
    256 			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
    257 			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
    258 			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
    259 			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
    260 			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
    261 			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
    262 			 <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
    263 			 <&rng_ick>, <&mspro_fck>;
    264 	};
    265 };
    266