1 /* $NetBSD: agp_i810.c,v 1.127 2026/06/21 17:09:44 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.127 2026/06/21 17:09:44 andvar Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/agpio.h> 37 #include <sys/atomic.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/proc.h> 44 #include <sys/systm.h> 45 #include <sys/xcall.h> 46 47 #include <dev/pci/agp_i810var.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcidevs.h> 53 54 55 #include "agp_intel.h" 56 57 #ifdef AGP_DEBUG 58 #define DPRINTF(sc, fmt, ...) \ 59 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 60 #else 61 #define DPRINTF(sc, fmt, ...) do {} while (0) 62 #endif 63 64 struct agp_softc *agp_i810_sc = NULL; 65 66 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 67 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 68 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 69 70 #define CHIP_I810 0 /* i810/i815 */ 71 #define CHIP_I830 1 /* 830M/845G */ 72 #define CHIP_I855 2 /* 852GM/855GM/865G */ 73 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 74 #define CHIP_I965 4 /* 965Q/965PM */ 75 #define CHIP_G33 5 /* G33/Q33/Q35 */ 76 #define CHIP_G4X 6 /* G45/Q45 */ 77 #define CHIP_PINEVIEW 7 /* Pineview */ 78 79 /* XXX hack, see below */ 80 static bus_addr_t agp_i810_vga_regbase; 81 static bus_size_t agp_i810_vga_regsize; 82 static bus_space_tag_t agp_i810_vga_bst; 83 static bus_space_handle_t agp_i810_vga_bsh; 84 85 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 86 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 87 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 88 static int agp_i810_unbind_page(struct agp_softc *, off_t); 89 static void agp_i810_flush_tlb(struct agp_softc *); 90 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 91 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 92 vsize_t); 93 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 94 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 95 off_t); 96 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 97 off_t); 98 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 99 struct agp_memory *, off_t); 100 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 101 102 static bool agp_i810_resume(device_t, const pmf_qual_t *); 103 static int agp_i810_init(struct agp_softc *); 104 105 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 106 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 107 static int agp_i810_init(struct agp_softc *); 108 109 static struct agp_methods agp_i810_methods = { 110 agp_i810_get_aperture, 111 agp_i810_set_aperture, 112 agp_i810_bind_page, 113 agp_i810_unbind_page, 114 agp_i810_flush_tlb, 115 agp_i810_enable, 116 agp_i810_alloc_memory, 117 agp_i810_free_memory, 118 agp_i810_bind_memory, 119 agp_i810_unbind_memory, 120 }; 121 122 int 123 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, 124 bus_addr_t addr, int flags) 125 { 126 u_int32_t pte; 127 128 /* 129 * Bits 11:4 (physical start address extension) should be zero. 130 * Flag bits 3:0 should be zero too. 131 * 132 * XXX This should be a kassert -- no reason for this routine 133 * to allow failure. 134 */ 135 if ((addr & 0xfff) != 0) 136 return EINVAL; 137 KASSERT(flags == (flags & 0x7)); 138 139 pte = (u_int32_t)addr; 140 /* 141 * We need to massage the pte if bus_addr_t is wider than 32 bits. 142 * The compiler isn't smart enough, hence the casts to uintmax_t. 143 */ 144 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 145 /* 965+ can do 36-bit addressing, add in the extra bits. */ 146 if (isc->chiptype == CHIP_I965 || 147 isc->chiptype == CHIP_G33 || 148 isc->chiptype == CHIP_PINEVIEW || 149 isc->chiptype == CHIP_G4X) { 150 if (((uintmax_t)addr >> 36) != 0) 151 return EINVAL; 152 pte |= (addr >> 28) & 0xf0; 153 } else { 154 if (((uintmax_t)addr >> 32) != 0) 155 return EINVAL; 156 } 157 } 158 159 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 160 4*(off >> AGP_PAGE_SHIFT), pte | flags); 161 162 return 0; 163 } 164 165 void 166 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 167 { 168 169 /* 170 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 171 * Out of paranoia, let's do the write barrier and posting 172 * read, because I don't have enough time or hardware to 173 * conduct conclusive tests. 174 */ 175 bus_space_barrier(isc->gtt_bst, isc->gtt_bsh, 0, isc->gtt_size, 176 BUS_SPACE_BARRIER_WRITE); 177 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 178 4*(off >> AGP_PAGE_SHIFT)); 179 } 180 181 static void 182 agp_flush_cache_ipi(void *cookie __unused) 183 { 184 185 agp_flush_cache(); 186 } 187 188 void 189 agp_i810_chipset_flush(struct agp_i810_softc *isc) 190 { 191 unsigned int timo = 20000; /* * 50 us = 1 s */ 192 193 switch (isc->chiptype) { 194 case CHIP_I810: 195 break; 196 case CHIP_I830: 197 case CHIP_I855: 198 /* 199 * Flush all CPU caches. If we're cold, we can't run 200 * xcalls, but there should be only one CPU up, so 201 * flushing only the local CPU's cache should suffice. 202 * 203 * XXX Come to think of it, do these chipsets appear in 204 * any multi-CPU systems? 205 */ 206 if (cold) { 207 agp_flush_cache(); 208 } else { 209 /* 210 * Caller may hold a spin lock, so use ipi(9) 211 * rather than xcall(9) here. 212 */ 213 ipi_msg_t msg = { .func = agp_flush_cache_ipi }; 214 kpreempt_disable(); 215 ipi_broadcast(&msg, /*skip_self*/false); 216 ipi_wait(&msg); 217 kpreempt_enable(); 218 } 219 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 220 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 221 if (timo-- == 0) 222 break; 223 DELAY(50); 224 } 225 break; 226 case CHIP_I915: 227 case CHIP_I965: 228 case CHIP_G33: 229 case CHIP_PINEVIEW: 230 case CHIP_G4X: 231 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 232 break; 233 } 234 } 235 236 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 237 static int 238 agp_i810_vgamatch(const struct pci_attach_args *pa) 239 { 240 241 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 242 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 243 return (0); 244 245 switch (PCI_PRODUCT(pa->pa_id)) { 246 case PCI_PRODUCT_INTEL_82810_GC: 247 case PCI_PRODUCT_INTEL_82810_DC100_GC: 248 case PCI_PRODUCT_INTEL_82810E_GC: 249 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 250 case PCI_PRODUCT_INTEL_82830MP_IV: 251 case PCI_PRODUCT_INTEL_82845G_IGD: 252 case PCI_PRODUCT_INTEL_82855GM_IGD: 253 case PCI_PRODUCT_INTEL_82865_IGD: 254 case PCI_PRODUCT_INTEL_82915G_IGD: 255 case PCI_PRODUCT_INTEL_82915GM_IGD: 256 case PCI_PRODUCT_INTEL_82945P_IGD: 257 case PCI_PRODUCT_INTEL_82945GM_IGD: 258 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 259 case PCI_PRODUCT_INTEL_82945GME_IGD: 260 case PCI_PRODUCT_INTEL_E7221_IGD: 261 case PCI_PRODUCT_INTEL_82965Q_IGD: 262 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 263 case PCI_PRODUCT_INTEL_82965PM_IGD: 264 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 265 case PCI_PRODUCT_INTEL_82G33_IGD: 266 case PCI_PRODUCT_INTEL_82G33_IGD_1: 267 case PCI_PRODUCT_INTEL_82965G_IGD: 268 case PCI_PRODUCT_INTEL_82965G_IGD_1: 269 case PCI_PRODUCT_INTEL_82965GME_IGD: 270 case PCI_PRODUCT_INTEL_82Q35_IGD: 271 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 272 case PCI_PRODUCT_INTEL_82Q33_IGD: 273 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 274 case PCI_PRODUCT_INTEL_82G35_IGD: 275 case PCI_PRODUCT_INTEL_82G35_IGD_1: 276 case PCI_PRODUCT_INTEL_82946GZ_IGD: 277 case PCI_PRODUCT_INTEL_82GM45_IGD: 278 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 279 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 280 case PCI_PRODUCT_INTEL_82Q45_IGD: 281 case PCI_PRODUCT_INTEL_82G45_IGD: 282 case PCI_PRODUCT_INTEL_82G41_IGD: 283 case PCI_PRODUCT_INTEL_82B43_IGD: 284 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 285 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 286 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 287 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 288 return (1); 289 } 290 291 return (0); 292 } 293 294 static int 295 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 296 { 297 /* 298 * Find the aperture. Don't map it (yet), this would 299 * eat KVA. 300 */ 301 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 302 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 303 &sc->as_apflags) != 0) 304 return ENXIO; 305 306 sc->as_apt = pa->pa_memt; 307 308 return 0; 309 } 310 311 int 312 agp_i810_attach(device_t parent, device_t self, void *aux) 313 { 314 struct agp_softc *sc = device_private(self); 315 struct agp_i810_softc *isc; 316 int apbase, mmadr_bar, gtt_bar; 317 int mmadr_type, mmadr_flags; 318 bus_addr_t mmadr; 319 bus_size_t mmadr_size, gtt_off; 320 int error; 321 322 isc = malloc(sizeof *isc, M_AGP, M_WAITOK|M_ZERO); 323 sc->as_chipc = isc; 324 sc->as_methods = &agp_i810_methods; 325 326 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 327 #if NAGP_INTEL > 0 328 const struct pci_attach_args *pa = aux; 329 330 switch (PCI_PRODUCT(pa->pa_id)) { 331 case PCI_PRODUCT_INTEL_82840_HB: 332 case PCI_PRODUCT_INTEL_82865_HB: 333 case PCI_PRODUCT_INTEL_82845G_DRAM: 334 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 335 case PCI_PRODUCT_INTEL_82855GM_MCH: 336 free(isc, M_AGP); 337 return agp_intel_attach(parent, self, aux); 338 } 339 #endif 340 aprint_error(": can't find internal VGA" 341 " config space\n"); 342 error = ENOENT; 343 goto fail1; 344 } 345 346 /* XXXfvdl */ 347 sc->as_dmat = isc->vga_pa.pa_dmat; 348 349 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 350 case PCI_PRODUCT_INTEL_82810_GC: 351 case PCI_PRODUCT_INTEL_82810_DC100_GC: 352 case PCI_PRODUCT_INTEL_82810E_GC: 353 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 354 isc->chiptype = CHIP_I810; 355 aprint_normal(": i810-family chipset\n"); 356 break; 357 case PCI_PRODUCT_INTEL_82830MP_IV: 358 case PCI_PRODUCT_INTEL_82845G_IGD: 359 isc->chiptype = CHIP_I830; 360 aprint_normal(": i830-family chipset\n"); 361 break; 362 case PCI_PRODUCT_INTEL_82855GM_IGD: 363 case PCI_PRODUCT_INTEL_82865_IGD: 364 isc->chiptype = CHIP_I855; 365 aprint_normal(": i855-family chipset\n"); 366 break; 367 case PCI_PRODUCT_INTEL_82915G_IGD: 368 case PCI_PRODUCT_INTEL_82915GM_IGD: 369 case PCI_PRODUCT_INTEL_82945P_IGD: 370 case PCI_PRODUCT_INTEL_82945GM_IGD: 371 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 372 case PCI_PRODUCT_INTEL_82945GME_IGD: 373 case PCI_PRODUCT_INTEL_E7221_IGD: 374 isc->chiptype = CHIP_I915; 375 aprint_normal(": i915-family chipset\n"); 376 break; 377 case PCI_PRODUCT_INTEL_82965Q_IGD: 378 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 379 case PCI_PRODUCT_INTEL_82965PM_IGD: 380 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 381 case PCI_PRODUCT_INTEL_82965G_IGD: 382 case PCI_PRODUCT_INTEL_82965G_IGD_1: 383 case PCI_PRODUCT_INTEL_82965GME_IGD: 384 case PCI_PRODUCT_INTEL_82946GZ_IGD: 385 case PCI_PRODUCT_INTEL_82G35_IGD: 386 case PCI_PRODUCT_INTEL_82G35_IGD_1: 387 isc->chiptype = CHIP_I965; 388 aprint_normal(": i965-family chipset\n"); 389 break; 390 case PCI_PRODUCT_INTEL_82Q35_IGD: 391 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 392 case PCI_PRODUCT_INTEL_82G33_IGD: 393 case PCI_PRODUCT_INTEL_82G33_IGD_1: 394 case PCI_PRODUCT_INTEL_82Q33_IGD: 395 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 396 isc->chiptype = CHIP_G33; 397 aprint_normal(": G33-family chipset\n"); 398 break; 399 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 400 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 401 isc->chiptype = CHIP_PINEVIEW; 402 aprint_normal(": Pineview chipset\n"); 403 break; 404 case PCI_PRODUCT_INTEL_82GM45_IGD: 405 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 406 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 407 case PCI_PRODUCT_INTEL_82Q45_IGD: 408 case PCI_PRODUCT_INTEL_82G45_IGD: 409 case PCI_PRODUCT_INTEL_82G41_IGD: 410 case PCI_PRODUCT_INTEL_82B43_IGD: 411 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 412 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 413 isc->chiptype = CHIP_G4X; 414 aprint_normal(": G4X-family chipset\n"); 415 break; 416 } 417 aprint_naive("\n"); 418 419 /* Discriminate on the chipset to choose the relevant BARs. */ 420 switch (isc->chiptype) { 421 case CHIP_I915: 422 case CHIP_G33: 423 case CHIP_PINEVIEW: 424 apbase = AGP_I915_GMADR; 425 mmadr_bar = AGP_I915_MMADR; 426 gtt_bar = AGP_I915_GTTADR; 427 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 428 break; 429 case CHIP_I965: 430 apbase = AGP_I965_GMADR; 431 mmadr_bar = AGP_I965_MMADR; 432 gtt_bar = 0; 433 gtt_off = AGP_I965_GTT; 434 break; 435 case CHIP_G4X: 436 apbase = AGP_I965_GMADR; 437 mmadr_bar = AGP_I965_MMADR; 438 gtt_bar = 0; 439 gtt_off = AGP_G4X_GTT; 440 break; 441 default: 442 apbase = AGP_I810_GMADR; 443 mmadr_bar = AGP_I810_MMADR; 444 gtt_bar = 0; 445 gtt_off = AGP_I810_GTT; 446 break; 447 } 448 449 /* 450 * Ensure the MMIO BAR is, in fact, a memory BAR. 451 * 452 * XXX This is required because we use pa_memt below. It is 453 * not a priori clear to me there is any other reason to 454 * require this. 455 */ 456 mmadr_type = pci_mapreg_type(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 457 mmadr_bar); 458 if (PCI_MAPREG_TYPE(mmadr_type) != PCI_MAPREG_TYPE_MEM) { 459 aprint_error_dev(self, "non-memory device MMIO registers\n"); 460 error = ENXIO; 461 goto fail1; 462 } 463 464 /* 465 * Determine the size of the MMIO registers. 466 * 467 * XXX The size of the MMIO registers we use is statically 468 * determined, as a function of the chipset, by the driver's 469 * implementation. 470 * 471 * On some chipsets, the GTT is part of the MMIO register BAR. 472 * We would like to map the GTT separately, so that we can map 473 * it prefetchable, which we can't do with the MMIO registers. 474 * Consequently, we would especially like to map a fixed size 475 * of MMIO registers, not just whatever size the BAR says. 476 * 477 * However, old drm assumes that the combined GTT/MMIO register 478 * space is a single bus space mapping, so mapping them 479 * separately breaks that. Once we rip out old drm, we can 480 * replace the pci_mapreg_info call by the chipset switch. 481 */ 482 #if notyet 483 switch (isc->chiptype) { 484 case CHIP_I810: 485 case CHIP_I830: 486 case CHIP_I855: 487 case CHIP_I915: 488 case CHIP_I965: 489 case CHIP_G33: 490 case CHIP_PINEVIEW: 491 case CHIP_G4X: 492 isc->size = 512*1024; 493 break; 494 case CHIP_SANDYBRIDGE: 495 case CHIP_IVYBRIDGE: 496 case CHIP_HASWELL: 497 isc->size = 2*1024*1024; 498 break; 499 } 500 #else 501 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 502 mmadr_bar, mmadr_type, NULL, &isc->size, NULL)) 503 isc->size = 512*1024; 504 #endif /* notyet */ 505 506 /* Map (or, rather, find the address and size of) the aperture. */ 507 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 508 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 509 else 510 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 511 if (error) { 512 aprint_error_dev(self, "can't map aperture: %d\n", error); 513 goto fail1; 514 } 515 516 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 517 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 518 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 519 aprint_error_dev(self, "can't find MMIO registers\n"); 520 error = ENXIO; 521 goto fail1; 522 } 523 if (mmadr_size < isc->size) { 524 aprint_error_dev(self, "MMIO registers too small" 525 ": %"PRIuMAX" < %"PRIuMAX"\n", 526 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 527 error = ENXIO; 528 goto fail1; 529 } 530 isc->bst = isc->vga_pa.pa_memt; 531 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 532 &isc->bsh); 533 if (error) { 534 aprint_error_dev(self, "can't map MMIO registers: %d\n", 535 error); 536 error = ENXIO; 537 goto fail1; 538 } 539 540 /* Set up a chipset flush page if necessary. */ 541 switch (isc->chiptype) { 542 case CHIP_I915: 543 case CHIP_I965: 544 case CHIP_G33: 545 case CHIP_PINEVIEW: 546 case CHIP_G4X: 547 error = agp_i810_setup_chipset_flush_page(sc); 548 if (error) { 549 aprint_error_dev(self, 550 "can't set up chipset flush page: %d\n", error); 551 goto fail2; 552 } 553 break; 554 } 555 556 /* 557 * XXX horrible hack to allow drm code to use our mapping 558 * of VGA chip registers 559 */ 560 agp_i810_vga_regbase = mmadr; 561 agp_i810_vga_regsize = isc->size; 562 agp_i810_vga_bst = isc->bst; 563 agp_i810_vga_bsh = isc->bsh; 564 565 /* Initialize the chipset. */ 566 error = agp_i810_init(sc); 567 if (error) 568 goto fail3; 569 570 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 571 if (gtt_bar == 0) { 572 isc->gtt_bst = isc->bst; 573 if ((mmadr_size - gtt_off) < isc->gtt_size) { 574 aprint_error_dev(self, "GTTMMADR too small for GTT" 575 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 576 (uintmax_t)mmadr_size, 577 (uintmax_t)gtt_off, 578 (uintmax_t)isc->gtt_size); 579 error = ENXIO; 580 goto fail4; 581 } 582 /* 583 * Map the GTT separately if we can, so that we can map 584 * it prefetchable, but in early models, there are MMIO 585 * registers before and after the GTT, so we can only 586 * take a subregion. 587 */ 588 if (isc->size < gtt_off) 589 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 590 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 591 else 592 error = bus_space_subregion(isc->bst, isc->bsh, 593 gtt_off, isc->gtt_size, &isc->gtt_bsh); 594 if (error) { 595 aprint_error_dev(self, "can't map GTT: %d\n", error); 596 error = ENXIO; 597 goto fail4; 598 } 599 } else { 600 bus_size_t gtt_bar_size; 601 /* 602 * All chipsets with a separate BAR for the GTT, namely 603 * the i915 and G33 families, have 32-bit GTT BARs. 604 * 605 * XXX [citation needed] 606 */ 607 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 608 0, 609 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 610 aprint_error_dev(self, "can't map GTT\n"); 611 error = ENXIO; 612 goto fail4; 613 } 614 if (gtt_bar_size != isc->gtt_size) { 615 aprint_error_dev(self, 616 "BAR size %"PRIxMAX 617 " mismatches detected GTT size %"PRIxMAX 618 "; trusting BAR\n", 619 (uintmax_t)gtt_bar_size, 620 (uintmax_t)isc->gtt_size); 621 isc->gtt_size = gtt_bar_size; 622 } 623 } 624 625 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 626 if (!pmf_device_register(self, NULL, agp_i810_resume)) 627 aprint_error_dev(self, "can't establish power handler\n"); 628 629 /* Match the generic AGP code's autoconf output format. */ 630 aprint_normal("%s", device_xname(self)); 631 632 /* Success! */ 633 return 0; 634 635 fail5: __unused 636 pmf_device_deregister(self); 637 if ((gtt_bar != 0) || (isc->size < gtt_off)) 638 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 639 isc->gtt_size = 0; 640 fail4: 641 #if notyet 642 agp_i810_fini(sc); 643 #endif 644 fail3: switch (isc->chiptype) { 645 case CHIP_I915: 646 case CHIP_I965: 647 case CHIP_G33: 648 case CHIP_PINEVIEW: 649 case CHIP_G4X: 650 agp_i810_teardown_chipset_flush_page(sc); 651 break; 652 } 653 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 654 isc->size = 0; 655 fail1: free(isc, M_AGP); 656 sc->as_chipc = NULL; 657 agp_generic_detach(sc); 658 KASSERT(error); 659 return error; 660 } 661 662 /* 663 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff, 664 * which includes the video BIOS at 0xc0000-0xdffff which the display 665 * drivers need for video mode detection. 666 * 667 * XXX Is there an MI name for this, or a conventional x86 name? Or 668 * should we really use bus_dma instead? 669 */ 670 #define PCIBIOS_MIN_MEM 0x100000 671 672 static int 673 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 674 { 675 struct agp_i810_softc *const isc = sc->as_chipc; 676 const pci_chipset_tag_t pc = sc->as_pc; 677 const pcitag_t tag = sc->as_tag; 678 pcireg_t lo, hi; 679 bus_addr_t addr, minaddr, maxaddr; 680 int error; 681 682 /* We always use memory-mapped I/O. */ 683 isc->flush_bst = isc->vga_pa.pa_memt; 684 685 /* No page allocated yet. */ 686 isc->flush_addr = 0; 687 688 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 689 if (isc->chiptype == CHIP_I915) { 690 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 691 minaddr = PCIBIOS_MIN_MEM; 692 maxaddr = UINT32_MAX; 693 } else { 694 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 695 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 696 /* 697 * Convert to uint64_t, rather than bus_addr_t which 698 * may be 32-bit, to avoid undefined behaviour with a 699 * too-wide shift. Since the BIOS doesn't know whether 700 * the OS will run 64-bit or with PAE, it ought to 701 * configure at most a 32-bit physical address, so 702 * let's print a warning in case that happens. 703 */ 704 addr = ((uint64_t)hi << 32) | lo; 705 if (hi) { 706 aprint_error_dev(sc->as_dev, 707 "BIOS configured >32-bit flush page address" 708 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 709 #if __i386__ && !PAE 710 return EIO; 711 #endif 712 } 713 minaddr = PCIBIOS_MIN_MEM; 714 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 715 } 716 717 /* Allocate or map a pre-allocated a page for it. */ 718 if (ISSET(addr, 1)) { 719 /* BIOS allocated it for us. Use that. */ 720 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 721 &isc->flush_bsh); 722 if (error) 723 return error; 724 } else { 725 /* None allocated. Allocate one. */ 726 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 727 PAGE_SIZE, PAGE_SIZE, 0, 0, 728 &isc->flush_addr, &isc->flush_bsh); 729 if (error) 730 return error; 731 KASSERT(isc->flush_addr != 0); 732 /* Write it into the PCI config register. */ 733 addr = isc->flush_addr | 1; 734 if (isc->chiptype == CHIP_I915) { 735 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 736 } else { 737 hi = __SHIFTOUT(addr, __BITS(63, 32)); 738 lo = __SHIFTOUT(addr, __BITS(31, 0)); 739 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 740 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 741 } 742 } 743 744 /* Success! */ 745 return 0; 746 } 747 748 static void 749 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 750 { 751 struct agp_i810_softc *const isc = sc->as_chipc; 752 753 if (isc->flush_addr) { 754 /* If we allocated a page, clear it. */ 755 if (isc->chiptype == CHIP_I915) { 756 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 757 0); 758 } else { 759 pci_conf_write(sc->as_pc, sc->as_tag, 760 AGP_I965_IFPADDR, 0); 761 pci_conf_write(sc->as_pc, sc->as_tag, 762 AGP_I965_IFPADDR + 4, 0); 763 } 764 isc->flush_addr = 0; 765 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 766 } else { 767 /* Otherwise, just unmap the pre-allocated page. */ 768 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 769 } 770 } 771 772 /* 773 * XXX horrible hack to allow drm code to use our mapping 774 * of VGA chip registers 775 */ 776 int 777 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 778 { 779 780 if (agp_i810_vga_regbase == 0) 781 return 0; 782 if (base < agp_i810_vga_regbase) 783 return 0; 784 if (agp_i810_vga_regsize < size) 785 return 0; 786 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 787 return 0; 788 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 789 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 790 hdlp)) 791 return 0; 792 return 1; 793 } 794 795 static int 796 agp_i810_init(struct agp_softc *sc) 797 { 798 struct agp_i810_softc *isc; 799 int error; 800 801 isc = sc->as_chipc; 802 803 if (isc->chiptype == CHIP_I810) { 804 struct agp_gatt *gatt; 805 void *virtual; 806 int dummyseg; 807 808 /* Some i810s have on-chip memory called dcache */ 809 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 810 isc->dcache_size = 4 * 1024 * 1024; 811 else 812 isc->dcache_size = 0; 813 814 /* According to the specs the gatt on the i810 must be 64k */ 815 isc->gtt_size = 64 * 1024; 816 gatt = malloc(sizeof(*gatt), M_AGP, M_WAITOK); 817 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 818 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 819 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 820 &gatt->ag_dmaseg, 1, &dummyseg); 821 if (error) { 822 aprint_error_dev(sc->as_dev, 823 "can't allocate memory for GTT: %d\n", error); 824 free(gatt, M_AGP); 825 goto fail0; 826 } 827 828 gatt->ag_virtual = (uint32_t *)virtual; 829 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 830 memset(gatt->ag_virtual, 0, gatt->ag_size); 831 agp_flush_cache(); 832 833 /* Install the GATT. */ 834 isc->pgtblctl = gatt->ag_physical | 1; 835 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 836 isc->gatt = gatt; 837 } else if (isc->chiptype == CHIP_I830) { 838 /* The i830 automatically initializes the 128k gatt on boot. */ 839 /* XXX [citation needed] */ 840 pcireg_t reg; 841 u_int16_t gcc1; 842 843 isc->gtt_size = 128 * 1024; 844 845 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 846 gcc1 = (u_int16_t)(reg >> 16); 847 switch (gcc1 & AGP_I830_GCC1_GMS) { 848 case AGP_I830_GCC1_GMS_STOLEN_512: 849 isc->stolen = (512 - 132) * 1024 / 4096; 850 break; 851 case AGP_I830_GCC1_GMS_STOLEN_1024: 852 isc->stolen = (1024 - 132) * 1024 / 4096; 853 break; 854 case AGP_I830_GCC1_GMS_STOLEN_8192: 855 isc->stolen = (8192 - 132) * 1024 / 4096; 856 break; 857 default: 858 isc->stolen = 0; 859 aprint_error_dev(sc->as_dev, 860 "unknown memory configuration, disabling\n"); 861 error = ENXIO; 862 goto fail0; 863 } 864 865 if (isc->stolen > 0) { 866 aprint_normal_dev(sc->as_dev, 867 "detected %dk stolen memory\n", 868 isc->stolen * 4); 869 } 870 871 /* GATT address is already in there, make sure it's enabled */ 872 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 873 isc->pgtblctl |= 1; 874 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 875 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 876 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 877 isc->chiptype == CHIP_PINEVIEW || 878 isc->chiptype == CHIP_G4X) { 879 pcireg_t reg; 880 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 881 u_int16_t gcc1; 882 883 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 884 gcc1 = (u_int16_t)(reg >> 16); 885 886 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 887 888 /* Stolen memory is set up at the beginning of the aperture by 889 * the BIOS, consisting of the GATT followed by 4kb for the 890 * BIOS display. 891 */ 892 switch (isc->chiptype) { 893 case CHIP_I855: 894 gtt_size = 128; 895 break; 896 case CHIP_I915: 897 gtt_size = 256; 898 break; 899 case CHIP_I965: 900 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 901 case AGP_I810_PGTBL_SIZE_128KB: 902 case AGP_I810_PGTBL_SIZE_512KB: 903 gtt_size = 512; 904 break; 905 case AGP_I965_PGTBL_SIZE_1MB: 906 gtt_size = 1024; 907 break; 908 case AGP_I965_PGTBL_SIZE_2MB: 909 gtt_size = 2048; 910 break; 911 case AGP_I965_PGTBL_SIZE_1_5MB: 912 gtt_size = 1024 + 512; 913 break; 914 default: 915 aprint_error_dev(sc->as_dev, 916 "bad PGTBL size\n"); 917 error = ENXIO; 918 goto fail0; 919 } 920 break; 921 case CHIP_G33: 922 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 923 case AGP_G33_PGTBL_SIZE_1M: 924 gtt_size = 1024; 925 break; 926 case AGP_G33_PGTBL_SIZE_2M: 927 gtt_size = 2048; 928 break; 929 default: 930 aprint_error_dev(sc->as_dev, 931 "bad PGTBL size\n"); 932 error = ENXIO; 933 goto fail0; 934 } 935 break; 936 case CHIP_PINEVIEW: 937 switch (gcc1 & AGP_PINEVIEW_PGTBL_SIZE_MASK) { 938 case AGP_PINEVIEW_PGTBL_SIZE_1M: 939 gtt_size = 1024; 940 break; 941 default: 942 aprint_error_dev(sc->as_dev, 943 "bad PGTBL size\n"); 944 error = ENXIO; 945 goto fail0; 946 } 947 break; 948 case CHIP_G4X: 949 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 950 case AGP_G4X_PGTBL_SIZE_512K: 951 gtt_size = 512; 952 break; 953 case AGP_G4X_PGTBL_SIZE_256K: 954 gtt_size = 256; 955 break; 956 case AGP_G4X_PGTBL_SIZE_128K: 957 gtt_size = 128; 958 break; 959 case AGP_G4X_PGTBL_SIZE_1M: 960 gtt_size = 1*1024; 961 break; 962 case AGP_G4X_PGTBL_SIZE_2M: 963 gtt_size = 2*1024; 964 break; 965 case AGP_G4X_PGTBL_SIZE_1_5M: 966 gtt_size = 1*1024 + 512; 967 break; 968 default: 969 aprint_error_dev(sc->as_dev, 970 "bad PGTBL size\n"); 971 error = ENXIO; 972 goto fail0; 973 } 974 break; 975 default: 976 panic("impossible chiptype %d", isc->chiptype); 977 } 978 979 /* 980 * XXX If I'm reading the datasheets right, this stolen 981 * memory detection logic is totally wrong. 982 */ 983 switch (gcc1 & AGP_I855_GCC1_GMS) { 984 case AGP_I855_GCC1_GMS_STOLEN_1M: 985 stolen = 1024; 986 break; 987 case AGP_I855_GCC1_GMS_STOLEN_4M: 988 stolen = 4 * 1024; 989 break; 990 case AGP_I855_GCC1_GMS_STOLEN_8M: 991 stolen = 8 * 1024; 992 break; 993 case AGP_I855_GCC1_GMS_STOLEN_16M: 994 stolen = 16 * 1024; 995 break; 996 case AGP_I855_GCC1_GMS_STOLEN_32M: 997 stolen = 32 * 1024; 998 break; 999 case AGP_I915_GCC1_GMS_STOLEN_48M: 1000 stolen = 48 * 1024; 1001 break; 1002 case AGP_I915_GCC1_GMS_STOLEN_64M: 1003 stolen = 64 * 1024; 1004 break; 1005 case AGP_G33_GCC1_GMS_STOLEN_128M: 1006 stolen = 128 * 1024; 1007 break; 1008 case AGP_G33_GCC1_GMS_STOLEN_256M: 1009 stolen = 256 * 1024; 1010 break; 1011 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1012 stolen = 96 * 1024; 1013 break; 1014 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1015 stolen = 160 * 1024; 1016 break; 1017 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1018 stolen = 224 * 1024; 1019 break; 1020 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1021 stolen = 352 * 1024; 1022 break; 1023 default: 1024 aprint_error_dev(sc->as_dev, 1025 "unknown memory configuration, disabling\n"); 1026 error = ENXIO; 1027 goto fail0; 1028 } 1029 1030 switch (gcc1 & AGP_I855_GCC1_GMS) { 1031 case AGP_I915_GCC1_GMS_STOLEN_48M: 1032 case AGP_I915_GCC1_GMS_STOLEN_64M: 1033 if (isc->chiptype != CHIP_I915 && 1034 isc->chiptype != CHIP_I965 && 1035 isc->chiptype != CHIP_G33 && 1036 isc->chiptype != CHIP_PINEVIEW && 1037 isc->chiptype != CHIP_G4X) 1038 stolen = 0; 1039 break; 1040 case AGP_G33_GCC1_GMS_STOLEN_128M: 1041 case AGP_G33_GCC1_GMS_STOLEN_256M: 1042 if (isc->chiptype != CHIP_I965 && 1043 isc->chiptype != CHIP_G33 && 1044 isc->chiptype != CHIP_PINEVIEW && 1045 isc->chiptype != CHIP_G4X) 1046 stolen = 0; 1047 break; 1048 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1049 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1050 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1051 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1052 if (isc->chiptype != CHIP_I965 && 1053 isc->chiptype != CHIP_G4X) 1054 stolen = 0; 1055 break; 1056 } 1057 1058 isc->gtt_size = gtt_size * 1024; 1059 1060 /* BIOS space */ 1061 /* XXX [citation needed] */ 1062 gtt_size += 4; 1063 1064 /* XXX [citation needed] for this subtraction */ 1065 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 1066 1067 if (isc->stolen > 0) { 1068 aprint_normal_dev(sc->as_dev, 1069 "detected %dk stolen memory\n", 1070 isc->stolen * 4); 1071 } 1072 1073 /* GATT address is already in there, make sure it's enabled */ 1074 isc->pgtblctl |= 1; 1075 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 1076 } 1077 1078 /* 1079 * Make sure the chipset can see everything. 1080 */ 1081 agp_flush_cache(); 1082 1083 /* 1084 * Publish what we found for kludgey drivers (I'm looking at 1085 * you, drm). 1086 */ 1087 if (agp_i810_sc == NULL) 1088 agp_i810_sc = sc; 1089 else 1090 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1091 1092 /* Success! */ 1093 return 0; 1094 1095 fail0: KASSERT(error); 1096 return error; 1097 } 1098 1099 #if 0 1100 static int 1101 agp_i810_detach(struct agp_softc *sc) 1102 { 1103 int error; 1104 struct agp_i810_softc *isc = sc->as_chipc; 1105 1106 error = agp_generic_detach(sc); 1107 if (error) 1108 return error; 1109 1110 switch (isc->chiptype) { 1111 case CHIP_I915: 1112 case CHIP_I965: 1113 case CHIP_G33: 1114 case CHIP_PINEVIEW: 1115 case CHIP_G4X: 1116 agp_i810_teardown_chipset_flush_page(sc); 1117 break; 1118 } 1119 1120 /* Clear the GATT base. */ 1121 if (sc->chiptype == CHIP_I810) { 1122 WRITE4(AGP_I810_PGTBL_CTL, 0); 1123 } else { 1124 unsigned int pgtblctl; 1125 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1126 pgtblctl &= ~1; 1127 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1128 } 1129 1130 if (sc->chiptype == CHIP_I810) { 1131 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1132 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1133 free(isc->gatt, M_AGP); 1134 } 1135 1136 return 0; 1137 } 1138 #endif 1139 1140 static u_int32_t 1141 agp_i810_get_aperture(struct agp_softc *sc) 1142 { 1143 struct agp_i810_softc *isc = sc->as_chipc; 1144 pcireg_t reg; 1145 u_int32_t size; 1146 u_int16_t miscc, gcc1; 1147 1148 size = 0; 1149 1150 switch (isc->chiptype) { 1151 case CHIP_I810: 1152 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1153 miscc = (u_int16_t)(reg >> 16); 1154 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1155 AGP_I810_MISCC_WINSIZE_32) 1156 size = 32 * 1024 * 1024; 1157 else 1158 size = 64 * 1024 * 1024; 1159 break; 1160 case CHIP_I830: 1161 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1162 gcc1 = (u_int16_t)(reg >> 16); 1163 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1164 size = 64 * 1024 * 1024; 1165 else 1166 size = 128 * 1024 * 1024; 1167 break; 1168 case CHIP_I855: 1169 size = 128 * 1024 * 1024; 1170 break; 1171 case CHIP_I915: 1172 case CHIP_G33: 1173 case CHIP_PINEVIEW: 1174 case CHIP_G4X: 1175 size = sc->as_apsize; 1176 break; 1177 case CHIP_I965: 1178 size = 512 * 1024 * 1024; 1179 break; 1180 default: 1181 aprint_error(": Unknown chipset\n"); 1182 } 1183 1184 return size; 1185 } 1186 1187 static int 1188 agp_i810_set_aperture(struct agp_softc *sc __unused, 1189 uint32_t aperture __unused) 1190 { 1191 1192 return ENOSYS; 1193 } 1194 1195 static int 1196 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1197 { 1198 struct agp_i810_softc *isc = sc->as_chipc; 1199 1200 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1201 DPRINTF(sc, "failed" 1202 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1203 (uintmax_t)offset, 1204 (unsigned)AGP_PAGE_SHIFT, 1205 (uintmax_t)isc->gtt_size/4); 1206 return EINVAL; 1207 } 1208 1209 if (isc->chiptype != CHIP_I810) { 1210 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1211 DPRINTF(sc, "trying to bind into stolen memory\n"); 1212 return EINVAL; 1213 } 1214 } 1215 1216 return agp_i810_write_gtt_entry(isc, offset, physical, 1217 AGP_I810_GTT_VALID); 1218 } 1219 1220 static int 1221 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1222 { 1223 struct agp_i810_softc *isc = sc->as_chipc; 1224 1225 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1226 return EINVAL; 1227 1228 if (isc->chiptype != CHIP_I810 ) { 1229 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1230 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1231 return EINVAL; 1232 } 1233 } 1234 1235 return agp_i810_write_gtt_entry(isc, offset, 0, 0); 1236 } 1237 1238 /* 1239 * Writing via memory mapped registers already flushes all TLBs. 1240 */ 1241 static void 1242 agp_i810_flush_tlb(struct agp_softc *sc) 1243 { 1244 } 1245 1246 static int 1247 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1248 { 1249 1250 return 0; 1251 } 1252 1253 #define AGP_I810_MEMTYPE_MAIN 0 1254 #define AGP_I810_MEMTYPE_DCACHE 1 1255 #define AGP_I810_MEMTYPE_HWCURSOR 2 1256 1257 static struct agp_memory * 1258 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1259 { 1260 struct agp_i810_softc *isc = sc->as_chipc; 1261 struct agp_memory *mem; 1262 int error; 1263 1264 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1265 1266 if (size <= 0) 1267 return NULL; 1268 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1269 return NULL; 1270 KASSERT(sc->as_allocated <= sc->as_maxmem); 1271 if (size > (sc->as_maxmem - sc->as_allocated)) 1272 return NULL; 1273 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1274 return NULL; 1275 1276 switch (type) { 1277 case AGP_I810_MEMTYPE_MAIN: 1278 break; 1279 case AGP_I810_MEMTYPE_DCACHE: 1280 if (isc->chiptype != CHIP_I810) 1281 return NULL; 1282 if (size != isc->dcache_size) 1283 return NULL; 1284 break; 1285 case AGP_I810_MEMTYPE_HWCURSOR: 1286 if ((size != AGP_PAGE_SIZE) && 1287 (size != AGP_PAGE_SIZE*4)) 1288 return NULL; 1289 break; 1290 default: 1291 return NULL; 1292 } 1293 1294 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1295 if (mem == NULL) 1296 goto fail0; 1297 mem->am_id = sc->as_nextid++; 1298 mem->am_size = size; 1299 mem->am_type = type; 1300 1301 switch (type) { 1302 case AGP_I810_MEMTYPE_MAIN: 1303 error = bus_dmamap_create(sc->as_dmat, size, 1304 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1305 &mem->am_dmamap); 1306 if (error) 1307 goto fail1; 1308 break; 1309 case AGP_I810_MEMTYPE_DCACHE: 1310 break; 1311 case AGP_I810_MEMTYPE_HWCURSOR: 1312 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1313 M_WAITOK); 1314 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1315 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1316 &mem->am_nseg); 1317 if (error) { 1318 free(mem->am_dmaseg, M_AGP); 1319 goto fail1; 1320 } 1321 (void)memset(mem->am_virtual, 0, size); 1322 break; 1323 default: 1324 panic("invalid agp memory type: %d", type); 1325 } 1326 1327 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1328 sc->as_allocated += size; 1329 1330 return mem; 1331 1332 fail1: free(mem, M_AGP); 1333 fail0: return NULL; 1334 } 1335 1336 static int 1337 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1338 { 1339 1340 if (mem->am_is_bound) 1341 return EBUSY; 1342 1343 switch (mem->am_type) { 1344 case AGP_I810_MEMTYPE_MAIN: 1345 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1346 break; 1347 case AGP_I810_MEMTYPE_DCACHE: 1348 break; 1349 case AGP_I810_MEMTYPE_HWCURSOR: 1350 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1351 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1352 free(mem->am_dmaseg, M_AGP); 1353 break; 1354 default: 1355 panic("invalid agp i810 memory type: %d", mem->am_type); 1356 } 1357 1358 sc->as_allocated -= mem->am_size; 1359 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1360 free(mem, M_AGP); 1361 1362 return 0; 1363 } 1364 1365 static int 1366 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1367 off_t offset) 1368 { 1369 struct agp_i810_softc *isc = sc->as_chipc; 1370 uint32_t pgtblctl; 1371 int error; 1372 1373 if (mem->am_is_bound) 1374 return EINVAL; 1375 1376 /* 1377 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1378 * X server for mysterious reasons which leads to crashes if we write 1379 * to the GTT through the MMIO window. 1380 * Until the issue is solved, simply restore it. 1381 */ 1382 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1383 if (pgtblctl != isc->pgtblctl) { 1384 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1385 " - fixing\n", pgtblctl); 1386 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1387 isc->pgtblctl); 1388 } 1389 1390 switch (mem->am_type) { 1391 case AGP_I810_MEMTYPE_MAIN: 1392 return agp_generic_bind_memory_bounded(sc, mem, offset, 1393 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1394 case AGP_I810_MEMTYPE_DCACHE: 1395 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1396 break; 1397 case AGP_I810_MEMTYPE_HWCURSOR: 1398 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1399 break; 1400 default: 1401 panic("invalid agp i810 memory type: %d", mem->am_type); 1402 } 1403 if (error) 1404 return error; 1405 1406 /* Success! */ 1407 mem->am_is_bound = 1; 1408 return 0; 1409 } 1410 1411 static int 1412 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1413 off_t offset) 1414 { 1415 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1416 uint32_t i, j; 1417 int error; 1418 1419 KASSERT(isc->chiptype == CHIP_I810); 1420 1421 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1422 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1423 error = agp_i810_write_gtt_entry(isc, offset + i, 1424 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE); 1425 if (error) 1426 goto fail0; 1427 } 1428 1429 /* Success! */ 1430 mem->am_offset = offset; 1431 return 0; 1432 1433 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1434 (void)agp_i810_unbind_page(sc, offset + j); 1435 return error; 1436 } 1437 1438 static int 1439 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1440 off_t offset) 1441 { 1442 const bus_addr_t pa = mem->am_physical; 1443 uint32_t i, j; 1444 int error; 1445 1446 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1447 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1448 error = agp_i810_bind_page(sc, offset + i, pa + i); 1449 if (error) 1450 goto fail0; 1451 } 1452 1453 /* Success! */ 1454 mem->am_offset = offset; 1455 return 0; 1456 1457 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1458 (void)agp_i810_unbind_page(sc, offset + j); 1459 return error; 1460 } 1461 1462 static int 1463 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1464 { 1465 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1466 u_int32_t i; 1467 1468 if (!mem->am_is_bound) 1469 return EINVAL; 1470 1471 switch (mem->am_type) { 1472 case AGP_I810_MEMTYPE_MAIN: 1473 return agp_generic_unbind_memory(sc, mem); 1474 case AGP_I810_MEMTYPE_DCACHE: 1475 KASSERT(isc->chiptype == CHIP_I810); 1476 /* FALLTHROUGH */ 1477 case AGP_I810_MEMTYPE_HWCURSOR: 1478 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1479 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1480 mem->am_offset = 0; 1481 break; 1482 default: 1483 panic("invalid agp i810 memory type: %d", mem->am_type); 1484 } 1485 1486 mem->am_is_bound = 0; 1487 return 0; 1488 } 1489 1490 void 1491 agp_i810_reset(struct agp_i810_softc *isc) 1492 { 1493 1494 /* Restore the page table control register. */ 1495 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1496 isc->pgtblctl); 1497 1498 agp_flush_cache(); 1499 } 1500 1501 static bool 1502 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1503 { 1504 struct agp_softc *sc = device_private(dv); 1505 struct agp_i810_softc *isc = sc->as_chipc; 1506 1507 agp_i810_reset(isc); 1508 1509 return true; 1510 } 1511
Indexes created Tue Jun 23 00:25:03 UTC 2026