1 /* $NetBSD: amdgpu_atombios_i2c.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_atombios_i2c.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $"); 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "atom.h" 34 #include "amdgpu_atombios.h" 35 #include "atombios_i2c.h" 36 37 #define TARGET_HW_I2C_CLOCK 50 38 39 /* these are a limitation of ProcessI2cChannelTransaction not the hw */ 40 #define ATOM_MAX_HW_I2C_WRITE 3 41 #define ATOM_MAX_HW_I2C_READ 255 42 43 static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan, 44 u8 slave_addr, u8 flags, 45 u8 *buf, u8 num) 46 { 47 struct drm_device *dev = chan->dev; 48 struct amdgpu_device *adev = dev->dev_private; 49 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args; 50 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction); 51 unsigned char *base; 52 u16 out = cpu_to_le16(0); 53 int r = 0; 54 55 memset(&args, 0, sizeof(args)); 56 57 mutex_lock(&chan->mutex); 58 59 base = (unsigned char *)adev->mode_info.atom_context->scratch; 60 61 if (flags & HW_I2C_WRITE) { 62 if (num > ATOM_MAX_HW_I2C_WRITE) { 63 DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num); 64 r = -EINVAL; 65 goto done; 66 } 67 if (buf == NULL) 68 args.ucRegIndex = 0; 69 else 70 args.ucRegIndex = buf[0]; 71 if (num) 72 num--; 73 if (num) { 74 if (buf) { 75 memcpy(&out, &buf[1], num); 76 } else { 77 DRM_ERROR("hw i2c: missing buf with num > 1\n"); 78 r = -EINVAL; 79 goto done; 80 } 81 } 82 args.lpI2CDataOut = cpu_to_le16(out); 83 } else { 84 CTASSERT(ATOM_MAX_HW_I2C_READ < 85 (uintmax_t)1 << (CHAR_BIT*sizeof(num))); 86 args.ucRegIndex = 0; 87 args.lpI2CDataOut = 0; 88 } 89 90 args.ucFlag = flags; 91 args.ucI2CSpeed = TARGET_HW_I2C_CLOCK; 92 args.ucTransBytes = num; 93 args.ucSlaveAddr = slave_addr << 1; 94 args.ucLineNumber = chan->rec.i2c_id; 95 96 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 97 98 /* error */ 99 if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) { 100 DRM_DEBUG_KMS("hw_i2c error\n"); 101 r = -EIO; 102 goto done; 103 } 104 105 if (!(flags & HW_I2C_WRITE)) 106 amdgpu_atombios_copy_swap(buf, base, num, false); 107 108 done: 109 mutex_unlock(&chan->mutex); 110 111 return r; 112 } 113 114 int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap, 115 struct i2c_msg *msgs, int num) 116 { 117 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 118 struct i2c_msg *p; 119 int i, remaining, current_count, buffer_offset, max_bytes, ret; 120 u8 flags; 121 122 /* check for bus probe */ 123 p = &msgs[0]; 124 if ((num == 1) && (p->len == 0)) { 125 ret = amdgpu_atombios_i2c_process_i2c_ch(i2c, 126 p->addr, HW_I2C_WRITE, 127 NULL, 0); 128 if (ret) 129 return ret; 130 else 131 return num; 132 } 133 134 for (i = 0; i < num; i++) { 135 p = &msgs[i]; 136 remaining = p->len; 137 buffer_offset = 0; 138 /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */ 139 if (p->flags & I2C_M_RD) { 140 max_bytes = ATOM_MAX_HW_I2C_READ; 141 flags = HW_I2C_READ; 142 } else { 143 max_bytes = ATOM_MAX_HW_I2C_WRITE; 144 flags = HW_I2C_WRITE; 145 } 146 while (remaining) { 147 if (remaining > max_bytes) 148 current_count = max_bytes; 149 else 150 current_count = remaining; 151 ret = amdgpu_atombios_i2c_process_i2c_ch(i2c, 152 p->addr, flags, 153 &p->buf[buffer_offset], current_count); 154 if (ret) 155 return ret; 156 remaining -= current_count; 157 buffer_offset += current_count; 158 } 159 } 160 161 return num; 162 } 163 164 u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap) 165 { 166 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 167 } 168 169 void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device* adev, u8 slave_addr, u8 line_number, u8 offset, u8 data) 170 { 171 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args; 172 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction); 173 174 args.ucRegIndex = offset; 175 args.lpI2CDataOut = data; 176 args.ucFlag = 1; 177 args.ucI2CSpeed = TARGET_HW_I2C_CLOCK; 178 args.ucTransBytes = 1; 179 args.ucSlaveAddr = slave_addr; 180 args.ucLineNumber = line_number; 181 182 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 183 } 184
Indexes created Sat Sep 20 22:09:52 GMT 2025