1 /* $NetBSD: amdgpu_connectors.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_connectors.c,v 1.3 2021/12/18 23:44:58 riastradh Exp $"); 31 32 #include <drm/drm_edid.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu.h" 37 #include "atom.h" 38 #include "atombios_encoders.h" 39 #include "atombios_dp.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_i2c.h" 42 #include "amdgpu_display.h" 43 44 #include <linux/pm_runtime.h> 45 46 void amdgpu_connector_hotplug(struct drm_connector *connector) 47 { 48 struct drm_device *dev = connector->dev; 49 struct amdgpu_device *adev = dev->dev_private; 50 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 51 52 /* bail if the connector does not have hpd pin, e.g., 53 * VGA, TV, etc. 54 */ 55 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 56 return; 57 58 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 59 60 /* if the connector is already off, don't turn it back on */ 61 if (connector->dpms != DRM_MODE_DPMS_ON) 62 return; 63 64 /* just deal with DP (not eDP) here. */ 65 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 66 struct amdgpu_connector_atom_dig *dig_connector = 67 amdgpu_connector->con_priv; 68 69 /* if existing sink type was not DP no need to retrain */ 70 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 71 return; 72 73 /* first get sink type as it may be reset after (un)plug */ 74 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 75 /* don't do anything if sink is not display port, i.e., 76 * passive dp->(dvi|hdmi) adaptor 77 */ 78 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 79 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 80 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 81 /* Don't start link training before we have the DPCD */ 82 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 83 return; 84 85 /* Turn the connector off and back on immediately, which 86 * will trigger link training 87 */ 88 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 89 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 90 } 91 } 92 } 93 94 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 95 { 96 struct drm_crtc *crtc = encoder->crtc; 97 98 if (crtc && crtc->enabled) { 99 drm_crtc_helper_set_mode(crtc, &crtc->mode, 100 crtc->x, crtc->y, crtc->primary->fb); 101 } 102 } 103 104 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 105 { 106 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 107 struct amdgpu_connector_atom_dig *dig_connector; 108 int bpc = 8; 109 unsigned mode_clock, max_tmds_clock; 110 111 switch (connector->connector_type) { 112 case DRM_MODE_CONNECTOR_DVII: 113 case DRM_MODE_CONNECTOR_HDMIB: 114 if (amdgpu_connector->use_digital) { 115 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 116 if (connector->display_info.bpc) 117 bpc = connector->display_info.bpc; 118 } 119 } 120 break; 121 case DRM_MODE_CONNECTOR_DVID: 122 case DRM_MODE_CONNECTOR_HDMIA: 123 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 124 if (connector->display_info.bpc) 125 bpc = connector->display_info.bpc; 126 } 127 break; 128 case DRM_MODE_CONNECTOR_DisplayPort: 129 dig_connector = amdgpu_connector->con_priv; 130 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 131 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 132 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 133 if (connector->display_info.bpc) 134 bpc = connector->display_info.bpc; 135 } 136 break; 137 case DRM_MODE_CONNECTOR_eDP: 138 case DRM_MODE_CONNECTOR_LVDS: 139 if (connector->display_info.bpc) 140 bpc = connector->display_info.bpc; 141 else { 142 const struct drm_connector_helper_funcs *connector_funcs = 143 connector->helper_private; 144 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 145 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 146 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 147 148 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 149 bpc = 6; 150 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 151 bpc = 8; 152 } 153 break; 154 } 155 156 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 157 /* 158 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 159 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 160 * 12 bpc is always supported on hdmi deep color sinks, as this is 161 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 162 */ 163 if (bpc > 12) { 164 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 165 connector->name, bpc); 166 bpc = 12; 167 } 168 169 /* Any defined maximum tmds clock limit we must not exceed? */ 170 if (connector->display_info.max_tmds_clock > 0) { 171 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 172 mode_clock = amdgpu_connector->pixelclock_for_modeset; 173 174 /* Maximum allowable input clock in kHz */ 175 max_tmds_clock = connector->display_info.max_tmds_clock; 176 177 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 178 connector->name, mode_clock, max_tmds_clock); 179 180 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 181 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 182 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 183 (mode_clock * 5/4 <= max_tmds_clock)) 184 bpc = 10; 185 else 186 bpc = 8; 187 188 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 189 connector->name, bpc); 190 } 191 192 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 193 bpc = 8; 194 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 195 connector->name, bpc); 196 } 197 } else if (bpc > 8) { 198 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 199 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 200 connector->name); 201 bpc = 8; 202 } 203 } 204 205 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 206 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 207 connector->name); 208 bpc = 8; 209 } 210 211 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 212 connector->name, connector->display_info.bpc, bpc); 213 214 return bpc; 215 } 216 217 static void 218 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 219 enum drm_connector_status status) 220 { 221 struct drm_encoder *best_encoder; 222 struct drm_encoder *encoder; 223 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 224 bool connected; 225 226 best_encoder = connector_funcs->best_encoder(connector); 227 228 drm_connector_for_each_possible_encoder(connector, encoder) { 229 if ((encoder == best_encoder) && (status == connector_status_connected)) 230 connected = true; 231 else 232 connected = false; 233 234 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 235 } 236 } 237 238 static struct drm_encoder * 239 amdgpu_connector_find_encoder(struct drm_connector *connector, 240 int encoder_type) 241 { 242 struct drm_encoder *encoder; 243 244 drm_connector_for_each_possible_encoder(connector, encoder) { 245 if (encoder->encoder_type == encoder_type) 246 return encoder; 247 } 248 249 return NULL; 250 } 251 252 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 253 { 254 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 255 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 256 257 if (amdgpu_connector->edid) { 258 return amdgpu_connector->edid; 259 } else if (edid_blob) { 260 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 261 if (edid) 262 amdgpu_connector->edid = edid; 263 } 264 return amdgpu_connector->edid; 265 } 266 267 static struct edid * 268 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 269 { 270 struct edid *edid; 271 272 if (adev->mode_info.bios_hardcoded_edid) { 273 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 274 if (edid) { 275 memcpy((unsigned char *)edid, 276 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 277 adev->mode_info.bios_hardcoded_edid_size); 278 return edid; 279 } 280 } 281 return NULL; 282 } 283 284 static void amdgpu_connector_get_edid(struct drm_connector *connector) 285 { 286 struct drm_device *dev = connector->dev; 287 struct amdgpu_device *adev = dev->dev_private; 288 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 289 290 if (amdgpu_connector->edid) 291 return; 292 293 /* on hw with routers, select right port */ 294 if (amdgpu_connector->router.ddc_valid) 295 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 296 297 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 298 ENCODER_OBJECT_ID_NONE) && 299 amdgpu_connector->ddc_bus->has_aux) { 300 amdgpu_connector->edid = drm_get_edid(connector, 301 &amdgpu_connector->ddc_bus->aux.ddc); 302 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 303 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 304 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 305 306 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 307 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 308 amdgpu_connector->ddc_bus->has_aux) 309 amdgpu_connector->edid = drm_get_edid(connector, 310 &amdgpu_connector->ddc_bus->aux.ddc); 311 else if (amdgpu_connector->ddc_bus) 312 amdgpu_connector->edid = drm_get_edid(connector, 313 &amdgpu_connector->ddc_bus->adapter); 314 } else if (amdgpu_connector->ddc_bus) { 315 amdgpu_connector->edid = drm_get_edid(connector, 316 &amdgpu_connector->ddc_bus->adapter); 317 } 318 319 if (!amdgpu_connector->edid) { 320 /* some laptops provide a hardcoded edid in rom for LCDs */ 321 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 322 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 323 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 324 } 325 } 326 327 static void amdgpu_connector_free_edid(struct drm_connector *connector) 328 { 329 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 330 331 kfree(amdgpu_connector->edid); 332 amdgpu_connector->edid = NULL; 333 } 334 335 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 336 { 337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 338 int ret; 339 340 if (amdgpu_connector->edid) { 341 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 342 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 343 return ret; 344 } 345 drm_connector_update_edid_property(connector, NULL); 346 return 0; 347 } 348 349 static struct drm_encoder * 350 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 351 { 352 struct drm_encoder *encoder; 353 354 /* pick the first one */ 355 drm_connector_for_each_possible_encoder(connector, encoder) 356 return encoder; 357 358 return NULL; 359 } 360 361 static void amdgpu_get_native_mode(struct drm_connector *connector) 362 { 363 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 364 struct amdgpu_encoder *amdgpu_encoder; 365 366 if (encoder == NULL) 367 return; 368 369 amdgpu_encoder = to_amdgpu_encoder(encoder); 370 371 if (!list_empty(&connector->probed_modes)) { 372 struct drm_display_mode *preferred_mode = 373 list_first_entry(&connector->probed_modes, 374 struct drm_display_mode, head); 375 376 amdgpu_encoder->native_mode = *preferred_mode; 377 } else { 378 amdgpu_encoder->native_mode.clock = 0; 379 } 380 } 381 382 static struct drm_display_mode * 383 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 384 { 385 struct drm_device *dev = encoder->dev; 386 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 387 struct drm_display_mode *mode = NULL; 388 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 389 390 if (native_mode->hdisplay != 0 && 391 native_mode->vdisplay != 0 && 392 native_mode->clock != 0) { 393 mode = drm_mode_duplicate(dev, native_mode); 394 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 395 drm_mode_set_name(mode); 396 397 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 398 } else if (native_mode->hdisplay != 0 && 399 native_mode->vdisplay != 0) { 400 /* mac laptops without an edid */ 401 /* Note that this is not necessarily the exact panel mode, 402 * but an approximation based on the cvt formula. For these 403 * systems we should ideally read the mode info out of the 404 * registers or add a mode table, but this works and is much 405 * simpler. 406 */ 407 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 408 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 409 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 410 } 411 return mode; 412 } 413 414 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 415 struct drm_connector *connector) 416 { 417 struct drm_device *dev = encoder->dev; 418 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 419 struct drm_display_mode *mode = NULL; 420 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 421 int i; 422 static const struct mode_size { 423 int w; 424 int h; 425 } common_modes[17] = { 426 { 640, 480}, 427 { 720, 480}, 428 { 800, 600}, 429 { 848, 480}, 430 {1024, 768}, 431 {1152, 768}, 432 {1280, 720}, 433 {1280, 800}, 434 {1280, 854}, 435 {1280, 960}, 436 {1280, 1024}, 437 {1440, 900}, 438 {1400, 1050}, 439 {1680, 1050}, 440 {1600, 1200}, 441 {1920, 1080}, 442 {1920, 1200} 443 }; 444 445 for (i = 0; i < 17; i++) { 446 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 447 if (common_modes[i].w > 1024 || 448 common_modes[i].h > 768) 449 continue; 450 } 451 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 452 if (common_modes[i].w > native_mode->hdisplay || 453 common_modes[i].h > native_mode->vdisplay || 454 (common_modes[i].w == native_mode->hdisplay && 455 common_modes[i].h == native_mode->vdisplay)) 456 continue; 457 } 458 if (common_modes[i].w < 320 || common_modes[i].h < 200) 459 continue; 460 461 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 462 drm_mode_probed_add(connector, mode); 463 } 464 } 465 466 static int amdgpu_connector_set_property(struct drm_connector *connector, 467 struct drm_property *property, 468 uint64_t val) 469 { 470 struct drm_device *dev = connector->dev; 471 struct amdgpu_device *adev = dev->dev_private; 472 struct drm_encoder *encoder; 473 struct amdgpu_encoder *amdgpu_encoder; 474 475 if (property == adev->mode_info.coherent_mode_property) { 476 struct amdgpu_encoder_atom_dig *dig; 477 bool new_coherent_mode; 478 479 /* need to find digital encoder on connector */ 480 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 481 if (!encoder) 482 return 0; 483 484 amdgpu_encoder = to_amdgpu_encoder(encoder); 485 486 if (!amdgpu_encoder->enc_priv) 487 return 0; 488 489 dig = amdgpu_encoder->enc_priv; 490 new_coherent_mode = val ? true : false; 491 if (dig->coherent_mode != new_coherent_mode) { 492 dig->coherent_mode = new_coherent_mode; 493 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 494 } 495 } 496 497 if (property == adev->mode_info.audio_property) { 498 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 499 /* need to find digital encoder on connector */ 500 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 501 if (!encoder) 502 return 0; 503 504 amdgpu_encoder = to_amdgpu_encoder(encoder); 505 506 if (amdgpu_connector->audio != val) { 507 amdgpu_connector->audio = val; 508 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 509 } 510 } 511 512 if (property == adev->mode_info.dither_property) { 513 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 514 /* need to find digital encoder on connector */ 515 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 516 if (!encoder) 517 return 0; 518 519 amdgpu_encoder = to_amdgpu_encoder(encoder); 520 521 if (amdgpu_connector->dither != val) { 522 amdgpu_connector->dither = val; 523 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 524 } 525 } 526 527 if (property == adev->mode_info.underscan_property) { 528 /* need to find digital encoder on connector */ 529 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 530 if (!encoder) 531 return 0; 532 533 amdgpu_encoder = to_amdgpu_encoder(encoder); 534 535 if (amdgpu_encoder->underscan_type != val) { 536 amdgpu_encoder->underscan_type = val; 537 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 538 } 539 } 540 541 if (property == adev->mode_info.underscan_hborder_property) { 542 /* need to find digital encoder on connector */ 543 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 544 if (!encoder) 545 return 0; 546 547 amdgpu_encoder = to_amdgpu_encoder(encoder); 548 549 if (amdgpu_encoder->underscan_hborder != val) { 550 amdgpu_encoder->underscan_hborder = val; 551 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 552 } 553 } 554 555 if (property == adev->mode_info.underscan_vborder_property) { 556 /* need to find digital encoder on connector */ 557 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 558 if (!encoder) 559 return 0; 560 561 amdgpu_encoder = to_amdgpu_encoder(encoder); 562 563 if (amdgpu_encoder->underscan_vborder != val) { 564 amdgpu_encoder->underscan_vborder = val; 565 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 566 } 567 } 568 569 if (property == adev->mode_info.load_detect_property) { 570 struct amdgpu_connector *amdgpu_connector = 571 to_amdgpu_connector(connector); 572 573 if (val == 0) 574 amdgpu_connector->dac_load_detect = false; 575 else 576 amdgpu_connector->dac_load_detect = true; 577 } 578 579 if (property == dev->mode_config.scaling_mode_property) { 580 enum amdgpu_rmx_type rmx_type; 581 582 if (connector->encoder) { 583 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 584 } else { 585 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 586 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 587 } 588 589 switch (val) { 590 default: 591 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 592 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 593 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 594 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 595 } 596 if (amdgpu_encoder->rmx_type == rmx_type) 597 return 0; 598 599 if ((rmx_type != DRM_MODE_SCALE_NONE) && 600 (amdgpu_encoder->native_mode.clock == 0)) 601 return 0; 602 603 amdgpu_encoder->rmx_type = rmx_type; 604 605 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 606 } 607 608 return 0; 609 } 610 611 static void 612 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 613 struct drm_connector *connector) 614 { 615 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 616 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 617 struct drm_display_mode *t, *mode; 618 619 /* If the EDID preferred mode doesn't match the native mode, use it */ 620 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 621 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 622 if (mode->hdisplay != native_mode->hdisplay || 623 mode->vdisplay != native_mode->vdisplay) 624 memcpy(native_mode, mode, sizeof(*mode)); 625 } 626 } 627 628 /* Try to get native mode details from EDID if necessary */ 629 if (!native_mode->clock) { 630 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 631 if (mode->hdisplay == native_mode->hdisplay && 632 mode->vdisplay == native_mode->vdisplay) { 633 *native_mode = *mode; 634 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 635 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 636 break; 637 } 638 } 639 } 640 641 if (!native_mode->clock) { 642 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 643 amdgpu_encoder->rmx_type = RMX_OFF; 644 } 645 } 646 647 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 648 { 649 struct drm_encoder *encoder; 650 int ret = 0; 651 struct drm_display_mode *mode; 652 653 amdgpu_connector_get_edid(connector); 654 ret = amdgpu_connector_ddc_get_modes(connector); 655 if (ret > 0) { 656 encoder = amdgpu_connector_best_single_encoder(connector); 657 if (encoder) { 658 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 659 /* add scaled modes */ 660 amdgpu_connector_add_common_modes(encoder, connector); 661 } 662 return ret; 663 } 664 665 encoder = amdgpu_connector_best_single_encoder(connector); 666 if (!encoder) 667 return 0; 668 669 /* we have no EDID modes */ 670 mode = amdgpu_connector_lcd_native_mode(encoder); 671 if (mode) { 672 ret = 1; 673 drm_mode_probed_add(connector, mode); 674 /* add the width/height from vbios tables if available */ 675 connector->display_info.width_mm = mode->width_mm; 676 connector->display_info.height_mm = mode->height_mm; 677 /* add scaled modes */ 678 amdgpu_connector_add_common_modes(encoder, connector); 679 } 680 681 return ret; 682 } 683 684 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 685 struct drm_display_mode *mode) 686 { 687 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 688 689 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 690 return MODE_PANEL; 691 692 if (encoder) { 693 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 694 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 695 696 /* AVIVO hardware supports downscaling modes larger than the panel 697 * to the panel size, but I'm not sure this is desirable. 698 */ 699 if ((mode->hdisplay > native_mode->hdisplay) || 700 (mode->vdisplay > native_mode->vdisplay)) 701 return MODE_PANEL; 702 703 /* if scaling is disabled, block non-native modes */ 704 if (amdgpu_encoder->rmx_type == RMX_OFF) { 705 if ((mode->hdisplay != native_mode->hdisplay) || 706 (mode->vdisplay != native_mode->vdisplay)) 707 return MODE_PANEL; 708 } 709 } 710 711 return MODE_OK; 712 } 713 714 static enum drm_connector_status 715 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 716 { 717 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 718 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 719 enum drm_connector_status ret = connector_status_disconnected; 720 int r; 721 722 if (!drm_kms_helper_is_poll_worker()) { 723 r = pm_runtime_get_sync(connector->dev->dev); 724 if (r < 0) 725 return connector_status_disconnected; 726 } 727 728 if (encoder) { 729 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 730 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 731 732 /* check if panel is valid */ 733 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 734 ret = connector_status_connected; 735 736 } 737 738 /* check for edid as well */ 739 amdgpu_connector_get_edid(connector); 740 if (amdgpu_connector->edid) 741 ret = connector_status_connected; 742 /* check acpi lid status ??? */ 743 744 amdgpu_connector_update_scratch_regs(connector, ret); 745 746 if (!drm_kms_helper_is_poll_worker()) { 747 pm_runtime_mark_last_busy(connector->dev->dev); 748 pm_runtime_put_autosuspend(connector->dev->dev); 749 } 750 751 return ret; 752 } 753 754 static void amdgpu_connector_unregister(struct drm_connector *connector) 755 { 756 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 757 758 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 759 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 760 amdgpu_connector->ddc_bus->has_aux = false; 761 } 762 } 763 764 static void amdgpu_connector_destroy(struct drm_connector *connector) 765 { 766 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 767 768 amdgpu_connector_free_edid(connector); 769 kfree(amdgpu_connector->con_priv); 770 drm_connector_unregister(connector); 771 drm_connector_cleanup(connector); 772 kfree(connector); 773 } 774 775 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 776 struct drm_property *property, 777 uint64_t value) 778 { 779 struct drm_device *dev = connector->dev; 780 struct amdgpu_encoder *amdgpu_encoder; 781 enum amdgpu_rmx_type rmx_type; 782 783 DRM_DEBUG_KMS("\n"); 784 if (property != dev->mode_config.scaling_mode_property) 785 return 0; 786 787 if (connector->encoder) 788 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 789 else { 790 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 791 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 792 } 793 794 switch (value) { 795 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 796 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 797 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 798 default: 799 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 800 } 801 if (amdgpu_encoder->rmx_type == rmx_type) 802 return 0; 803 804 amdgpu_encoder->rmx_type = rmx_type; 805 806 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 807 return 0; 808 } 809 810 811 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 812 .get_modes = amdgpu_connector_lvds_get_modes, 813 .mode_valid = amdgpu_connector_lvds_mode_valid, 814 .best_encoder = amdgpu_connector_best_single_encoder, 815 }; 816 817 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 818 .dpms = drm_helper_connector_dpms, 819 .detect = amdgpu_connector_lvds_detect, 820 .fill_modes = drm_helper_probe_single_connector_modes, 821 .early_unregister = amdgpu_connector_unregister, 822 .destroy = amdgpu_connector_destroy, 823 .set_property = amdgpu_connector_set_lcd_property, 824 }; 825 826 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 827 { 828 int ret; 829 830 amdgpu_connector_get_edid(connector); 831 ret = amdgpu_connector_ddc_get_modes(connector); 832 833 return ret; 834 } 835 836 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 837 struct drm_display_mode *mode) 838 { 839 struct drm_device *dev = connector->dev; 840 struct amdgpu_device *adev = dev->dev_private; 841 842 /* XXX check mode bandwidth */ 843 844 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 845 return MODE_CLOCK_HIGH; 846 847 return MODE_OK; 848 } 849 850 static enum drm_connector_status 851 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 852 { 853 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 854 struct drm_encoder *encoder; 855 const struct drm_encoder_helper_funcs *encoder_funcs; 856 bool dret = false; 857 enum drm_connector_status ret = connector_status_disconnected; 858 int r; 859 860 if (!drm_kms_helper_is_poll_worker()) { 861 r = pm_runtime_get_sync(connector->dev->dev); 862 if (r < 0) 863 return connector_status_disconnected; 864 } 865 866 encoder = amdgpu_connector_best_single_encoder(connector); 867 if (!encoder) 868 ret = connector_status_disconnected; 869 870 if (amdgpu_connector->ddc_bus) 871 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 872 if (dret) { 873 amdgpu_connector->detected_by_load = false; 874 amdgpu_connector_free_edid(connector); 875 amdgpu_connector_get_edid(connector); 876 877 if (!amdgpu_connector->edid) { 878 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 879 connector->name); 880 ret = connector_status_connected; 881 } else { 882 amdgpu_connector->use_digital = 883 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 884 885 /* some oems have boards with separate digital and analog connectors 886 * with a shared ddc line (often vga + hdmi) 887 */ 888 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 889 amdgpu_connector_free_edid(connector); 890 ret = connector_status_disconnected; 891 } else { 892 ret = connector_status_connected; 893 } 894 } 895 } else { 896 897 /* if we aren't forcing don't do destructive polling */ 898 if (!force) { 899 /* only return the previous status if we last 900 * detected a monitor via load. 901 */ 902 if (amdgpu_connector->detected_by_load) 903 ret = connector->status; 904 goto out; 905 } 906 907 if (amdgpu_connector->dac_load_detect && encoder) { 908 encoder_funcs = encoder->helper_private; 909 ret = encoder_funcs->detect(encoder, connector); 910 if (ret != connector_status_disconnected) 911 amdgpu_connector->detected_by_load = true; 912 } 913 } 914 915 amdgpu_connector_update_scratch_regs(connector, ret); 916 917 out: 918 if (!drm_kms_helper_is_poll_worker()) { 919 pm_runtime_mark_last_busy(connector->dev->dev); 920 pm_runtime_put_autosuspend(connector->dev->dev); 921 } 922 923 return ret; 924 } 925 926 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 927 .get_modes = amdgpu_connector_vga_get_modes, 928 .mode_valid = amdgpu_connector_vga_mode_valid, 929 .best_encoder = amdgpu_connector_best_single_encoder, 930 }; 931 932 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 933 .dpms = drm_helper_connector_dpms, 934 .detect = amdgpu_connector_vga_detect, 935 .fill_modes = drm_helper_probe_single_connector_modes, 936 .early_unregister = amdgpu_connector_unregister, 937 .destroy = amdgpu_connector_destroy, 938 .set_property = amdgpu_connector_set_property, 939 }; 940 941 static bool 942 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 943 { 944 struct drm_device *dev = connector->dev; 945 struct amdgpu_device *adev = dev->dev_private; 946 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 947 enum drm_connector_status status; 948 949 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 950 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 951 status = connector_status_connected; 952 else 953 status = connector_status_disconnected; 954 if (connector->status == status) 955 return true; 956 } 957 958 return false; 959 } 960 961 /* 962 * DVI is complicated 963 * Do a DDC probe, if DDC probe passes, get the full EDID so 964 * we can do analog/digital monitor detection at this point. 965 * If the monitor is an analog monitor or we got no DDC, 966 * we need to find the DAC encoder object for this connector. 967 * If we got no DDC, we do load detection on the DAC encoder object. 968 * If we got analog DDC or load detection passes on the DAC encoder 969 * we have to check if this analog encoder is shared with anyone else (TV) 970 * if its shared we have to set the other connector to disconnected. 971 */ 972 static enum drm_connector_status 973 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 974 { 975 struct drm_device *dev = connector->dev; 976 struct amdgpu_device *adev = dev->dev_private; 977 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 978 const struct drm_encoder_helper_funcs *encoder_funcs; 979 int r; 980 enum drm_connector_status ret = connector_status_disconnected; 981 bool dret = false, broken_edid = false; 982 983 if (!drm_kms_helper_is_poll_worker()) { 984 r = pm_runtime_get_sync(connector->dev->dev); 985 if (r < 0) 986 return connector_status_disconnected; 987 } 988 989 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 990 ret = connector->status; 991 goto exit; 992 } 993 994 if (amdgpu_connector->ddc_bus) 995 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 996 if (dret) { 997 amdgpu_connector->detected_by_load = false; 998 amdgpu_connector_free_edid(connector); 999 amdgpu_connector_get_edid(connector); 1000 1001 if (!amdgpu_connector->edid) { 1002 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1003 connector->name); 1004 ret = connector_status_connected; 1005 broken_edid = true; /* defer use_digital to later */ 1006 } else { 1007 amdgpu_connector->use_digital = 1008 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1009 1010 /* some oems have boards with separate digital and analog connectors 1011 * with a shared ddc line (often vga + hdmi) 1012 */ 1013 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1014 amdgpu_connector_free_edid(connector); 1015 ret = connector_status_disconnected; 1016 } else { 1017 ret = connector_status_connected; 1018 } 1019 1020 /* This gets complicated. We have boards with VGA + HDMI with a 1021 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1022 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1023 * you don't really know what's connected to which port as both are digital. 1024 */ 1025 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1026 struct drm_connector *list_connector; 1027 struct drm_connector_list_iter iter; 1028 struct amdgpu_connector *list_amdgpu_connector; 1029 1030 drm_connector_list_iter_begin(dev, &iter); 1031 drm_for_each_connector_iter(list_connector, 1032 &iter) { 1033 if (connector == list_connector) 1034 continue; 1035 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1036 if (list_amdgpu_connector->shared_ddc && 1037 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1038 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1039 /* cases where both connectors are digital */ 1040 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1041 /* hpd is our only option in this case */ 1042 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1043 amdgpu_connector_free_edid(connector); 1044 ret = connector_status_disconnected; 1045 } 1046 } 1047 } 1048 } 1049 drm_connector_list_iter_end(&iter); 1050 } 1051 } 1052 } 1053 1054 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1055 goto out; 1056 1057 /* DVI-D and HDMI-A are digital only */ 1058 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1059 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1060 goto out; 1061 1062 /* if we aren't forcing don't do destructive polling */ 1063 if (!force) { 1064 /* only return the previous status if we last 1065 * detected a monitor via load. 1066 */ 1067 if (amdgpu_connector->detected_by_load) 1068 ret = connector->status; 1069 goto out; 1070 } 1071 1072 /* find analog encoder */ 1073 if (amdgpu_connector->dac_load_detect) { 1074 struct drm_encoder *encoder; 1075 1076 drm_connector_for_each_possible_encoder(connector, encoder) { 1077 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1078 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1079 continue; 1080 1081 encoder_funcs = encoder->helper_private; 1082 if (encoder_funcs->detect) { 1083 if (!broken_edid) { 1084 if (ret != connector_status_connected) { 1085 /* deal with analog monitors without DDC */ 1086 ret = encoder_funcs->detect(encoder, connector); 1087 if (ret == connector_status_connected) { 1088 amdgpu_connector->use_digital = false; 1089 } 1090 if (ret != connector_status_disconnected) 1091 amdgpu_connector->detected_by_load = true; 1092 } 1093 } else { 1094 enum drm_connector_status lret; 1095 /* assume digital unless load detected otherwise */ 1096 amdgpu_connector->use_digital = true; 1097 lret = encoder_funcs->detect(encoder, connector); 1098 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1099 if (lret == connector_status_connected) 1100 amdgpu_connector->use_digital = false; 1101 } 1102 break; 1103 } 1104 } 1105 } 1106 1107 out: 1108 /* updated in get modes as well since we need to know if it's analog or digital */ 1109 amdgpu_connector_update_scratch_regs(connector, ret); 1110 1111 exit: 1112 if (!drm_kms_helper_is_poll_worker()) { 1113 pm_runtime_mark_last_busy(connector->dev->dev); 1114 pm_runtime_put_autosuspend(connector->dev->dev); 1115 } 1116 1117 return ret; 1118 } 1119 1120 /* okay need to be smart in here about which encoder to pick */ 1121 static struct drm_encoder * 1122 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1123 { 1124 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1125 struct drm_encoder *encoder; 1126 1127 drm_connector_for_each_possible_encoder(connector, encoder) { 1128 if (amdgpu_connector->use_digital == true) { 1129 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1130 return encoder; 1131 } else { 1132 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1133 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1134 return encoder; 1135 } 1136 } 1137 1138 /* see if we have a default encoder TODO */ 1139 1140 /* then check use digitial */ 1141 /* pick the first one */ 1142 drm_connector_for_each_possible_encoder(connector, encoder) 1143 return encoder; 1144 1145 return NULL; 1146 } 1147 1148 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1149 { 1150 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1151 if (connector->force == DRM_FORCE_ON) 1152 amdgpu_connector->use_digital = false; 1153 if (connector->force == DRM_FORCE_ON_DIGITAL) 1154 amdgpu_connector->use_digital = true; 1155 } 1156 1157 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1158 struct drm_display_mode *mode) 1159 { 1160 struct drm_device *dev = connector->dev; 1161 struct amdgpu_device *adev = dev->dev_private; 1162 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1163 1164 /* XXX check mode bandwidth */ 1165 1166 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1167 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1168 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1169 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1170 return MODE_OK; 1171 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1172 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1173 if (mode->clock > 340000) 1174 return MODE_CLOCK_HIGH; 1175 else 1176 return MODE_OK; 1177 } else { 1178 return MODE_CLOCK_HIGH; 1179 } 1180 } 1181 1182 /* check against the max pixel clock */ 1183 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1184 return MODE_CLOCK_HIGH; 1185 1186 return MODE_OK; 1187 } 1188 1189 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1190 .get_modes = amdgpu_connector_vga_get_modes, 1191 .mode_valid = amdgpu_connector_dvi_mode_valid, 1192 .best_encoder = amdgpu_connector_dvi_encoder, 1193 }; 1194 1195 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1196 .dpms = drm_helper_connector_dpms, 1197 .detect = amdgpu_connector_dvi_detect, 1198 .fill_modes = drm_helper_probe_single_connector_modes, 1199 .set_property = amdgpu_connector_set_property, 1200 .early_unregister = amdgpu_connector_unregister, 1201 .destroy = amdgpu_connector_destroy, 1202 .force = amdgpu_connector_dvi_force, 1203 }; 1204 1205 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1206 { 1207 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1208 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1209 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1210 int ret; 1211 1212 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1213 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1214 struct drm_display_mode *mode; 1215 1216 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1217 if (!amdgpu_dig_connector->edp_on) 1218 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1219 ATOM_TRANSMITTER_ACTION_POWER_ON); 1220 amdgpu_connector_get_edid(connector); 1221 ret = amdgpu_connector_ddc_get_modes(connector); 1222 if (!amdgpu_dig_connector->edp_on) 1223 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1224 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1225 } else { 1226 /* need to setup ddc on the bridge */ 1227 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1228 ENCODER_OBJECT_ID_NONE) { 1229 if (encoder) 1230 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1231 } 1232 amdgpu_connector_get_edid(connector); 1233 ret = amdgpu_connector_ddc_get_modes(connector); 1234 } 1235 1236 if (ret > 0) { 1237 if (encoder) { 1238 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1239 /* add scaled modes */ 1240 amdgpu_connector_add_common_modes(encoder, connector); 1241 } 1242 return ret; 1243 } 1244 1245 if (!encoder) 1246 return 0; 1247 1248 /* we have no EDID modes */ 1249 mode = amdgpu_connector_lcd_native_mode(encoder); 1250 if (mode) { 1251 ret = 1; 1252 drm_mode_probed_add(connector, mode); 1253 /* add the width/height from vbios tables if available */ 1254 connector->display_info.width_mm = mode->width_mm; 1255 connector->display_info.height_mm = mode->height_mm; 1256 /* add scaled modes */ 1257 amdgpu_connector_add_common_modes(encoder, connector); 1258 } 1259 } else { 1260 /* need to setup ddc on the bridge */ 1261 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1262 ENCODER_OBJECT_ID_NONE) { 1263 if (encoder) 1264 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1265 } 1266 amdgpu_connector_get_edid(connector); 1267 ret = amdgpu_connector_ddc_get_modes(connector); 1268 1269 amdgpu_get_native_mode(connector); 1270 } 1271 1272 return ret; 1273 } 1274 1275 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1276 { 1277 struct drm_encoder *encoder; 1278 struct amdgpu_encoder *amdgpu_encoder; 1279 1280 drm_connector_for_each_possible_encoder(connector, encoder) { 1281 amdgpu_encoder = to_amdgpu_encoder(encoder); 1282 1283 switch (amdgpu_encoder->encoder_id) { 1284 case ENCODER_OBJECT_ID_TRAVIS: 1285 case ENCODER_OBJECT_ID_NUTMEG: 1286 return amdgpu_encoder->encoder_id; 1287 default: 1288 break; 1289 } 1290 } 1291 1292 return ENCODER_OBJECT_ID_NONE; 1293 } 1294 1295 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1296 { 1297 struct drm_encoder *encoder; 1298 struct amdgpu_encoder *amdgpu_encoder; 1299 bool found = false; 1300 1301 drm_connector_for_each_possible_encoder(connector, encoder) { 1302 amdgpu_encoder = to_amdgpu_encoder(encoder); 1303 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1304 found = true; 1305 } 1306 1307 return found; 1308 } 1309 1310 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1311 { 1312 struct drm_device *dev = connector->dev; 1313 struct amdgpu_device *adev = dev->dev_private; 1314 1315 if ((adev->clock.default_dispclk >= 53900) && 1316 amdgpu_connector_encoder_is_hbr2(connector)) { 1317 return true; 1318 } 1319 1320 return false; 1321 } 1322 1323 static enum drm_connector_status 1324 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1325 { 1326 struct drm_device *dev = connector->dev; 1327 struct amdgpu_device *adev = dev->dev_private; 1328 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1329 enum drm_connector_status ret = connector_status_disconnected; 1330 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1331 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1332 int r; 1333 1334 if (!drm_kms_helper_is_poll_worker()) { 1335 r = pm_runtime_get_sync(connector->dev->dev); 1336 if (r < 0) 1337 return connector_status_disconnected; 1338 } 1339 1340 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1341 ret = connector->status; 1342 goto out; 1343 } 1344 1345 amdgpu_connector_free_edid(connector); 1346 1347 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1348 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1349 if (encoder) { 1350 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1351 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1352 1353 /* check if panel is valid */ 1354 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1355 ret = connector_status_connected; 1356 } 1357 /* eDP is always DP */ 1358 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1359 if (!amdgpu_dig_connector->edp_on) 1360 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1361 ATOM_TRANSMITTER_ACTION_POWER_ON); 1362 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1363 ret = connector_status_connected; 1364 if (!amdgpu_dig_connector->edp_on) 1365 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1366 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1367 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1368 ENCODER_OBJECT_ID_NONE) { 1369 /* DP bridges are always DP */ 1370 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1371 /* get the DPCD from the bridge */ 1372 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1373 1374 if (encoder) { 1375 /* setup ddc on the bridge */ 1376 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1377 /* bridge chips are always aux */ 1378 /* try DDC */ 1379 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1380 ret = connector_status_connected; 1381 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1382 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1383 ret = encoder_funcs->detect(encoder, connector); 1384 } 1385 } 1386 } else { 1387 amdgpu_dig_connector->dp_sink_type = 1388 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1389 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1390 ret = connector_status_connected; 1391 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1392 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1393 } else { 1394 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1395 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1396 ret = connector_status_connected; 1397 } else { 1398 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1399 if (amdgpu_display_ddc_probe(amdgpu_connector, 1400 false)) 1401 ret = connector_status_connected; 1402 } 1403 } 1404 } 1405 1406 amdgpu_connector_update_scratch_regs(connector, ret); 1407 out: 1408 if (!drm_kms_helper_is_poll_worker()) { 1409 pm_runtime_mark_last_busy(connector->dev->dev); 1410 pm_runtime_put_autosuspend(connector->dev->dev); 1411 } 1412 1413 return ret; 1414 } 1415 1416 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1417 struct drm_display_mode *mode) 1418 { 1419 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1420 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1421 1422 /* XXX check mode bandwidth */ 1423 1424 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1425 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1426 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1427 1428 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1429 return MODE_PANEL; 1430 1431 if (encoder) { 1432 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1433 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1434 1435 /* AVIVO hardware supports downscaling modes larger than the panel 1436 * to the panel size, but I'm not sure this is desirable. 1437 */ 1438 if ((mode->hdisplay > native_mode->hdisplay) || 1439 (mode->vdisplay > native_mode->vdisplay)) 1440 return MODE_PANEL; 1441 1442 /* if scaling is disabled, block non-native modes */ 1443 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1444 if ((mode->hdisplay != native_mode->hdisplay) || 1445 (mode->vdisplay != native_mode->vdisplay)) 1446 return MODE_PANEL; 1447 } 1448 } 1449 return MODE_OK; 1450 } else { 1451 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1452 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1453 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1454 } else { 1455 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1456 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1457 if (mode->clock > 340000) 1458 return MODE_CLOCK_HIGH; 1459 } else { 1460 if (mode->clock > 165000) 1461 return MODE_CLOCK_HIGH; 1462 } 1463 } 1464 } 1465 1466 return MODE_OK; 1467 } 1468 1469 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1470 .get_modes = amdgpu_connector_dp_get_modes, 1471 .mode_valid = amdgpu_connector_dp_mode_valid, 1472 .best_encoder = amdgpu_connector_dvi_encoder, 1473 }; 1474 1475 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1476 .dpms = drm_helper_connector_dpms, 1477 .detect = amdgpu_connector_dp_detect, 1478 .fill_modes = drm_helper_probe_single_connector_modes, 1479 .set_property = amdgpu_connector_set_property, 1480 .early_unregister = amdgpu_connector_unregister, 1481 .destroy = amdgpu_connector_destroy, 1482 .force = amdgpu_connector_dvi_force, 1483 }; 1484 1485 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1486 .dpms = drm_helper_connector_dpms, 1487 .detect = amdgpu_connector_dp_detect, 1488 .fill_modes = drm_helper_probe_single_connector_modes, 1489 .set_property = amdgpu_connector_set_lcd_property, 1490 .early_unregister = amdgpu_connector_unregister, 1491 .destroy = amdgpu_connector_destroy, 1492 .force = amdgpu_connector_dvi_force, 1493 }; 1494 1495 void 1496 amdgpu_connector_add(struct amdgpu_device *adev, 1497 uint32_t connector_id, 1498 uint32_t supported_device, 1499 int connector_type, 1500 struct amdgpu_i2c_bus_rec *i2c_bus, 1501 uint16_t connector_object_id, 1502 struct amdgpu_hpd *hpd, 1503 struct amdgpu_router *router) 1504 { 1505 struct drm_device *dev = adev->ddev; 1506 struct drm_connector *connector; 1507 struct drm_connector_list_iter iter; 1508 struct amdgpu_connector *amdgpu_connector; 1509 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1510 struct drm_encoder *encoder; 1511 struct amdgpu_encoder *amdgpu_encoder; 1512 struct i2c_adapter *ddc = NULL; 1513 uint32_t subpixel_order = SubPixelNone; 1514 bool shared_ddc = false; 1515 bool is_dp_bridge = false; 1516 bool has_aux = false; 1517 1518 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1519 return; 1520 1521 /* see if we already added it */ 1522 drm_connector_list_iter_begin(dev, &iter); 1523 drm_for_each_connector_iter(connector, &iter) { 1524 amdgpu_connector = to_amdgpu_connector(connector); 1525 if (amdgpu_connector->connector_id == connector_id) { 1526 amdgpu_connector->devices |= supported_device; 1527 drm_connector_list_iter_end(&iter); 1528 return; 1529 } 1530 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1531 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1532 amdgpu_connector->shared_ddc = true; 1533 shared_ddc = true; 1534 } 1535 if (amdgpu_connector->router_bus && router->ddc_valid && 1536 (amdgpu_connector->router.router_id == router->router_id)) { 1537 amdgpu_connector->shared_ddc = false; 1538 shared_ddc = false; 1539 } 1540 } 1541 } 1542 drm_connector_list_iter_end(&iter); 1543 1544 /* check if it's a dp bridge */ 1545 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1546 amdgpu_encoder = to_amdgpu_encoder(encoder); 1547 if (amdgpu_encoder->devices & supported_device) { 1548 switch (amdgpu_encoder->encoder_id) { 1549 case ENCODER_OBJECT_ID_TRAVIS: 1550 case ENCODER_OBJECT_ID_NUTMEG: 1551 is_dp_bridge = true; 1552 break; 1553 default: 1554 break; 1555 } 1556 } 1557 } 1558 1559 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1560 if (!amdgpu_connector) 1561 return; 1562 1563 connector = &amdgpu_connector->base; 1564 1565 amdgpu_connector->connector_id = connector_id; 1566 amdgpu_connector->devices = supported_device; 1567 amdgpu_connector->shared_ddc = shared_ddc; 1568 amdgpu_connector->connector_object_id = connector_object_id; 1569 amdgpu_connector->hpd = *hpd; 1570 1571 amdgpu_connector->router = *router; 1572 if (router->ddc_valid || router->cd_valid) { 1573 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1574 if (!amdgpu_connector->router_bus) 1575 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1576 } 1577 1578 if (is_dp_bridge) { 1579 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1580 if (!amdgpu_dig_connector) 1581 goto failed; 1582 amdgpu_connector->con_priv = amdgpu_dig_connector; 1583 if (i2c_bus->valid) { 1584 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1585 if (amdgpu_connector->ddc_bus) { 1586 has_aux = true; 1587 ddc = &amdgpu_connector->ddc_bus->adapter; 1588 } else { 1589 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1590 } 1591 } 1592 switch (connector_type) { 1593 case DRM_MODE_CONNECTOR_VGA: 1594 case DRM_MODE_CONNECTOR_DVIA: 1595 default: 1596 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1597 &amdgpu_connector_dp_funcs, 1598 connector_type, 1599 ddc); 1600 drm_connector_helper_add(&amdgpu_connector->base, 1601 &amdgpu_connector_dp_helper_funcs); 1602 connector->interlace_allowed = true; 1603 connector->doublescan_allowed = true; 1604 amdgpu_connector->dac_load_detect = true; 1605 drm_object_attach_property(&amdgpu_connector->base.base, 1606 adev->mode_info.load_detect_property, 1607 1); 1608 drm_object_attach_property(&amdgpu_connector->base.base, 1609 dev->mode_config.scaling_mode_property, 1610 DRM_MODE_SCALE_NONE); 1611 break; 1612 case DRM_MODE_CONNECTOR_DVII: 1613 case DRM_MODE_CONNECTOR_DVID: 1614 case DRM_MODE_CONNECTOR_HDMIA: 1615 case DRM_MODE_CONNECTOR_HDMIB: 1616 case DRM_MODE_CONNECTOR_DisplayPort: 1617 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1618 &amdgpu_connector_dp_funcs, 1619 connector_type, 1620 ddc); 1621 drm_connector_helper_add(&amdgpu_connector->base, 1622 &amdgpu_connector_dp_helper_funcs); 1623 drm_object_attach_property(&amdgpu_connector->base.base, 1624 adev->mode_info.underscan_property, 1625 UNDERSCAN_OFF); 1626 drm_object_attach_property(&amdgpu_connector->base.base, 1627 adev->mode_info.underscan_hborder_property, 1628 0); 1629 drm_object_attach_property(&amdgpu_connector->base.base, 1630 adev->mode_info.underscan_vborder_property, 1631 0); 1632 1633 drm_object_attach_property(&amdgpu_connector->base.base, 1634 dev->mode_config.scaling_mode_property, 1635 DRM_MODE_SCALE_NONE); 1636 1637 drm_object_attach_property(&amdgpu_connector->base.base, 1638 adev->mode_info.dither_property, 1639 AMDGPU_FMT_DITHER_DISABLE); 1640 1641 if (amdgpu_audio != 0) 1642 drm_object_attach_property(&amdgpu_connector->base.base, 1643 adev->mode_info.audio_property, 1644 AMDGPU_AUDIO_AUTO); 1645 1646 subpixel_order = SubPixelHorizontalRGB; 1647 connector->interlace_allowed = true; 1648 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1649 connector->doublescan_allowed = true; 1650 else 1651 connector->doublescan_allowed = false; 1652 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1653 amdgpu_connector->dac_load_detect = true; 1654 drm_object_attach_property(&amdgpu_connector->base.base, 1655 adev->mode_info.load_detect_property, 1656 1); 1657 } 1658 break; 1659 case DRM_MODE_CONNECTOR_LVDS: 1660 case DRM_MODE_CONNECTOR_eDP: 1661 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1662 &amdgpu_connector_edp_funcs, 1663 connector_type, 1664 ddc); 1665 drm_connector_helper_add(&amdgpu_connector->base, 1666 &amdgpu_connector_dp_helper_funcs); 1667 drm_object_attach_property(&amdgpu_connector->base.base, 1668 dev->mode_config.scaling_mode_property, 1669 DRM_MODE_SCALE_FULLSCREEN); 1670 subpixel_order = SubPixelHorizontalRGB; 1671 connector->interlace_allowed = false; 1672 connector->doublescan_allowed = false; 1673 break; 1674 } 1675 } else { 1676 switch (connector_type) { 1677 case DRM_MODE_CONNECTOR_VGA: 1678 if (i2c_bus->valid) { 1679 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1680 if (!amdgpu_connector->ddc_bus) 1681 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1682 else 1683 ddc = &amdgpu_connector->ddc_bus->adapter; 1684 } 1685 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1686 &amdgpu_connector_vga_funcs, 1687 connector_type, 1688 ddc); 1689 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1690 amdgpu_connector->dac_load_detect = true; 1691 drm_object_attach_property(&amdgpu_connector->base.base, 1692 adev->mode_info.load_detect_property, 1693 1); 1694 drm_object_attach_property(&amdgpu_connector->base.base, 1695 dev->mode_config.scaling_mode_property, 1696 DRM_MODE_SCALE_NONE); 1697 /* no HPD on analog connectors */ 1698 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1699 connector->interlace_allowed = true; 1700 connector->doublescan_allowed = true; 1701 break; 1702 case DRM_MODE_CONNECTOR_DVIA: 1703 if (i2c_bus->valid) { 1704 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1705 if (!amdgpu_connector->ddc_bus) 1706 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1707 else 1708 ddc = &amdgpu_connector->ddc_bus->adapter; 1709 } 1710 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1711 &amdgpu_connector_vga_funcs, 1712 connector_type, 1713 ddc); 1714 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1715 amdgpu_connector->dac_load_detect = true; 1716 drm_object_attach_property(&amdgpu_connector->base.base, 1717 adev->mode_info.load_detect_property, 1718 1); 1719 drm_object_attach_property(&amdgpu_connector->base.base, 1720 dev->mode_config.scaling_mode_property, 1721 DRM_MODE_SCALE_NONE); 1722 /* no HPD on analog connectors */ 1723 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1724 connector->interlace_allowed = true; 1725 connector->doublescan_allowed = true; 1726 break; 1727 case DRM_MODE_CONNECTOR_DVII: 1728 case DRM_MODE_CONNECTOR_DVID: 1729 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1730 if (!amdgpu_dig_connector) 1731 goto failed; 1732 amdgpu_connector->con_priv = amdgpu_dig_connector; 1733 if (i2c_bus->valid) { 1734 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1735 if (!amdgpu_connector->ddc_bus) 1736 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1737 else 1738 ddc = &amdgpu_connector->ddc_bus->adapter; 1739 } 1740 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1741 &amdgpu_connector_dvi_funcs, 1742 connector_type, 1743 ddc); 1744 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1745 subpixel_order = SubPixelHorizontalRGB; 1746 drm_object_attach_property(&amdgpu_connector->base.base, 1747 adev->mode_info.coherent_mode_property, 1748 1); 1749 drm_object_attach_property(&amdgpu_connector->base.base, 1750 adev->mode_info.underscan_property, 1751 UNDERSCAN_OFF); 1752 drm_object_attach_property(&amdgpu_connector->base.base, 1753 adev->mode_info.underscan_hborder_property, 1754 0); 1755 drm_object_attach_property(&amdgpu_connector->base.base, 1756 adev->mode_info.underscan_vborder_property, 1757 0); 1758 drm_object_attach_property(&amdgpu_connector->base.base, 1759 dev->mode_config.scaling_mode_property, 1760 DRM_MODE_SCALE_NONE); 1761 1762 if (amdgpu_audio != 0) { 1763 drm_object_attach_property(&amdgpu_connector->base.base, 1764 adev->mode_info.audio_property, 1765 AMDGPU_AUDIO_AUTO); 1766 } 1767 drm_object_attach_property(&amdgpu_connector->base.base, 1768 adev->mode_info.dither_property, 1769 AMDGPU_FMT_DITHER_DISABLE); 1770 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1771 amdgpu_connector->dac_load_detect = true; 1772 drm_object_attach_property(&amdgpu_connector->base.base, 1773 adev->mode_info.load_detect_property, 1774 1); 1775 } 1776 connector->interlace_allowed = true; 1777 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1778 connector->doublescan_allowed = true; 1779 else 1780 connector->doublescan_allowed = false; 1781 break; 1782 case DRM_MODE_CONNECTOR_HDMIA: 1783 case DRM_MODE_CONNECTOR_HDMIB: 1784 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1785 if (!amdgpu_dig_connector) 1786 goto failed; 1787 amdgpu_connector->con_priv = amdgpu_dig_connector; 1788 if (i2c_bus->valid) { 1789 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1790 if (!amdgpu_connector->ddc_bus) 1791 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1792 else 1793 ddc = &amdgpu_connector->ddc_bus->adapter; 1794 } 1795 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1796 &amdgpu_connector_dvi_funcs, 1797 connector_type, 1798 ddc); 1799 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1800 drm_object_attach_property(&amdgpu_connector->base.base, 1801 adev->mode_info.coherent_mode_property, 1802 1); 1803 drm_object_attach_property(&amdgpu_connector->base.base, 1804 adev->mode_info.underscan_property, 1805 UNDERSCAN_OFF); 1806 drm_object_attach_property(&amdgpu_connector->base.base, 1807 adev->mode_info.underscan_hborder_property, 1808 0); 1809 drm_object_attach_property(&amdgpu_connector->base.base, 1810 adev->mode_info.underscan_vborder_property, 1811 0); 1812 drm_object_attach_property(&amdgpu_connector->base.base, 1813 dev->mode_config.scaling_mode_property, 1814 DRM_MODE_SCALE_NONE); 1815 if (amdgpu_audio != 0) { 1816 drm_object_attach_property(&amdgpu_connector->base.base, 1817 adev->mode_info.audio_property, 1818 AMDGPU_AUDIO_AUTO); 1819 } 1820 drm_object_attach_property(&amdgpu_connector->base.base, 1821 adev->mode_info.dither_property, 1822 AMDGPU_FMT_DITHER_DISABLE); 1823 subpixel_order = SubPixelHorizontalRGB; 1824 connector->interlace_allowed = true; 1825 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1826 connector->doublescan_allowed = true; 1827 else 1828 connector->doublescan_allowed = false; 1829 break; 1830 case DRM_MODE_CONNECTOR_DisplayPort: 1831 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1832 if (!amdgpu_dig_connector) 1833 goto failed; 1834 amdgpu_connector->con_priv = amdgpu_dig_connector; 1835 if (i2c_bus->valid) { 1836 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1837 if (amdgpu_connector->ddc_bus) { 1838 has_aux = true; 1839 ddc = &amdgpu_connector->ddc_bus->adapter; 1840 } else { 1841 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1842 } 1843 } 1844 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1845 &amdgpu_connector_dp_funcs, 1846 connector_type, 1847 ddc); 1848 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1849 subpixel_order = SubPixelHorizontalRGB; 1850 drm_object_attach_property(&amdgpu_connector->base.base, 1851 adev->mode_info.coherent_mode_property, 1852 1); 1853 drm_object_attach_property(&amdgpu_connector->base.base, 1854 adev->mode_info.underscan_property, 1855 UNDERSCAN_OFF); 1856 drm_object_attach_property(&amdgpu_connector->base.base, 1857 adev->mode_info.underscan_hborder_property, 1858 0); 1859 drm_object_attach_property(&amdgpu_connector->base.base, 1860 adev->mode_info.underscan_vborder_property, 1861 0); 1862 drm_object_attach_property(&amdgpu_connector->base.base, 1863 dev->mode_config.scaling_mode_property, 1864 DRM_MODE_SCALE_NONE); 1865 if (amdgpu_audio != 0) { 1866 drm_object_attach_property(&amdgpu_connector->base.base, 1867 adev->mode_info.audio_property, 1868 AMDGPU_AUDIO_AUTO); 1869 } 1870 drm_object_attach_property(&amdgpu_connector->base.base, 1871 adev->mode_info.dither_property, 1872 AMDGPU_FMT_DITHER_DISABLE); 1873 connector->interlace_allowed = true; 1874 /* in theory with a DP to VGA converter... */ 1875 connector->doublescan_allowed = false; 1876 break; 1877 case DRM_MODE_CONNECTOR_eDP: 1878 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1879 if (!amdgpu_dig_connector) 1880 goto failed; 1881 amdgpu_connector->con_priv = amdgpu_dig_connector; 1882 if (i2c_bus->valid) { 1883 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1884 if (amdgpu_connector->ddc_bus) { 1885 has_aux = true; 1886 ddc = &amdgpu_connector->ddc_bus->adapter; 1887 } else { 1888 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1889 } 1890 } 1891 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1892 &amdgpu_connector_edp_funcs, 1893 connector_type, 1894 ddc); 1895 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1896 drm_object_attach_property(&amdgpu_connector->base.base, 1897 dev->mode_config.scaling_mode_property, 1898 DRM_MODE_SCALE_FULLSCREEN); 1899 subpixel_order = SubPixelHorizontalRGB; 1900 connector->interlace_allowed = false; 1901 connector->doublescan_allowed = false; 1902 break; 1903 case DRM_MODE_CONNECTOR_LVDS: 1904 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1905 if (!amdgpu_dig_connector) 1906 goto failed; 1907 amdgpu_connector->con_priv = amdgpu_dig_connector; 1908 if (i2c_bus->valid) { 1909 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1910 if (!amdgpu_connector->ddc_bus) 1911 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1912 else 1913 ddc = &amdgpu_connector->ddc_bus->adapter; 1914 } 1915 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1916 &amdgpu_connector_lvds_funcs, 1917 connector_type, 1918 ddc); 1919 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1920 drm_object_attach_property(&amdgpu_connector->base.base, 1921 dev->mode_config.scaling_mode_property, 1922 DRM_MODE_SCALE_FULLSCREEN); 1923 subpixel_order = SubPixelHorizontalRGB; 1924 connector->interlace_allowed = false; 1925 connector->doublescan_allowed = false; 1926 break; 1927 } 1928 } 1929 1930 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1931 if (i2c_bus->valid) { 1932 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1933 DRM_CONNECTOR_POLL_DISCONNECT; 1934 } 1935 } else 1936 connector->polled = DRM_CONNECTOR_POLL_HPD; 1937 1938 connector->display_info.subpixel_order = subpixel_order; 1939 drm_connector_register(connector); 1940 1941 if (has_aux) 1942 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1943 1944 return; 1945 1946 failed: 1947 drm_connector_cleanup(connector); 1948 kfree(connector); 1949 } 1950
Indexes created Sun Sep 21 20:09:37 GMT 2025