1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <errno.h> 26 #include <string.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_drm.h" 30 #include "amdgpu_internal.h" 31 #include "xf86drm.h" 32 33 drm_public int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 34 unsigned size, void *value) 35 { 36 struct drm_amdgpu_info request; 37 38 memset(&request, 0, sizeof(request)); 39 request.return_pointer = (uintptr_t)value; 40 request.return_size = size; 41 request.query = info_id; 42 43 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 44 sizeof(struct drm_amdgpu_info)); 45 } 46 47 drm_public int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 48 int32_t *result) 49 { 50 struct drm_amdgpu_info request; 51 52 memset(&request, 0, sizeof(request)); 53 request.return_pointer = (uintptr_t)result; 54 request.return_size = sizeof(*result); 55 request.query = AMDGPU_INFO_CRTC_FROM_ID; 56 request.mode_crtc.id = id; 57 58 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 59 sizeof(struct drm_amdgpu_info)); 60 } 61 62 drm_public int amdgpu_read_mm_registers(amdgpu_device_handle dev, 63 unsigned dword_offset, unsigned count, uint32_t instance, 64 uint32_t flags, uint32_t *values) 65 { 66 struct drm_amdgpu_info request; 67 68 memset(&request, 0, sizeof(request)); 69 request.return_pointer = (uintptr_t)values; 70 request.return_size = count * sizeof(uint32_t); 71 request.query = AMDGPU_INFO_READ_MMR_REG; 72 request.read_mmr_reg.dword_offset = dword_offset; 73 request.read_mmr_reg.count = count; 74 request.read_mmr_reg.instance = instance; 75 request.read_mmr_reg.flags = flags; 76 77 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 78 sizeof(struct drm_amdgpu_info)); 79 } 80 81 drm_public int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, 82 unsigned type, 83 uint32_t *count) 84 { 85 struct drm_amdgpu_info request; 86 87 memset(&request, 0, sizeof(request)); 88 request.return_pointer = (uintptr_t)count; 89 request.return_size = sizeof(*count); 90 request.query = AMDGPU_INFO_HW_IP_COUNT; 91 request.query_hw_ip.type = type; 92 93 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 94 sizeof(struct drm_amdgpu_info)); 95 } 96 97 drm_public int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 98 unsigned ip_instance, 99 struct drm_amdgpu_info_hw_ip *info) 100 { 101 struct drm_amdgpu_info request; 102 103 memset(&request, 0, sizeof(request)); 104 request.return_pointer = (uintptr_t)info; 105 request.return_size = sizeof(*info); 106 request.query = AMDGPU_INFO_HW_IP_INFO; 107 request.query_hw_ip.type = type; 108 request.query_hw_ip.ip_instance = ip_instance; 109 110 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 111 sizeof(struct drm_amdgpu_info)); 112 } 113 114 drm_public int amdgpu_query_firmware_version(amdgpu_device_handle dev, 115 unsigned fw_type, unsigned ip_instance, unsigned index, 116 uint32_t *version, uint32_t *feature) 117 { 118 struct drm_amdgpu_info request; 119 struct drm_amdgpu_info_firmware firmware = {}; 120 int r; 121 122 memset(&request, 0, sizeof(request)); 123 request.return_pointer = (uintptr_t)&firmware; 124 request.return_size = sizeof(firmware); 125 request.query = AMDGPU_INFO_FW_VERSION; 126 request.query_fw.fw_type = fw_type; 127 request.query_fw.ip_instance = ip_instance; 128 request.query_fw.index = index; 129 130 r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 131 sizeof(struct drm_amdgpu_info)); 132 if (r) 133 return r; 134 135 *version = firmware.ver; 136 *feature = firmware.feature; 137 return 0; 138 } 139 140 drm_public int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev, 141 unsigned type, 142 unsigned ip_instance, 143 struct drm_amdgpu_info_uq_fw_areas *info) 144 { 145 struct drm_amdgpu_info request; 146 147 memset(&request, 0, sizeof(request)); 148 request.return_pointer = (uintptr_t)info; 149 request.return_size = sizeof(*info); 150 request.query = AMDGPU_INFO_UQ_FW_AREAS; 151 request.query_hw_ip.type = type; 152 request.query_hw_ip.ip_instance = ip_instance; 153 154 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 155 sizeof(struct drm_amdgpu_info)); 156 } 157 158 drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) 159 { 160 int r, i; 161 162 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(dev->dev_info), 163 &dev->dev_info); 164 if (r) 165 return r; 166 167 dev->info.asic_id = dev->dev_info.device_id; 168 dev->info.chip_rev = dev->dev_info.chip_rev; 169 dev->info.chip_external_rev = dev->dev_info.external_rev; 170 dev->info.family_id = dev->dev_info.family; 171 dev->info.max_engine_clk = dev->dev_info.max_engine_clock; 172 dev->info.max_memory_clk = dev->dev_info.max_memory_clock; 173 dev->info.gpu_counter_freq = dev->dev_info.gpu_counter_freq; 174 dev->info.enabled_rb_pipes_mask = dev->dev_info.enabled_rb_pipes_mask; 175 dev->info.rb_pipes = dev->dev_info.num_rb_pipes; 176 dev->info.ids_flags = dev->dev_info.ids_flags; 177 dev->info.num_hw_gfx_contexts = dev->dev_info.num_hw_gfx_contexts; 178 dev->info.num_shader_engines = dev->dev_info.num_shader_engines; 179 dev->info.num_shader_arrays_per_engine = 180 dev->dev_info.num_shader_arrays_per_engine; 181 dev->info.vram_type = dev->dev_info.vram_type; 182 dev->info.vram_bit_width = dev->dev_info.vram_bit_width; 183 dev->info.ce_ram_size = dev->dev_info.ce_ram_size; 184 dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config; 185 dev->info.pci_rev_id = dev->dev_info.pci_rev; 186 187 if (dev->info.family_id < AMDGPU_FAMILY_AI) { 188 for (i = 0; i < (int)dev->info.num_shader_engines; i++) { 189 unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) | 190 (AMDGPU_INFO_MMR_SH_INDEX_MASK << 191 AMDGPU_INFO_MMR_SH_INDEX_SHIFT); 192 193 r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0, 194 &dev->info.backend_disable[i]); 195 if (r) 196 return r; 197 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */ 198 dev->info.backend_disable[i] = 199 (dev->info.backend_disable[i] >> 16) & 0xff; 200 201 r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0, 202 &dev->info.pa_sc_raster_cfg[i]); 203 if (r) 204 return r; 205 206 if (dev->info.family_id >= AMDGPU_FAMILY_CI) { 207 r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, 208 &dev->info.pa_sc_raster_cfg1[i]); 209 if (r) 210 return r; 211 } 212 } 213 } 214 215 r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0, 216 &dev->info.gb_addr_cfg); 217 if (r) 218 return r; 219 220 if (dev->info.family_id < AMDGPU_FAMILY_AI) { 221 r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0, 222 dev->info.gb_tile_mode); 223 if (r) 224 return r; 225 226 if (dev->info.family_id >= AMDGPU_FAMILY_CI) { 227 r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, 228 dev->info.gb_macro_tile_mode); 229 if (r) 230 return r; 231 } 232 233 r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0, 234 &dev->info.mc_arb_ramcfg); 235 if (r) 236 return r; 237 } 238 239 dev->info.cu_active_number = dev->dev_info.cu_active_number; 240 dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask; 241 memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap)); 242 243 /* TODO: info->max_quad_shader_pipes is not set */ 244 /* TODO: info->avail_quad_shader_pipes is not set */ 245 /* TODO: info->cache_entries_per_quad_pipe is not set */ 246 return 0; 247 } 248 249 drm_public int amdgpu_query_gpu_info(amdgpu_device_handle dev, 250 struct amdgpu_gpu_info *info) 251 { 252 if (!dev || !info) 253 return -EINVAL; 254 255 /* Get ASIC info*/ 256 *info = dev->info; 257 258 return 0; 259 } 260 261 drm_public int amdgpu_query_heap_info(amdgpu_device_handle dev, 262 uint32_t heap, 263 uint32_t flags, 264 struct amdgpu_heap_info *info) 265 { 266 struct drm_amdgpu_info_vram_gtt vram_gtt_info = {}; 267 int r; 268 269 r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT, 270 sizeof(vram_gtt_info), &vram_gtt_info); 271 if (r) 272 return r; 273 274 /* Get heap information */ 275 switch (heap) { 276 case AMDGPU_GEM_DOMAIN_VRAM: 277 /* query visible only vram heap */ 278 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 279 info->heap_size = vram_gtt_info.vram_cpu_accessible_size; 280 else /* query total vram heap */ 281 info->heap_size = vram_gtt_info.vram_size; 282 283 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; 284 285 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 286 r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, 287 sizeof(info->heap_usage), 288 &info->heap_usage); 289 else 290 r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE, 291 sizeof(info->heap_usage), 292 &info->heap_usage); 293 if (r) 294 return r; 295 break; 296 case AMDGPU_GEM_DOMAIN_GTT: 297 info->heap_size = vram_gtt_info.gtt_size; 298 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; 299 300 r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, 301 sizeof(info->heap_usage), 302 &info->heap_usage); 303 if (r) 304 return r; 305 break; 306 default: 307 return -EINVAL; 308 } 309 310 return 0; 311 } 312 313 drm_public int amdgpu_query_gds_info(amdgpu_device_handle dev, 314 struct amdgpu_gds_resource_info *gds_info) 315 { 316 struct drm_amdgpu_info_gds gds_config = {}; 317 int r; 318 319 if (!gds_info) 320 return -EINVAL; 321 322 r = amdgpu_query_info(dev, AMDGPU_INFO_GDS_CONFIG, 323 sizeof(gds_config), &gds_config); 324 if (r) 325 return r; 326 327 gds_info->gds_gfx_partition_size = gds_config.gds_gfx_partition_size; 328 gds_info->compute_partition_size = gds_config.compute_partition_size; 329 gds_info->gds_total_size = gds_config.gds_total_size; 330 gds_info->gws_per_gfx_partition = gds_config.gws_per_gfx_partition; 331 gds_info->gws_per_compute_partition = gds_config.gws_per_compute_partition; 332 gds_info->oa_per_gfx_partition = gds_config.oa_per_gfx_partition; 333 gds_info->oa_per_compute_partition = gds_config.oa_per_compute_partition; 334 335 return 0; 336 } 337 338 drm_public int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 339 unsigned size, void *value) 340 { 341 struct drm_amdgpu_info request; 342 343 memset(&request, 0, sizeof(request)); 344 request.return_pointer = (uintptr_t)value; 345 request.return_size = size; 346 request.query = AMDGPU_INFO_SENSOR; 347 request.sensor_info.type = sensor_type; 348 349 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 350 sizeof(struct drm_amdgpu_info)); 351 } 352 353 drm_public int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, 354 unsigned size, void *value) 355 { 356 struct drm_amdgpu_info request; 357 358 memset(&request, 0, sizeof(request)); 359 request.return_pointer = (uintptr_t)value; 360 request.return_size = size; 361 request.query = AMDGPU_INFO_VIDEO_CAPS; 362 request.sensor_info.type = cap_type; 363 364 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 365 sizeof(struct drm_amdgpu_info)); 366 } 367 368 drm_public int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, 369 unsigned size, void *value) 370 { 371 struct drm_amdgpu_info request; 372 373 memset(&request, 0, sizeof(request)); 374 request.return_pointer = (uintptr_t)value; 375 request.return_size = size; 376 request.query = AMDGPU_INFO_GPUVM_FAULT; 377 378 return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 379 sizeof(struct drm_amdgpu_info)); 380 } 381
Indexes created Tue Aug 04 00:24:20 UTC 2026