1 /* $NetBSD: amdgpu_drv.c,v 1.8 2021/12/19 12:23:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_drv.c,v 1.8 2021/12/19 12:23:42 riastradh Exp $"); 29 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_gem.h> 33 #include <drm/drm_vblank.h> 34 #include "amdgpu_drv.h" 35 36 #include <drm/drm_pci.h> 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include <linux/vga_switcheroo.h> 43 #include <drm/drm_probe_helper.h> 44 #include <linux/mmu_notifier.h> 45 46 #include "amdgpu.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_dma_buf.h" 49 50 #include "amdgpu_amdkfd.h" 51 52 #include "amdgpu_ras.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 */ 95 #define KMS_DRIVER_MAJOR 3 96 #define KMS_DRIVER_MINOR 36 97 #define KMS_DRIVER_PATCHLEVEL 0 98 99 int amdgpu_vram_limit = 0; 100 int amdgpu_vis_vram_limit = 0; 101 int amdgpu_gart_size = -1; /* auto */ 102 int amdgpu_gtt_size = -1; /* auto */ 103 int amdgpu_moverate = -1; /* auto */ 104 int amdgpu_benchmarking = 0; 105 int amdgpu_testing = 0; 106 int amdgpu_audio = -1; 107 int amdgpu_disp_priority = 0; 108 int amdgpu_hw_i2c = 0; 109 int amdgpu_pcie_gen2 = -1; 110 int amdgpu_msi = -1; 111 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 112 int amdgpu_dpm = -1; 113 int amdgpu_fw_load_type = -1; 114 int amdgpu_aspm = -1; 115 int amdgpu_runtime_pm = -1; 116 uint amdgpu_ip_block_mask = 0xffffffff; 117 int amdgpu_bapm = -1; 118 int amdgpu_deep_color = 0; 119 int amdgpu_vm_size = -1; 120 int amdgpu_vm_fragment_size = -1; 121 int amdgpu_vm_block_size = -1; 122 int amdgpu_vm_fault_stop = 0; 123 int amdgpu_vm_debug = 0; 124 int amdgpu_vm_update_mode = -1; 125 int amdgpu_exp_hw_support = 0; 126 int amdgpu_dc = -1; 127 int amdgpu_sched_jobs = 32; 128 int amdgpu_sched_hw_submission = 2; 129 uint amdgpu_pcie_gen_cap = 0; 130 uint amdgpu_pcie_lane_cap = 0; 131 uint amdgpu_cg_mask = 0xffffffff; 132 uint amdgpu_pg_mask = 0xffffffff; 133 uint amdgpu_sdma_phase_quantum = 32; 134 char *amdgpu_disable_cu = NULL; 135 char *amdgpu_virtual_display = NULL; 136 /* OverDrive(bit 14) disabled by default*/ 137 uint amdgpu_pp_feature_mask = 0xffffbfff; 138 uint amdgpu_force_long_training = 0; 139 int amdgpu_job_hang_limit = 0; 140 int amdgpu_lbpw = -1; 141 int amdgpu_compute_multipipe = -1; 142 int amdgpu_gpu_recovery = -1; /* auto */ 143 int amdgpu_emu_mode = 0; 144 uint amdgpu_smu_memory_pool_size = 0; 145 /* FBC (bit 0) disabled by default*/ 146 uint amdgpu_dc_feature_mask = 0; 147 int amdgpu_async_gfx_ring = 1; 148 int amdgpu_mcbp = 0; 149 int amdgpu_discovery = -1; 150 int amdgpu_mes = 0; 151 int amdgpu_noretry; 152 int amdgpu_force_asic_type = -1; 153 154 struct amdgpu_mgpu_info mgpu_info = { 155 #ifndef __NetBSD__ 156 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 157 #endif 158 }; 159 int amdgpu_ras_enable = -1; 160 uint amdgpu_ras_mask = 0xffffffff; 161 162 /** 163 * DOC: vramlimit (int) 164 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 165 */ 166 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 167 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 168 169 /** 170 * DOC: vis_vramlimit (int) 171 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 172 */ 173 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 174 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 175 176 /** 177 * DOC: gartsize (uint) 178 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 179 */ 180 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 181 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 182 183 /** 184 * DOC: gttsize (int) 185 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 186 * otherwise 3/4 RAM size). 187 */ 188 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 189 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 190 191 /** 192 * DOC: moverate (int) 193 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 194 */ 195 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 196 module_param_named(moverate, amdgpu_moverate, int, 0600); 197 198 /** 199 * DOC: benchmark (int) 200 * Run benchmarks. The default is 0 (Skip benchmarks). 201 */ 202 MODULE_PARM_DESC(benchmark, "Run benchmark"); 203 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 204 205 /** 206 * DOC: test (int) 207 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 208 */ 209 MODULE_PARM_DESC(test, "Run tests"); 210 module_param_named(test, amdgpu_testing, int, 0444); 211 212 /** 213 * DOC: audio (int) 214 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 215 */ 216 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 217 module_param_named(audio, amdgpu_audio, int, 0444); 218 219 /** 220 * DOC: disp_priority (int) 221 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 222 */ 223 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 224 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 225 226 /** 227 * DOC: hw_i2c (int) 228 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 229 */ 230 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 231 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 232 233 /** 234 * DOC: pcie_gen2 (int) 235 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 236 */ 237 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 238 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 239 240 /** 241 * DOC: msi (int) 242 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 243 */ 244 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 245 module_param_named(msi, amdgpu_msi, int, 0444); 246 247 /** 248 * DOC: lockup_timeout (string) 249 * Set GPU scheduler timeout value in ms. 250 * 251 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 252 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 253 * to the default timeout. 254 * 255 * - With one value specified, the setting will apply to all non-compute jobs. 256 * - With multiple values specified, the first one will be for GFX. 257 * The second one is for Compute. The third and fourth ones are 258 * for SDMA and Video. 259 * 260 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 261 * jobs is 10000. And there is no timeout enforced on compute jobs. 262 */ 263 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 264 "for passthrough or sriov, 10000 for all jobs." 265 " 0: keep default value. negative: infinity timeout), " 266 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 267 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 268 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 269 270 /** 271 * DOC: dpm (int) 272 * Override for dynamic power management setting 273 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 274 * The default is -1 (auto). 275 */ 276 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 277 module_param_named(dpm, amdgpu_dpm, int, 0444); 278 279 /** 280 * DOC: fw_load_type (int) 281 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 282 */ 283 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 284 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 285 286 /** 287 * DOC: aspm (int) 288 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 289 */ 290 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 291 module_param_named(aspm, amdgpu_aspm, int, 0444); 292 293 /** 294 * DOC: runpm (int) 295 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 296 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 297 */ 298 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 299 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 300 301 /** 302 * DOC: ip_block_mask (uint) 303 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 304 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 305 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 306 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 307 */ 308 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 309 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 310 311 /** 312 * DOC: bapm (int) 313 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 314 * The default -1 (auto, enabled) 315 */ 316 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 317 module_param_named(bapm, amdgpu_bapm, int, 0444); 318 319 /** 320 * DOC: deep_color (int) 321 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 322 */ 323 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 324 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 325 326 /** 327 * DOC: vm_size (int) 328 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 329 */ 330 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 331 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 332 333 /** 334 * DOC: vm_fragment_size (int) 335 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 336 */ 337 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 338 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 339 340 /** 341 * DOC: vm_block_size (int) 342 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 343 */ 344 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 345 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 346 347 /** 348 * DOC: vm_fault_stop (int) 349 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 350 */ 351 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 352 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 353 354 /** 355 * DOC: vm_debug (int) 356 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 357 */ 358 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 359 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 360 361 /** 362 * DOC: vm_update_mode (int) 363 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 364 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 365 */ 366 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 367 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 368 369 /** 370 * DOC: exp_hw_support (int) 371 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 372 */ 373 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 374 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 375 376 /** 377 * DOC: dc (int) 378 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 379 */ 380 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 381 module_param_named(dc, amdgpu_dc, int, 0444); 382 383 /** 384 * DOC: sched_jobs (int) 385 * Override the max number of jobs supported in the sw queue. The default is 32. 386 */ 387 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 388 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 389 390 /** 391 * DOC: sched_hw_submission (int) 392 * Override the max number of HW submissions. The default is 2. 393 */ 394 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 395 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 396 397 /** 398 * DOC: ppfeaturemask (uint) 399 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 400 * The default is the current set of stable power features. 401 */ 402 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 403 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 404 405 /** 406 * DOC: forcelongtraining (uint) 407 * Force long memory training in resume. 408 * The default is zero, indicates short training in resume. 409 */ 410 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 411 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 412 413 /** 414 * DOC: pcie_gen_cap (uint) 415 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 416 * The default is 0 (automatic for each asic). 417 */ 418 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 419 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 420 421 /** 422 * DOC: pcie_lane_cap (uint) 423 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 424 * The default is 0 (automatic for each asic). 425 */ 426 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 427 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 428 429 /** 430 * DOC: cg_mask (uint) 431 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 432 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 433 */ 434 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 435 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 436 437 /** 438 * DOC: pg_mask (uint) 439 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 440 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 441 */ 442 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 443 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 444 445 /** 446 * DOC: sdma_phase_quantum (uint) 447 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 448 */ 449 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 450 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 451 452 /** 453 * DOC: disable_cu (charp) 454 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 455 */ 456 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 457 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 458 459 /** 460 * DOC: virtual_display (charp) 461 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 462 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 463 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 464 * device at 26:00.0. The default is NULL. 465 */ 466 MODULE_PARM_DESC(virtual_display, 467 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 468 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 469 470 /** 471 * DOC: job_hang_limit (int) 472 * Set how much time allow a job hang and not drop it. The default is 0. 473 */ 474 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 475 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 476 477 /** 478 * DOC: lbpw (int) 479 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 480 */ 481 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 482 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 483 484 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 485 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 486 487 /** 488 * DOC: gpu_recovery (int) 489 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 490 */ 491 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 492 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 493 494 /** 495 * DOC: emu_mode (int) 496 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 497 */ 498 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 499 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 500 501 /** 502 * DOC: ras_enable (int) 503 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 504 */ 505 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 506 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 507 508 /** 509 * DOC: ras_mask (uint) 510 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 511 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 512 */ 513 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 514 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 515 516 /** 517 * DOC: si_support (int) 518 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 519 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 520 * otherwise using amdgpu driver. 521 */ 522 #ifdef CONFIG_DRM_AMDGPU_SI 523 524 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 525 int amdgpu_si_support = 0; 526 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 527 #else 528 int amdgpu_si_support = 1; 529 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 530 #endif 531 532 module_param_named(si_support, amdgpu_si_support, int, 0444); 533 #endif 534 535 /** 536 * DOC: cik_support (int) 537 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 538 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 539 * otherwise using amdgpu driver. 540 */ 541 #ifdef CONFIG_DRM_AMDGPU_CIK 542 543 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 544 int amdgpu_cik_support = 0; 545 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 546 #else 547 int amdgpu_cik_support = 1; 548 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 549 #endif 550 551 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 552 #endif 553 554 /** 555 * DOC: smu_memory_pool_size (uint) 556 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 557 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 558 */ 559 MODULE_PARM_DESC(smu_memory_pool_size, 560 "reserve gtt for smu debug usage, 0 = disable," 561 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 562 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 563 564 /** 565 * DOC: async_gfx_ring (int) 566 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 567 */ 568 MODULE_PARM_DESC(async_gfx_ring, 569 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 570 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 571 572 /** 573 * DOC: mcbp (int) 574 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 575 */ 576 MODULE_PARM_DESC(mcbp, 577 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 578 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 579 580 /** 581 * DOC: discovery (int) 582 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 583 * (-1 = auto (default), 0 = disabled, 1 = enabled) 584 */ 585 MODULE_PARM_DESC(discovery, 586 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 587 module_param_named(discovery, amdgpu_discovery, int, 0444); 588 589 /** 590 * DOC: mes (int) 591 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 592 * (0 = disabled (default), 1 = enabled) 593 */ 594 MODULE_PARM_DESC(mes, 595 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 596 module_param_named(mes, amdgpu_mes, int, 0444); 597 598 MODULE_PARM_DESC(noretry, 599 "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); 600 module_param_named(noretry, amdgpu_noretry, int, 0644); 601 602 /** 603 * DOC: force_asic_type (int) 604 * A non negative value used to specify the asic type for all supported GPUs. 605 */ 606 MODULE_PARM_DESC(force_asic_type, 607 "A non negative value used to specify the asic type for all supported GPUs"); 608 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 609 610 611 612 #ifdef CONFIG_HSA_AMD 613 /** 614 * DOC: sched_policy (int) 615 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 616 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 617 * assigns queues to HQDs. 618 */ 619 int sched_policy = KFD_SCHED_POLICY_HWS; 620 module_param(sched_policy, int, 0444); 621 MODULE_PARM_DESC(sched_policy, 622 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 623 624 /** 625 * DOC: hws_max_conc_proc (int) 626 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 627 * number of VMIDs assigned to the HWS, which is also the default. 628 */ 629 int hws_max_conc_proc = 8; 630 module_param(hws_max_conc_proc, int, 0444); 631 MODULE_PARM_DESC(hws_max_conc_proc, 632 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 633 634 /** 635 * DOC: cwsr_enable (int) 636 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 637 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 638 * disables it. 639 */ 640 int cwsr_enable = 1; 641 module_param(cwsr_enable, int, 0444); 642 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 643 644 /** 645 * DOC: max_num_of_queues_per_device (int) 646 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 647 * is 4096. 648 */ 649 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 650 module_param(max_num_of_queues_per_device, int, 0444); 651 MODULE_PARM_DESC(max_num_of_queues_per_device, 652 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 653 654 /** 655 * DOC: send_sigterm (int) 656 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 657 * but just print errors on dmesg. Setting 1 enables sending sigterm. 658 */ 659 int send_sigterm; 660 module_param(send_sigterm, int, 0444); 661 MODULE_PARM_DESC(send_sigterm, 662 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 663 664 /** 665 * DOC: debug_largebar (int) 666 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 667 * system. This limits the VRAM size reported to ROCm applications to the visible 668 * size, usually 256MB. 669 * Default value is 0, diabled. 670 */ 671 int debug_largebar; 672 module_param(debug_largebar, int, 0444); 673 MODULE_PARM_DESC(debug_largebar, 674 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 675 676 /** 677 * DOC: ignore_crat (int) 678 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 679 * table to get information about AMD APUs. This option can serve as a workaround on 680 * systems with a broken CRAT table. 681 */ 682 int ignore_crat; 683 module_param(ignore_crat, int, 0444); 684 MODULE_PARM_DESC(ignore_crat, 685 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 686 687 /** 688 * DOC: halt_if_hws_hang (int) 689 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 690 * Setting 1 enables halt on hang. 691 */ 692 int halt_if_hws_hang; 693 module_param(halt_if_hws_hang, int, 0644); 694 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 695 696 /** 697 * DOC: hws_gws_support(bool) 698 * Whether HWS support gws barriers. Default value: false (not supported) 699 * This will be replaced with a MEC firmware version check once firmware 700 * is ready 701 */ 702 bool hws_gws_support; 703 module_param(hws_gws_support, bool, 0444); 704 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 705 706 /** 707 * DOC: queue_preemption_timeout_ms (int) 708 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 709 */ 710 int queue_preemption_timeout_ms = 9000; 711 module_param(queue_preemption_timeout_ms, int, 0644); 712 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 713 #endif 714 715 /** 716 * DOC: dcfeaturemask (uint) 717 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 718 * The default is the current set of stable display features. 719 */ 720 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 721 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 722 723 /** 724 * DOC: abmlevel (uint) 725 * Override the default ABM (Adaptive Backlight Management) level used for DC 726 * enabled hardware. Requires DMCU to be supported and loaded. 727 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 728 * default. Values 1-4 control the maximum allowable brightness reduction via 729 * the ABM algorithm, with 1 being the least reduction and 4 being the most 730 * reduction. 731 * 732 * Defaults to 0, or disabled. Userspace can still override this level later 733 * after boot. 734 */ 735 uint amdgpu_dm_abm_level = 0; 736 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 737 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 738 739 static const struct pci_device_id pciidlist[] = { 740 #ifdef CONFIG_DRM_AMDGPU_SI 741 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 742 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 743 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 744 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 745 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 746 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 747 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 748 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 749 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 750 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 751 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 752 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 753 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 754 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 755 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 756 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 757 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 758 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 759 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 760 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 761 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 762 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 763 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 764 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 765 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 766 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 767 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 768 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 769 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 770 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 771 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 772 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 773 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 774 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 775 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 776 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 777 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 778 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 779 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 780 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 781 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 782 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 783 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 784 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 785 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 786 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 787 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 788 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 789 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 790 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 791 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 792 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 793 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 794 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 795 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 796 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 797 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 798 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 799 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 800 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 801 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 802 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 803 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 804 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 805 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 806 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 807 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 808 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 809 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 810 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 811 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 812 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 813 #endif 814 #ifdef CONFIG_DRM_AMDGPU_CIK 815 /* Kaveri */ 816 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 817 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 818 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 819 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 820 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 821 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 822 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 823 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 824 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 825 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 826 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 827 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 828 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 829 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 830 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 831 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 832 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 833 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 834 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 836 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 837 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 838 /* Bonaire */ 839 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 840 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 841 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 842 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 843 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 844 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 845 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 846 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 847 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 848 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 849 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 850 /* Hawaii */ 851 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 852 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 853 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 854 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 855 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 856 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 857 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 858 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 859 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 860 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 861 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 862 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 863 /* Kabini */ 864 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 865 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 866 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 867 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 868 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 869 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 870 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 871 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 872 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 873 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 874 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 875 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 876 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 877 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 878 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 879 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 880 /* mullins */ 881 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 884 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 890 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 891 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 893 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 895 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 897 #endif 898 /* topaz */ 899 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 900 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 901 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 902 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 903 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 904 /* tonga */ 905 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 906 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 907 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 908 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 909 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 910 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 911 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 912 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 913 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 914 /* fiji */ 915 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 916 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 917 /* carrizo */ 918 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 919 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 920 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 921 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 922 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 923 /* stoney */ 924 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 925 /* Polaris11 */ 926 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 927 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 928 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 929 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 930 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 931 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 932 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 933 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 934 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 935 /* Polaris10 */ 936 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 937 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 938 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 939 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 940 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 941 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 942 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 943 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 944 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 945 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 946 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 947 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 948 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 949 /* Polaris12 */ 950 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 951 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 952 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 953 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 954 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 955 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 956 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 957 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 958 /* VEGAM */ 959 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 960 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 961 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 962 /* Vega 10 */ 963 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 964 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 965 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 966 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 967 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 968 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 969 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 970 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 971 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 972 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 973 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 974 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 975 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 976 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 977 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 978 /* Vega 12 */ 979 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 980 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 981 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 982 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 983 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 984 /* Vega 20 */ 985 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 986 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 987 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 988 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 989 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 990 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 991 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 992 /* Raven */ 993 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 994 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 995 /* Arcturus */ 996 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 997 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 998 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 999 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1000 /* Navi10 */ 1001 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1002 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1003 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1004 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1005 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1006 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1007 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1008 /* Navi14 */ 1009 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1010 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1011 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1012 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1013 1014 /* Renoir */ 1015 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1016 1017 /* Navi12 */ 1018 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1019 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1020 1021 {0, 0, 0} 1022 }; 1023 1024 MODULE_DEVICE_TABLE(pci, pciidlist); 1025 1026 static struct drm_driver kms_driver; 1027 1028 #ifndef __NetBSD__ 1029 static int amdgpu_pci_probe(struct pci_dev *pdev, 1030 const struct pci_device_id *ent) 1031 { 1032 struct drm_device *dev; 1033 unsigned long flags = ent->driver_data; 1034 int ret, retry = 0; 1035 bool supports_atomic = false; 1036 1037 if (!amdgpu_virtual_display && 1038 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1039 supports_atomic = true; 1040 1041 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1042 DRM_INFO("This hardware requires experimental hardware support.\n" 1043 "See modparam exp_hw_support\n"); 1044 return -ENODEV; 1045 } 1046 1047 #ifdef CONFIG_DRM_AMDGPU_SI 1048 if (!amdgpu_si_support) { 1049 switch (flags & AMD_ASIC_MASK) { 1050 case CHIP_TAHITI: 1051 case CHIP_PITCAIRN: 1052 case CHIP_VERDE: 1053 case CHIP_OLAND: 1054 case CHIP_HAINAN: 1055 dev_info(&pdev->dev, 1056 "SI support provided by radeon.\n"); 1057 dev_info(&pdev->dev, 1058 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1059 ); 1060 return -ENODEV; 1061 } 1062 } 1063 #endif 1064 #ifdef CONFIG_DRM_AMDGPU_CIK 1065 if (!amdgpu_cik_support) { 1066 switch (flags & AMD_ASIC_MASK) { 1067 case CHIP_KAVERI: 1068 case CHIP_BONAIRE: 1069 case CHIP_HAWAII: 1070 case CHIP_KABINI: 1071 case CHIP_MULLINS: 1072 dev_info(&pdev->dev, 1073 "CIK support provided by radeon.\n"); 1074 dev_info(&pdev->dev, 1075 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1076 ); 1077 return -ENODEV; 1078 } 1079 } 1080 #endif 1081 1082 /* Get rid of things like offb */ 1083 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1084 if (ret) 1085 return ret; 1086 1087 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1088 if (IS_ERR(dev)) 1089 return PTR_ERR(dev); 1090 1091 if (!supports_atomic) 1092 dev->driver_features &= ~DRIVER_ATOMIC; 1093 1094 ret = pci_enable_device(pdev); 1095 if (ret) 1096 goto err_free; 1097 1098 dev->pdev = pdev; 1099 1100 pci_set_drvdata(pdev, dev); 1101 1102 retry_init: 1103 ret = drm_dev_register(dev, ent->driver_data); 1104 if (ret == -EAGAIN && ++retry <= 3) { 1105 DRM_INFO("retry init %d\n", retry); 1106 /* Don't request EX mode too frequently which is attacking */ 1107 msleep(5000); 1108 goto retry_init; 1109 } else if (ret) 1110 goto err_pci; 1111 1112 return 0; 1113 1114 err_pci: 1115 pci_disable_device(pdev); 1116 err_free: 1117 drm_dev_put(dev); 1118 return ret; 1119 } 1120 1121 static void 1122 amdgpu_pci_remove(struct pci_dev *pdev) 1123 { 1124 struct drm_device *dev = pci_get_drvdata(pdev); 1125 1126 #ifdef MODULE 1127 if (THIS_MODULE->state != MODULE_STATE_GOING) 1128 #endif 1129 DRM_ERROR("Hotplug removal is not supported\n"); 1130 drm_dev_unplug(dev); 1131 drm_dev_put(dev); 1132 pci_disable_device(pdev); 1133 pci_set_drvdata(pdev, NULL); 1134 } 1135 1136 static void 1137 amdgpu_pci_shutdown(struct pci_dev *pdev) 1138 { 1139 struct drm_device *dev = pci_get_drvdata(pdev); 1140 struct amdgpu_device *adev = dev->dev_private; 1141 1142 if (amdgpu_ras_intr_triggered()) 1143 return; 1144 1145 /* if we are running in a VM, make sure the device 1146 * torn down properly on reboot/shutdown. 1147 * unfortunately we can't detect certain 1148 * hypervisors so just do this all the time. 1149 */ 1150 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1151 amdgpu_device_ip_suspend(adev); 1152 adev->mp1_state = PP_MP1_STATE_NONE; 1153 } 1154 1155 static int amdgpu_pmops_suspend(struct device *dev) 1156 { 1157 struct drm_device *drm_dev = dev_get_drvdata(dev); 1158 1159 return amdgpu_device_suspend(drm_dev, true); 1160 } 1161 1162 static int amdgpu_pmops_resume(struct device *dev) 1163 { 1164 struct drm_device *drm_dev = dev_get_drvdata(dev); 1165 1166 /* GPU comes up enabled by the bios on resume */ 1167 if (amdgpu_device_supports_boco(drm_dev) || 1168 amdgpu_device_supports_baco(drm_dev)) { 1169 pm_runtime_disable(dev); 1170 pm_runtime_set_active(dev); 1171 pm_runtime_enable(dev); 1172 } 1173 1174 return amdgpu_device_resume(drm_dev, true); 1175 } 1176 1177 static int amdgpu_pmops_freeze(struct device *dev) 1178 { 1179 struct drm_device *drm_dev = dev_get_drvdata(dev); 1180 struct amdgpu_device *adev = drm_dev->dev_private; 1181 int r; 1182 1183 r = amdgpu_device_suspend(drm_dev, true); 1184 if (r) 1185 return r; 1186 return amdgpu_asic_reset(adev); 1187 } 1188 1189 static int amdgpu_pmops_thaw(struct device *dev) 1190 { 1191 struct drm_device *drm_dev = dev_get_drvdata(dev); 1192 1193 return amdgpu_device_resume(drm_dev, true); 1194 } 1195 1196 static int amdgpu_pmops_poweroff(struct device *dev) 1197 { 1198 struct drm_device *drm_dev = dev_get_drvdata(dev); 1199 1200 return amdgpu_device_suspend(drm_dev, true); 1201 } 1202 1203 static int amdgpu_pmops_restore(struct device *dev) 1204 { 1205 struct drm_device *drm_dev = dev_get_drvdata(dev); 1206 1207 return amdgpu_device_resume(drm_dev, true); 1208 } 1209 1210 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1211 { 1212 struct pci_dev *pdev = to_pci_dev(dev); 1213 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1214 struct amdgpu_device *adev = drm_dev->dev_private; 1215 int ret, i; 1216 1217 if (!adev->runpm) { 1218 pm_runtime_forbid(dev); 1219 return -EBUSY; 1220 } 1221 1222 /* wait for all rings to drain before suspending */ 1223 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1224 struct amdgpu_ring *ring = adev->rings[i]; 1225 if (ring && ring->sched.ready) { 1226 ret = amdgpu_fence_wait_empty(ring); 1227 if (ret) 1228 return -EBUSY; 1229 } 1230 } 1231 1232 if (amdgpu_device_supports_boco(drm_dev)) 1233 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1234 drm_kms_helper_poll_disable(drm_dev); 1235 1236 ret = amdgpu_device_suspend(drm_dev, false); 1237 if (amdgpu_device_supports_boco(drm_dev)) { 1238 /* Only need to handle PCI state in the driver for ATPX 1239 * PCI core handles it for _PR3. 1240 */ 1241 if (amdgpu_is_atpx_hybrid()) { 1242 pci_ignore_hotplug(pdev); 1243 } else { 1244 pci_save_state(pdev); 1245 pci_disable_device(pdev); 1246 pci_ignore_hotplug(pdev); 1247 pci_set_power_state(pdev, PCI_D3cold); 1248 } 1249 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1250 } else if (amdgpu_device_supports_baco(drm_dev)) { 1251 amdgpu_device_baco_enter(drm_dev); 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int amdgpu_pmops_runtime_resume(struct device *dev) 1258 { 1259 struct pci_dev *pdev = to_pci_dev(dev); 1260 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1261 struct amdgpu_device *adev = drm_dev->dev_private; 1262 int ret; 1263 1264 if (!adev->runpm) 1265 return -EINVAL; 1266 1267 if (amdgpu_device_supports_boco(drm_dev)) { 1268 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1269 1270 /* Only need to handle PCI state in the driver for ATPX 1271 * PCI core handles it for _PR3. 1272 */ 1273 if (amdgpu_is_atpx_hybrid()) { 1274 pci_set_master(pdev); 1275 } else { 1276 pci_set_power_state(pdev, PCI_D0); 1277 pci_restore_state(pdev); 1278 ret = pci_enable_device(pdev); 1279 if (ret) 1280 return ret; 1281 pci_set_master(pdev); 1282 } 1283 } else if (amdgpu_device_supports_baco(drm_dev)) { 1284 amdgpu_device_baco_exit(drm_dev); 1285 } 1286 ret = amdgpu_device_resume(drm_dev, false); 1287 drm_kms_helper_poll_enable(drm_dev); 1288 if (amdgpu_device_supports_boco(drm_dev)) 1289 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1290 return 0; 1291 } 1292 1293 static int amdgpu_pmops_runtime_idle(struct device *dev) 1294 { 1295 struct drm_device *drm_dev = dev_get_drvdata(dev); 1296 struct amdgpu_device *adev = drm_dev->dev_private; 1297 struct drm_crtc *crtc; 1298 1299 if (!adev->runpm) { 1300 pm_runtime_forbid(dev); 1301 return -EBUSY; 1302 } 1303 1304 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1305 if (crtc->enabled) { 1306 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1307 return -EBUSY; 1308 } 1309 } 1310 1311 pm_runtime_mark_last_busy(dev); 1312 pm_runtime_autosuspend(dev); 1313 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1314 return 1; 1315 } 1316 1317 long amdgpu_drm_ioctl(struct file *filp, 1318 unsigned int cmd, unsigned long arg) 1319 { 1320 struct drm_file *file_priv = filp->private_data; 1321 struct drm_device *dev; 1322 long ret; 1323 dev = file_priv->minor->dev; 1324 ret = pm_runtime_get_sync(dev->dev); 1325 if (ret < 0) 1326 return ret; 1327 1328 ret = drm_ioctl(filp, cmd, arg); 1329 1330 pm_runtime_mark_last_busy(dev->dev); 1331 pm_runtime_put_autosuspend(dev->dev); 1332 return ret; 1333 } 1334 1335 static const struct dev_pm_ops amdgpu_pm_ops = { 1336 .suspend = amdgpu_pmops_suspend, 1337 .resume = amdgpu_pmops_resume, 1338 .freeze = amdgpu_pmops_freeze, 1339 .thaw = amdgpu_pmops_thaw, 1340 .poweroff = amdgpu_pmops_poweroff, 1341 .restore = amdgpu_pmops_restore, 1342 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1343 .runtime_resume = amdgpu_pmops_runtime_resume, 1344 .runtime_idle = amdgpu_pmops_runtime_idle, 1345 }; 1346 1347 static int amdgpu_flush(struct file *f, fl_owner_t id) 1348 { 1349 struct drm_file *file_priv = f->private_data; 1350 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1351 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1352 1353 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1354 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1355 1356 return timeout >= 0 ? 0 : timeout; 1357 } 1358 1359 static const struct file_operations amdgpu_driver_kms_fops = { 1360 .owner = THIS_MODULE, 1361 .open = drm_open, 1362 .flush = amdgpu_flush, 1363 .release = drm_release, 1364 .unlocked_ioctl = amdgpu_drm_ioctl, 1365 .mmap = amdgpu_mmap, 1366 .poll = drm_poll, 1367 .read = drm_read, 1368 #ifdef CONFIG_COMPAT 1369 .compat_ioctl = amdgpu_kms_compat_ioctl, 1370 #endif 1371 }; 1372 #endif /* __NetBSD__ */ 1373 1374 #ifdef __NetBSD__ 1375 /* XXX Kludge for the non-GEM GEM that amdgpu uses. */ 1376 static const struct uvm_pagerops amdgpu_gem_uvm_ops; 1377 #endif 1378 1379 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1380 { 1381 struct drm_file *file; 1382 1383 if (!filp) 1384 return -EINVAL; 1385 1386 #ifdef __NetBSD__ 1387 if (filp->f_ops != &drm_fileops) 1388 return -EINVAL; 1389 file = filp->f_data; 1390 if (file->minor->dev->driver != &kms_driver) 1391 return -EINVAL; 1392 #else 1393 if (filp->f_op != &amdgpu_driver_kms_fops) { 1394 return -EINVAL; 1395 } 1396 1397 file = filp->private_data; 1398 #endif 1399 *fpriv = file->driver_priv; 1400 return 0; 1401 } 1402 1403 static bool 1404 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1405 bool in_vblank_irq, int *vpos, int *hpos, 1406 ktime_t *stime, ktime_t *etime, 1407 const struct drm_display_mode *mode) 1408 { 1409 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1410 stime, etime, mode); 1411 } 1412 1413 static struct drm_driver kms_driver = { 1414 .driver_features = 1415 DRIVER_USE_AGP | DRIVER_ATOMIC | 1416 DRIVER_GEM | 1417 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1418 DRIVER_SYNCOBJ_TIMELINE, 1419 .load = amdgpu_driver_load_kms, 1420 .open = amdgpu_driver_open_kms, 1421 .postclose = amdgpu_driver_postclose_kms, 1422 .lastclose = amdgpu_driver_lastclose_kms, 1423 .unload = amdgpu_driver_unload_kms, 1424 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1425 .enable_vblank = amdgpu_enable_vblank_kms, 1426 .disable_vblank = amdgpu_disable_vblank_kms, 1427 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1428 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1429 .irq_handler = amdgpu_irq_handler, 1430 #ifdef __NetBSD__ 1431 .request_irq = drm_pci_request_irq, 1432 .free_irq = drm_pci_free_irq, 1433 #endif 1434 .ioctls = amdgpu_ioctls_kms, 1435 .gem_free_object_unlocked = amdgpu_gem_object_free, 1436 .gem_open_object = amdgpu_gem_object_open, 1437 .gem_close_object = amdgpu_gem_object_close, 1438 .dumb_create = amdgpu_mode_dumb_create, 1439 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1440 #ifdef __NetBSD__ 1441 .fops = NULL, 1442 .mmap_object = &amdgpu_mmap_object, 1443 .gem_uvm_ops = &amdgpu_gem_uvm_ops, 1444 #else 1445 .fops = &amdgpu_driver_kms_fops, 1446 #endif 1447 1448 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1449 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1450 .gem_prime_export = amdgpu_gem_prime_export, 1451 .gem_prime_import = amdgpu_gem_prime_import, 1452 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1453 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1454 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1455 1456 .name = DRIVER_NAME, 1457 .desc = DRIVER_DESC, 1458 .date = DRIVER_DATE, 1459 .major = KMS_DRIVER_MAJOR, 1460 .minor = KMS_DRIVER_MINOR, 1461 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1462 }; 1463 1464 #ifdef __NetBSD__ 1465 1466 struct drm_driver *const amdgpu_drm_driver = &kms_driver; 1467 const struct pci_device_id *const amdgpu_device_ids = pciidlist; 1468 const size_t amdgpu_n_device_ids = __arraycount(pciidlist); 1469 1470 #else /* __NetBSD__ */ 1471 1472 static struct pci_driver amdgpu_kms_pci_driver = { 1473 .name = DRIVER_NAME, 1474 .id_table = pciidlist, 1475 .probe = amdgpu_pci_probe, 1476 .remove = amdgpu_pci_remove, 1477 .shutdown = amdgpu_pci_shutdown, 1478 .driver.pm = &amdgpu_pm_ops, 1479 }; 1480 1481 1482 1483 static int __init amdgpu_init(void) 1484 { 1485 int r; 1486 1487 if (vgacon_text_force()) { 1488 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1489 return -EINVAL; 1490 } 1491 1492 r = amdgpu_sync_init(); 1493 if (r) 1494 goto error_sync; 1495 1496 r = amdgpu_fence_slab_init(); 1497 if (r) 1498 goto error_fence; 1499 1500 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1501 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1502 amdgpu_register_atpx_handler(); 1503 1504 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1505 amdgpu_amdkfd_init(); 1506 1507 /* let modprobe override vga console setting */ 1508 return pci_register_driver(&amdgpu_kms_pci_driver); 1509 1510 error_fence: 1511 amdgpu_sync_fini(); 1512 1513 error_sync: 1514 return r; 1515 } 1516 1517 static void __exit amdgpu_exit(void) 1518 { 1519 amdgpu_amdkfd_fini(); 1520 pci_unregister_driver(&amdgpu_kms_pci_driver); 1521 amdgpu_unregister_atpx_handler(); 1522 amdgpu_sync_fini(); 1523 amdgpu_fence_slab_fini(); 1524 mmu_notifier_synchronize(); 1525 } 1526 1527 module_init(amdgpu_init); 1528 module_exit(amdgpu_exit); 1529 1530 MODULE_AUTHOR(DRIVER_AUTHOR); 1531 MODULE_DESCRIPTION(DRIVER_DESC); 1532 MODULE_LICENSE("GPL and additional rights"); 1533 1534 #endif /* __NetBSD__ */ 1535
Indexes created Sun Sep 21 18:09:52 GMT 2025