| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| soc15.h | 43 u32 and_mask; member in struct:soc15_reg_golden
81 #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
82 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
|
| amdgpu_device.c | 703 u32 tmp, reg, and_mask, or_mask; local in function:amdgpu_device_program_register_sequence
711 and_mask = registers[i + 1];
714 if (and_mask == 0xffffffff) {
718 tmp &= ~and_mask;
720 tmp |= (or_mask & and_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_device.c | 212 u32 tmp, reg, and_mask, or_mask; local in function:radeon_program_register_sequence
220 and_mask = registers[i + 1];
223 if (and_mask == 0xffffffff) {
227 tmp &= ~and_mask;
|
| radeon_combios.c | 2897 uint32_t reg, val, and_mask, or_mask; local in function:radeon_combios_external_tmds_setup
2923 and_mask = RBIOS32(index);
2928 val = (val & and_mask) | or_mask;
2977 and_mask = RBIOS32(index);
2982 val = (val & and_mask) | or_mask;
2992 and_mask = RBIOS32(index);
2997 val = (val & and_mask) | or_mask;
3028 uint32_t val, and_mask, or_mask; local in function:combios_parse_mmio_table
3044 and_mask = RBIOS32(offset);
3049 tmp &= and_mask;
3108 uint32_t and_mask, or_mask; local in function:combios_parse_pll_table
[all...] |
