1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2006 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5211desc.h,v 1.1.1.1 2008/12/11 04:46:34 alc Exp $ 18 */ 19 #ifndef _DEV_ATH_AR5211DESC_H 20 #define _DEV_ATH_AR5211DESC_H 21 22 #include "ah_desc.h" 23 24 /* 25 * Defintions for the DMA descriptors used by the Atheros 26 * AR5211 and AR5110 Wireless Lan controller parts. 27 */ 28 29 /* DMA descriptors */ 30 struct ar5211_desc { 31 uint32_t ds_link; /* link pointer */ 32 uint32_t ds_data; /* data buffer pointer */ 33 uint32_t ds_ctl0; /* DMA control 0 */ 34 uint32_t ds_ctl1; /* DMA control 1 */ 35 uint32_t ds_status0; /* DMA status 0 */ 36 uint32_t ds_status1; /* DMA status 1 */ 37 } __packed; 38 #define AR5211DESC(_ds) ((struct ar5211_desc *)(_ds)) 39 #define AR5211DESC_CONST(_ds) ((const struct ar5211_desc *)(_ds)) 40 41 /* TX ds_ctl0 */ 42 #define AR_FrameLen 0x00000fff /* frame length */ 43 /* bits 12-17 are reserved */ 44 #define AR_XmitRate 0x003c0000 /* txrate */ 45 #define AR_XmitRate_S 18 46 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS enable */ 47 #define AR_VEOL 0x00800000 /* virtual end-of-list */ 48 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */ 49 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */ 50 #define AR_AntModeXmit_S 25 51 #define AR_TxInterReq 0x20000000 /* TX interrupt request */ 52 #define AR_EncryptKeyValid 0x40000000 /* EncryptKeyIdx is valid */ 53 /* bit 31 is reserved */ 54 55 /* TX ds_ctl1 */ 56 #define AR_BufLen 0x00000fff /* data buffer length */ 57 #define AR_More 0x00001000 /* more desc in this frame */ 58 #define AR_EncryptKeyIdx 0x000fe000 /* ecnrypt key table index */ 59 #define AR_EncryptKeyIdx_S 13 60 #define AR_FrmType 0x00700000 /* frame type indication */ 61 #define AR_FrmType_S 20 62 #define AR_Frm_Normal 0x00000000 /* normal frame */ 63 #define AR_Frm_ATIM 0x00100000 /* ATIM frame */ 64 #define AR_Frm_PSPOLL 0x00200000 /* PS poll frame */ 65 #define AR_Frm_Beacon 0x00300000 /* Beacon frame */ 66 #define AR_Frm_ProbeResp 0x00400000 /* no delay data */ 67 #define AR_NoAck 0x00800000 /* No ACK flag */ 68 /* bits 24-31 are reserved */ 69 70 /* RX ds_ctl1 */ 71 /* AR_BufLen 0x00000fff data buffer length */ 72 /* bit 12 is reserved */ 73 #define AR_RxInterReq 0x00002000 /* RX interrupt request */ 74 /* bits 14-31 are reserved */ 75 76 /* TX ds_status0 */ 77 #define AR_FrmXmitOK 0x00000001 /* TX success */ 78 #define AR_ExcessiveRetries 0x00000002 /* excessive retries */ 79 #define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */ 80 #define AR_Filtered 0x00000008 /* TX filter indication */ 81 /* NB: the spec has the Short+Long retry counts reversed */ 82 #define AR_LongRetryCnt 0x000000f0 /* long retry count */ 83 #define AR_LongRetryCnt_S 4 84 #define AR_ShortRetryCnt 0x00000f00 /* short retry count */ 85 #define AR_ShortRetryCnt_S 8 86 #define AR_VirtCollCnt 0x0000f000 /* virtual collision count */ 87 #define AR_VirtCollCnt_S 12 88 #define AR_SendTimestamp 0xffff0000 /* TX timestamp */ 89 #define AR_SendTimestamp_S 16 90 91 /* RX ds_status0 */ 92 #define AR_DataLen 0x00000fff /* RX data length */ 93 /* AR_More 0x00001000 more desc in this frame */ 94 /* bits 13-14 are reserved */ 95 #define AR_RcvRate 0x00078000 /* reception rate */ 96 #define AR_RcvRate_S 15 97 #define AR_RcvSigStrength 0x07f80000 /* receive signal strength */ 98 #define AR_RcvSigStrength_S 19 99 #define AR_RcvAntenna 0x38000000 /* receive antenaa */ 100 #define AR_RcvAntenna_S 27 101 /* bits 30-31 are reserved */ 102 103 /* TX ds_status1 */ 104 #define AR_Done 0x00000001 /* descripter complete */ 105 #define AR_SeqNum 0x00001ffe /* TX sequence number */ 106 #define AR_SeqNum_S 1 107 #define AR_AckSigStrength 0x001fe000 /* strength of ACK */ 108 #define AR_AckSigStrength_S 13 109 /* bits 21-31 are reserved */ 110 111 /* RX ds_status1 */ 112 /* AR_Done 0x00000001 descripter complete */ 113 #define AR_FrmRcvOK 0x00000002 /* frame reception success */ 114 #define AR_CRCErr 0x00000004 /* CRC error */ 115 /* bit 3 reserved */ 116 #define AR_DecryptCRCErr 0x00000010 /* Decryption CRC fiailure */ 117 #define AR_PHYErr 0x000000e0 /* PHY error */ 118 #define AR_PHYErr_S 5 119 #define AR_PHYErr_Underrun 0x00000000 /* Transmit underrun */ 120 #define AR_PHYErr_Tim 0x00000020 /* Timing error */ 121 #define AR_PHYErr_Par 0x00000040 /* Parity error */ 122 #define AR_PHYErr_Rate 0x00000060 /* Illegal rate */ 123 #define AR_PHYErr_Len 0x00000080 /* Illegal length */ 124 #define AR_PHYErr_Radar 0x000000a0 /* Radar detect */ 125 #define AR_PHYErr_Srv 0x000000c0 /* Illegal service */ 126 #define AR_PHYErr_TOR 0x000000e0 /* Transmit override receive */ 127 #define AR_KeyIdxValid 0x00000100 /* decryption key index valid */ 128 #define AR_KeyIdx 0x00007e00 /* Decryption key index */ 129 #define AR_KeyIdx_S 9 130 #define AR_RcvTimestamp 0x0fff8000 /* timestamp */ 131 #define AR_RcvTimestamp_S 15 132 #define AR_KeyCacheMiss 0x10000000 /* key cache miss indication */ 133 134 #endif /* _DEV_ATH_AR5211DESC_H_ */ 135
Indexes created Mon Sep 29 15:09:53 GMT 2025