Home | History | Annotate | Line # | Download | only in arm 
      1 /*	$NetBSD: cpufunc_asm_arm67.S,v 1.8 2022/10/20 06:58:38 skrll Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997,1998 Mark Brinicombe.
      5  * Copyright (c) 1997 Causality Limited
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *	This product includes software developed by Causality Limited.
     19  * 4. The name of Causality Limited may not be used to endorse or promote
     20  *    products derived from this software without specific prior written
     21  *    permission.
     22  *
     23  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
     24  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     26  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
     27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     33  * SUCH DAMAGE.
     34  *
     35  * ARM6/ARM7 assembly functions for CPU / MMU / TLB specific operations
     36  */
     37 
     38 #include "assym.h"
     39 #include <machine/asm.h>
     40 #include <arm/locore.h>
     41 
     42 /*
     43  * Functions to set the MMU Translation Table Base register
     44  *
     45  * We need to clean and flush the cache as it uses virtual
     46  * addresses that are about to change.
     47  */
     48 ENTRY(arm67_setttb)
     49 	cmp	r1, #0
     50 
     51 	/* wbinv entire L1 I$ and D$ caches */
     52 	movne	r2, #0
     53 	mcrne	p15, 0, r2, c7, c0, 0
     54 
     55 	/* Write the TTB */
     56 	mcr	p15, 0, r0, c2, c0, 0
     57 
     58 	/* If we have updated the TTB we must flush the TLB */
     59 	mcrne	p15, 0, r0, c5, c0, 0
     60 
     61 	/* For good measure we will flush the IDC as well */
     62 	mcrne	p15, 0, r0, c7, c0, 0
     63 
     64 	/* Make sure that pipeline is emptied */
     65 	mov	r0, r0
     66 	mov	r0, r0
     67 
     68 	RET
     69 
     70 /*
     71  * TLB functions
     72  */
     73 ENTRY(arm67_tlb_flush)
     74 	mcr	p15, 0, r0, c5, c0, 0
     75 	mov	pc, lr
     76 
     77 ENTRY(arm67_tlb_purge)
     78 	mcr	p15, 0, r0, c6, c0, 0
     79 	mov	pc, lr
     80 
     81 /*
     82  * Cache functions
     83  */
     84 ENTRY(arm67_cache_flush)
     85 	mcr	p15, 0, r0, c7, c0, 0
     86 	mov	pc, lr
     87 
     88 /*
     89  * Context switch.
     90  *
     91  * These are the CPU-specific parts of the context switcher cpu_switch()
     92  * These functions actually perform the TTB reload.
     93  */
     94 ENTRY(arm67_context_switch)
     95 	/* For good measure we will flush the IDC as well */
     96 	mcr	p15, 0, r0, c7, c0, 0	/* flush cache */
     97 
     98 	/* Write the TTB */
     99 	mcr	p15, 0, r0, c2, c0, 0
    100 
    101 	/* If we have updated the TTB we must flush the TLB */
    102 	mcr	p15, 0, r0, c5, c0, 0
    103 
    104 #if 0
    105 	/* For good measure we will flush the IDC as well */
    106 	mcr	p15, 0, r0, c7, c0, 0	/* flush cache */
    107 #endif
    108 
    109 	/* Make sure that pipeline is emptied */
    110 	mov	r0, r0
    111 	mov	r0, r0
    112 	mov	pc, lr
    113