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      1 /*	$NetBSD: cpufunc_asm_arm7tdmi.S,v 1.8 2022/10/20 06:58:38 skrll Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001 John Fremlin
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Causality Limited.
     18  * 4. The name of Causality Limited may not be used to endorse or promote
     19  *    products derived from this software without specific prior written
     20  *    permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
     23  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     25  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
     26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  * ARM7TDMI assembly functions for CPU / MMU / TLB specific operations
     35  */
     36 
     37 #include "assym.h"
     38 #include <machine/asm.h>
     39 #include <arm/locore.h>
     40 
     41 /*
     42  * Functions to set the MMU Translation Table Base register
     43  *
     44  * We need to clean and flush the cache as it uses virtual
     45  * addresses that are about to change.
     46  */
     47 
     48 /*
     49  * Context switch.
     50  *
     51  * These are the CPU-specific parts of the context switcher cpu_switch()
     52  * These functions actually perform the TTB reload.
     53  */
     54 ENTRY(arm7tdmi_setttb)
     55 	mov	r3, lr		/* ditto with lr */
     56 	mov	r2, r1		/* store the flush flag in a safe place */
     57 	mov	r1, r0		/* store the TTB in a safe place */
     58 
     59 	cmp	r2, #0
     60 	blne	_C_LABEL(arm7tdmi_cache_flushID)
     61 
     62 	/* Write the TTB */
     63 	mcr	p15, 0, r1, c2, c0, 0
     64 
     65 	cmp	r2, #0		@ do we need to flush
     66 	moveq	pc, r3		@   if not, return
     67 
     68 	/* If we have updated the TTB we must flush the TLB */
     69 	bl	_C_LABEL(arm7tdmi_tlb_flushID)
     70 
     71 	/* For good measure we will flush the IDC as well */
     72 	bl	_C_LABEL(arm7tdmi_cache_flushID)
     73 
     74 	mov	pc, r3
     75 END(arm7tdmi_setttb)
     76 STRONG_ALIAS(arm7tdmi_context_switch, arm7tdmi_setttb)
     77 
     78 /*
     79  * TLB functions
     80  */
     81 ENTRY(arm7tdmi_tlb_flushID)
     82 	mov	r0, #0
     83 	mcr	p15, 0, r0, c8, c7, 0
     84 	mov	pc, lr
     85 END(arm7tdmi_tlb_flushID)
     86 
     87 ENTRY(arm7tdmi_tlb_flushID_SE)
     88 	mcr	p15, 0, r0, c8, c7, 1
     89 #if PAGE_SIZE == 2 * L2_S_SIZE
     90 	add	r0, r0, #L2_S_SIZE
     91 	mcr	p15, 0, r0, c8, c7, 1
     92 #endif
     93 	mov	pc, lr
     94 END(arm7tdmi_tlb_flushID_SE)
     95 
     96 /*
     97  * Cache functions
     98  */
     99 ENTRY(arm7tdmi_cache_flushID)
    100 	mov	r0, #0
    101 
    102 	mcr	p15, 0, r0, c7, c7, 0
    103 
    104 	/* Make sure that the pipeline is emptied */
    105 	mov	r0, r0
    106 	mov	r0, r0
    107 
    108 	mov	pc, lr
    109 END(arm7tdmi_cache_flushID)
    110