1 /* $NetBSD: disasm_decode.c,v 1.2 2016/08/05 16:45:50 scole Exp $ */ 2 3 /*- 4 * Copyright (c) 2000-2006 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* __FBSDID("$FreeBSD: releng/10.1/sys/ia64/disasm/disasm_decode.c 159916 2006-06-24 19:21:11Z marcel $"); */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <ia64/disasm/disasm_int.h> 36 #include <ia64/disasm/disasm.h> 37 38 /* 39 * Template names. 40 */ 41 static const char *asm_templname[] = { 42 "MII", "MII;", "MI;I", "MI;I;", "MLX", "MLX;", 0, 0, 43 "MMI", "MMI;", "M;MI", "M;MI;", "MFI", "MFI;", "MMF", "MMF;", 44 "MIB", "MIB;", "MBB", "MBB;", 0, 0, "BBB", "BBB;", 45 "MMB", "MMB;", 0, 0, "MFB", "MFB;", 0, 0 46 }; 47 48 /* 49 * Decode A-unit instructions. 50 */ 51 static int 52 asm_decodeA(uint64_t bits, struct asm_bundle *b, int slot) 53 { 54 enum asm_fmt fmt; 55 enum asm_op op; 56 57 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 58 switch((int)OPCODE(bits)) { 59 case 0x8: 60 switch (FIELD(bits, 34, 2)) { /* x2a */ 61 case 0x0: 62 if (FIELD(bits, 33, 1) == 0) { /* ve */ 63 switch (FIELD(bits, 29, 4)) { /* x4 */ 64 case 0x0: 65 if (FIELD(bits, 27, 2) <= 1) /* x2b */ 66 op = ASM_OP_ADD, 67 fmt = ASM_FMT_A1; 68 break; 69 case 0x1: 70 if (FIELD(bits, 27, 2) <= 1) /* x2b */ 71 op = ASM_OP_SUB, 72 fmt = ASM_FMT_A1; 73 break; 74 case 0x2: 75 if (FIELD(bits, 27, 2) == 0) /* x2b */ 76 op = ASM_OP_ADDP4, 77 fmt = ASM_FMT_A1; 78 break; 79 case 0x3: 80 switch (FIELD(bits, 27, 2)) { /* x2b */ 81 case 0x0: 82 op = ASM_OP_AND, 83 fmt = ASM_FMT_A1; 84 break; 85 case 0x1: 86 op = ASM_OP_ANDCM, 87 fmt = ASM_FMT_A1; 88 break; 89 case 0x2: 90 op = ASM_OP_OR, 91 fmt = ASM_FMT_A1; 92 break; 93 case 0x3: 94 op = ASM_OP_XOR, 95 fmt = ASM_FMT_A1; 96 break; 97 } 98 break; 99 case 0xB: 100 switch (FIELD(bits, 27, 2)) { /* x2b */ 101 case 0x0: 102 op = ASM_OP_AND, 103 fmt = ASM_FMT_A3; 104 break; 105 case 0x1: 106 op = ASM_OP_ANDCM, 107 fmt = ASM_FMT_A3; 108 break; 109 case 0x2: 110 op = ASM_OP_OR, 111 fmt = ASM_FMT_A3; 112 break; 113 case 0x3: 114 op = ASM_OP_XOR, 115 fmt = ASM_FMT_A3; 116 break; 117 } 118 break; 119 case 0x4: 120 op = ASM_OP_SHLADD, fmt = ASM_FMT_A2; 121 break; 122 case 0x6: 123 op = ASM_OP_SHLADDP4, fmt = ASM_FMT_A2; 124 break; 125 case 0x9: 126 if (FIELD(bits, 27, 2) == 1) /* x2b */ 127 op = ASM_OP_SUB, 128 fmt = ASM_FMT_A3; 129 break; 130 } 131 } 132 break; 133 case 0x1: 134 switch (FIELD(bits, 29, 8)) { /* za + x2a + zb + x4 */ 135 case 0x20: 136 switch (FIELD(bits, 27, 2)) { /* x2b */ 137 case 0x0: 138 op = ASM_OP_PADD1_, fmt = ASM_FMT_A9; 139 break; 140 case 0x1: 141 op = ASM_OP_PADD1_SSS, 142 fmt = ASM_FMT_A9; 143 break; 144 case 0x2: 145 op = ASM_OP_PADD1_UUU, 146 fmt = ASM_FMT_A9; 147 break; 148 case 0x3: 149 op = ASM_OP_PADD1_UUS, 150 fmt = ASM_FMT_A9; 151 break; 152 } 153 break; 154 case 0x21: 155 switch (FIELD(bits, 27, 2)) { /* x2b */ 156 case 0x0: 157 op = ASM_OP_PSUB1_, fmt = ASM_FMT_A9; 158 break; 159 case 0x1: 160 op = ASM_OP_PSUB1_SSS, 161 fmt = ASM_FMT_A9; 162 break; 163 case 0x2: 164 op = ASM_OP_PSUB1_UUU, 165 fmt = ASM_FMT_A9; 166 break; 167 case 0x3: 168 op = ASM_OP_PSUB1_UUS, 169 fmt = ASM_FMT_A9; 170 break; 171 } 172 break; 173 case 0x22: 174 switch (FIELD(bits, 27, 2)) { /* x2b */ 175 case 0x2: 176 op = ASM_OP_PAVG1_, fmt = ASM_FMT_A9; 177 break; 178 case 0x3: 179 op = ASM_OP_PAVG1_RAZ, 180 fmt = ASM_FMT_A9; 181 break; 182 } 183 break; 184 case 0x23: 185 if (FIELD(bits, 27, 2) == 2) /* x2b */ 186 op = ASM_OP_PAVGSUB1, fmt = ASM_FMT_A9; 187 break; 188 case 0x29: 189 switch (FIELD(bits, 27, 2)) { /* x2b */ 190 case 0x0: 191 op = ASM_OP_PCMP1_EQ, fmt = ASM_FMT_A9; 192 break; 193 case 0x1: 194 op = ASM_OP_PCMP1_GT, fmt = ASM_FMT_A9; 195 break; 196 } 197 break; 198 case 0x30: 199 switch (FIELD(bits, 27, 2)) { /* x2b */ 200 case 0x0: 201 op = ASM_OP_PADD2_, fmt = ASM_FMT_A9; 202 break; 203 case 0x1: 204 op = ASM_OP_PADD2_SSS, 205 fmt = ASM_FMT_A9; 206 break; 207 case 0x2: 208 op = ASM_OP_PADD2_UUU, 209 fmt = ASM_FMT_A9; 210 break; 211 case 0x3: 212 op = ASM_OP_PADD2_UUS, 213 fmt = ASM_FMT_A9; 214 break; 215 } 216 break; 217 case 0x31: 218 switch (FIELD(bits, 27, 2)) { /* x2b */ 219 case 0x0: 220 op = ASM_OP_PSUB2_, fmt = ASM_FMT_A9; 221 break; 222 case 0x1: 223 op = ASM_OP_PSUB2_SSS, 224 fmt = ASM_FMT_A9; 225 break; 226 case 0x2: 227 op = ASM_OP_PSUB2_UUU, 228 fmt = ASM_FMT_A9; 229 break; 230 case 0x3: 231 op = ASM_OP_PSUB2_UUS, 232 fmt = ASM_FMT_A9; 233 break; 234 } 235 break; 236 case 0x32: 237 switch (FIELD(bits, 27, 2)) { /* x2b */ 238 case 0x2: 239 op = ASM_OP_PAVG2_, fmt = ASM_FMT_A9; 240 break; 241 case 0x3: 242 op = ASM_OP_PAVG2_RAZ, 243 fmt = ASM_FMT_A9; 244 break; 245 } 246 break; 247 case 0x33: 248 if (FIELD(bits, 27, 2) == 2) /* x2b */ 249 op = ASM_OP_PAVGSUB2, fmt = ASM_FMT_A9; 250 break; 251 case 0x34: 252 op = ASM_OP_PSHLADD2, fmt = ASM_FMT_A10; 253 break; 254 case 0x36: 255 op = ASM_OP_PSHRADD2, fmt = ASM_FMT_A10; 256 break; 257 case 0x39: 258 switch (FIELD(bits, 27, 2)) { /* x2b */ 259 case 0x0: 260 op = ASM_OP_PCMP2_EQ, fmt = ASM_FMT_A9; 261 break; 262 case 0x1: 263 op = ASM_OP_PCMP2_GT, fmt = ASM_FMT_A9; 264 break; 265 } 266 break; 267 case 0xA0: 268 if (FIELD(bits, 27, 2) == 0) /* x2b */ 269 op = ASM_OP_PADD4, fmt = ASM_FMT_A9; 270 break; 271 case 0xA1: 272 if (FIELD(bits, 27, 2) == 0) /* x2b */ 273 op = ASM_OP_PSUB4, fmt = ASM_FMT_A9; 274 break; 275 case 0xA9: 276 switch (FIELD(bits, 27, 2)) { /* x2b */ 277 case 0x0: 278 op = ASM_OP_PCMP4_EQ, fmt = ASM_FMT_A9; 279 break; 280 case 0x1: 281 op = ASM_OP_PCMP4_GT, fmt = ASM_FMT_A9; 282 break; 283 } 284 break; 285 } 286 break; 287 case 0x2: 288 if (FIELD(bits, 33, 1) == 0) /* ve */ 289 op = ASM_OP_ADDS, fmt = ASM_FMT_A4; 290 break; 291 case 0x3: 292 if (FIELD(bits, 33, 1) == 0) /* ve */ 293 op = ASM_OP_ADDP4, fmt = ASM_FMT_A4; 294 break; 295 } 296 break; 297 case 0x9: 298 op = ASM_OP_ADDL, fmt = ASM_FMT_A5; 299 break; 300 case 0xC: case 0xD: case 0xE: 301 if (FIELD(bits, 12, 1) == 0) { /* c */ 302 switch (FIELD(bits, 33, 8)) { /* maj + tb + x2 + ta */ 303 case 0xC0: 304 op = ASM_OP_CMP_LT, fmt = ASM_FMT_A6; 305 break; 306 case 0xC1: 307 op = ASM_OP_CMP_EQ_AND, fmt = ASM_FMT_A6; 308 break; 309 case 0xC2: 310 op = ASM_OP_CMP4_LT, fmt = ASM_FMT_A6; 311 break; 312 case 0xC3: 313 op = ASM_OP_CMP4_EQ_AND, fmt = ASM_FMT_A6; 314 break; 315 case 0xC4: case 0xCC: 316 op = ASM_OP_CMP_LT, fmt = ASM_FMT_A8; 317 break; 318 case 0xC5: case 0xCD: 319 op = ASM_OP_CMP_EQ_AND, fmt = ASM_FMT_A8; 320 break; 321 case 0xC6: case 0xCE: 322 op = ASM_OP_CMP4_LT, fmt = ASM_FMT_A8; 323 break; 324 case 0xC7: case 0xCF: 325 op = ASM_OP_CMP4_EQ_AND, fmt = ASM_FMT_A8; 326 break; 327 case 0xC8: 328 op = ASM_OP_CMP_GT_AND, fmt = ASM_FMT_A7; 329 break; 330 case 0xC9: 331 op = ASM_OP_CMP_GE_AND, fmt = ASM_FMT_A7; 332 break; 333 case 0xCA: 334 op = ASM_OP_CMP4_GT_AND, fmt = ASM_FMT_A7; 335 break; 336 case 0xCB: 337 op = ASM_OP_CMP4_GE_AND, fmt = ASM_FMT_A7; 338 break; 339 case 0xD0: 340 op = ASM_OP_CMP_LTU, fmt = ASM_FMT_A6; 341 break; 342 case 0xD1: 343 op = ASM_OP_CMP_EQ_OR, fmt = ASM_FMT_A6; 344 break; 345 case 0xD2: 346 op = ASM_OP_CMP4_LTU, fmt = ASM_FMT_A6; 347 break; 348 case 0xD3: 349 op = ASM_OP_CMP4_EQ_OR, fmt = ASM_FMT_A6; 350 break; 351 case 0xD4: case 0xDC: 352 op = ASM_OP_CMP_LTU, fmt = ASM_FMT_A8; 353 break; 354 case 0xD5: case 0xDD: 355 op = ASM_OP_CMP_EQ_OR, fmt = ASM_FMT_A8; 356 break; 357 case 0xD6: case 0xDE: 358 op = ASM_OP_CMP4_LTU, fmt = ASM_FMT_A8; 359 break; 360 case 0xD7: case 0xDF: 361 op = ASM_OP_CMP4_EQ_OR, fmt = ASM_FMT_A8; 362 break; 363 case 0xD8: 364 op = ASM_OP_CMP_GT_OR, fmt = ASM_FMT_A7; 365 break; 366 case 0xD9: 367 op = ASM_OP_CMP_GE_OR, fmt = ASM_FMT_A7; 368 break; 369 case 0xDA: 370 op = ASM_OP_CMP4_GT_OR, fmt = ASM_FMT_A7; 371 break; 372 case 0xDB: 373 op = ASM_OP_CMP4_GE_OR, fmt = ASM_FMT_A7; 374 break; 375 case 0xE0: 376 op = ASM_OP_CMP_EQ, fmt = ASM_FMT_A6; 377 break; 378 case 0xE1: 379 op = ASM_OP_CMP_EQ_OR_ANDCM, fmt = ASM_FMT_A6; 380 break; 381 case 0xE2: 382 op = ASM_OP_CMP4_EQ, fmt = ASM_FMT_A6; 383 break; 384 case 0xE3: 385 op = ASM_OP_CMP4_EQ_OR_ANDCM, fmt = ASM_FMT_A6; 386 break; 387 case 0xE4: case 0xEC: 388 op = ASM_OP_CMP_EQ, fmt = ASM_FMT_A8; 389 break; 390 case 0xE5: case 0xED: 391 op = ASM_OP_CMP_EQ_OR_ANDCM, fmt = ASM_FMT_A8; 392 break; 393 case 0xE6: case 0xEE: 394 op = ASM_OP_CMP4_EQ, fmt = ASM_FMT_A8; 395 break; 396 case 0xE7: case 0xEF: 397 op = ASM_OP_CMP4_EQ_OR_ANDCM, fmt = ASM_FMT_A8; 398 break; 399 case 0xE8: 400 op = ASM_OP_CMP_GT_OR_ANDCM, fmt = ASM_FMT_A7; 401 break; 402 case 0xE9: 403 op = ASM_OP_CMP_GE_OR_ANDCM, fmt = ASM_FMT_A7; 404 break; 405 case 0xEA: 406 op = ASM_OP_CMP4_GT_OR_ANDCM, fmt = ASM_FMT_A7; 407 break; 408 case 0xEB: 409 op = ASM_OP_CMP4_GE_OR_ANDCM, fmt = ASM_FMT_A7; 410 break; 411 } 412 } else { 413 switch (FIELD(bits, 33, 8)) { /* maj + tb + x2 + ta */ 414 case 0xC0: 415 op = ASM_OP_CMP_LT_UNC, fmt = ASM_FMT_A6; 416 break; 417 case 0xC1: 418 op = ASM_OP_CMP_NE_AND, fmt = ASM_FMT_A6; 419 break; 420 case 0xC2: 421 op = ASM_OP_CMP4_LT_UNC, fmt = ASM_FMT_A6; 422 break; 423 case 0xC3: 424 op = ASM_OP_CMP4_NE_AND, fmt = ASM_FMT_A6; 425 break; 426 case 0xC4: case 0xCC: 427 op = ASM_OP_CMP_LT_UNC, fmt = ASM_FMT_A8; 428 break; 429 case 0xC5: case 0xCD: 430 op = ASM_OP_CMP_NE_AND, fmt = ASM_FMT_A8; 431 break; 432 case 0xC6: case 0xCE: 433 op = ASM_OP_CMP4_LT_UNC, fmt = ASM_FMT_A8; 434 break; 435 case 0xC7: case 0xCF: 436 op = ASM_OP_CMP4_NE_AND, fmt = ASM_FMT_A8; 437 break; 438 case 0xC8: 439 op = ASM_OP_CMP_LE_AND, fmt = ASM_FMT_A7; 440 break; 441 case 0xC9: 442 op = ASM_OP_CMP_LT_AND, fmt = ASM_FMT_A7; 443 break; 444 case 0xCA: 445 op = ASM_OP_CMP4_LE_AND, fmt = ASM_FMT_A7; 446 break; 447 case 0xCB: 448 op = ASM_OP_CMP4_LT_AND, fmt = ASM_FMT_A7; 449 break; 450 case 0xD0: 451 op = ASM_OP_CMP_LTU_UNC, fmt = ASM_FMT_A6; 452 break; 453 case 0xD1: 454 op = ASM_OP_CMP_NE_OR, fmt = ASM_FMT_A6; 455 break; 456 case 0xD2: 457 op = ASM_OP_CMP4_LTU_UNC, fmt = ASM_FMT_A6; 458 break; 459 case 0xD3: 460 op = ASM_OP_CMP4_NE_OR, fmt = ASM_FMT_A6; 461 break; 462 case 0xD4: case 0xDC: 463 op = ASM_OP_CMP_LTU_UNC, fmt = ASM_FMT_A8; 464 break; 465 case 0xD5: case 0xDD: 466 op = ASM_OP_CMP_NE_OR, fmt = ASM_FMT_A8; 467 break; 468 case 0xD6: case 0xDE: 469 op = ASM_OP_CMP4_LTU_UNC, fmt = ASM_FMT_A8; 470 break; 471 case 0xD7: case 0xDF: 472 op = ASM_OP_CMP4_NE_OR, fmt = ASM_FMT_A8; 473 break; 474 case 0xD8: 475 op = ASM_OP_CMP_LE_OR, fmt = ASM_FMT_A7; 476 break; 477 case 0xD9: 478 op = ASM_OP_CMP_LT_OR, fmt = ASM_FMT_A7; 479 break; 480 case 0xDA: 481 op = ASM_OP_CMP4_LE_OR, fmt = ASM_FMT_A7; 482 break; 483 case 0xDB: 484 op = ASM_OP_CMP4_LT_OR, fmt = ASM_FMT_A7; 485 break; 486 case 0xE0: 487 op = ASM_OP_CMP_EQ_UNC, fmt = ASM_FMT_A6; 488 break; 489 case 0xE1: 490 op = ASM_OP_CMP_NE_OR_ANDCM, fmt = ASM_FMT_A6; 491 break; 492 case 0xE2: 493 op = ASM_OP_CMP4_EQ_UNC, fmt = ASM_FMT_A6; 494 break; 495 case 0xE3: 496 op = ASM_OP_CMP4_NE_OR_ANDCM, fmt = ASM_FMT_A6; 497 break; 498 case 0xE4: case 0xEC: 499 op = ASM_OP_CMP_EQ_UNC, fmt = ASM_FMT_A8; 500 break; 501 case 0xE5: case 0xED: 502 op = ASM_OP_CMP_NE_OR_ANDCM, fmt = ASM_FMT_A8; 503 break; 504 case 0xE6: case 0xEE: 505 op = ASM_OP_CMP4_EQ_UNC, fmt = ASM_FMT_A8; 506 break; 507 case 0xE7: case 0xEF: 508 op = ASM_OP_CMP4_NE_OR_ANDCM, fmt = ASM_FMT_A8; 509 break; 510 case 0xE8: 511 op = ASM_OP_CMP_LE_OR_ANDCM, fmt = ASM_FMT_A7; 512 break; 513 case 0xE9: 514 op = ASM_OP_CMP_LT_OR_ANDCM, fmt = ASM_FMT_A7; 515 break; 516 case 0xEA: 517 op = ASM_OP_CMP4_LE_OR_ANDCM, fmt = ASM_FMT_A7; 518 break; 519 case 0xEB: 520 op = ASM_OP_CMP4_LT_OR_ANDCM, fmt = ASM_FMT_A7; 521 break; 522 } 523 } 524 break; 525 } 526 527 if (op != ASM_OP_NONE) 528 return (asm_extract(op, fmt, bits, b, slot)); 529 return (0); 530 } 531 532 /* 533 * Decode B-unit instructions. 534 */ 535 static int 536 asm_decodeB(uint64_t ip, struct asm_bundle *b, int slot) 537 { 538 uint64_t bits; 539 enum asm_fmt fmt; 540 enum asm_op op; 541 542 bits = SLOT(ip, slot); 543 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 544 545 switch((int)OPCODE(bits)) { 546 case 0x0: 547 switch (FIELD(bits, 27, 6)) { /* x6 */ 548 case 0x0: 549 op = ASM_OP_BREAK_B, fmt = ASM_FMT_B9; 550 break; 551 case 0x2: 552 op = ASM_OP_COVER, fmt = ASM_FMT_B8; 553 break; 554 case 0x4: 555 op = ASM_OP_CLRRRB_, fmt = ASM_FMT_B8; 556 break; 557 case 0x5: 558 op = ASM_OP_CLRRRB_PR, fmt = ASM_FMT_B8; 559 break; 560 case 0x8: 561 op = ASM_OP_RFI, fmt = ASM_FMT_B8; 562 break; 563 case 0xC: 564 op = ASM_OP_BSW_0, fmt = ASM_FMT_B8; 565 break; 566 case 0xD: 567 op = ASM_OP_BSW_1, fmt = ASM_FMT_B8; 568 break; 569 case 0x10: 570 op = ASM_OP_EPC, fmt = ASM_FMT_B8; 571 break; 572 case 0x18: 573 op = ASM_OP_VMSW_0, fmt = ASM_FMT_B8; 574 break; 575 case 0x19: 576 op = ASM_OP_VMSW_1, fmt = ASM_FMT_B8; 577 break; 578 case 0x20: 579 switch (FIELD(bits, 6, 3)) { /* btype */ 580 case 0x0: 581 op = ASM_OP_BR_COND, fmt = ASM_FMT_B4; 582 break; 583 case 0x1: 584 op = ASM_OP_BR_IA, fmt = ASM_FMT_B4; 585 break; 586 } 587 break; 588 case 0x21: 589 if (FIELD(bits, 6, 3) == 4) /* btype */ 590 op = ASM_OP_BR_RET, fmt = ASM_FMT_B4; 591 break; 592 } 593 break; 594 case 0x1: 595 op = ASM_OP_BR_CALL, fmt = ASM_FMT_B5; 596 break; 597 case 0x2: 598 switch (FIELD(bits, 27, 6)) { /* x6 */ 599 case 0x0: 600 op = ASM_OP_NOP_B, fmt = ASM_FMT_B9; 601 break; 602 case 0x1: 603 op = ASM_OP_HINT_B, fmt = ASM_FMT_B9; 604 break; 605 case 0x10: 606 op = ASM_OP_BRP_, fmt = ASM_FMT_B7; 607 break; 608 case 0x11: 609 op = ASM_OP_BRP_RET, fmt = ASM_FMT_B7; 610 break; 611 } 612 break; 613 case 0x4: 614 switch (FIELD(bits, 6, 3)) { /* btype */ 615 case 0x0: 616 op = ASM_OP_BR_COND, fmt = ASM_FMT_B1; 617 break; 618 case 0x2: 619 op = ASM_OP_BR_WEXIT, fmt = ASM_FMT_B1; 620 break; 621 case 0x3: 622 op = ASM_OP_BR_WTOP, fmt = ASM_FMT_B1; 623 break; 624 case 0x5: 625 op = ASM_OP_BR_CLOOP, fmt = ASM_FMT_B2; 626 break; 627 case 0x6: 628 op = ASM_OP_BR_CEXIT, fmt = ASM_FMT_B2; 629 break; 630 case 0x7: 631 op = ASM_OP_BR_CTOP, fmt = ASM_FMT_B2; 632 break; 633 } 634 break; 635 case 0x5: 636 op = ASM_OP_BR_CALL, fmt = ASM_FMT_B3; 637 break; 638 case 0x7: 639 op = ASM_OP_BRP_, fmt = ASM_FMT_B6; 640 break; 641 } 642 643 if (op != ASM_OP_NONE) 644 return (asm_extract(op, fmt, bits, b, slot)); 645 return (0); 646 } 647 648 /* 649 * Decode F-unit instructions. 650 */ 651 static int 652 asm_decodeF(uint64_t ip, struct asm_bundle *b, int slot) 653 { 654 uint64_t bits; 655 enum asm_fmt fmt; 656 enum asm_op op; 657 658 bits = SLOT(ip, slot); 659 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 660 661 switch((int)OPCODE(bits)) { 662 case 0x0: 663 if (FIELD(bits, 33, 1) == 0) { /* x */ 664 switch (FIELD(bits, 27, 6)) { /* x6 */ 665 case 0x0: 666 op = ASM_OP_BREAK_F, fmt = ASM_FMT_F15; 667 break; 668 case 0x1: 669 if (FIELD(bits, 26, 1) == 0) /* y */ 670 op = ASM_OP_NOP_F, fmt = ASM_FMT_F16; 671 else 672 op = ASM_OP_HINT_F, fmt = ASM_FMT_F16; 673 break; 674 case 0x4: 675 op = ASM_OP_FSETC, fmt = ASM_FMT_F12; 676 break; 677 case 0x5: 678 op = ASM_OP_FCLRF, fmt = ASM_FMT_F13; 679 break; 680 case 0x8: 681 op = ASM_OP_FCHKF, fmt = ASM_FMT_F14; 682 break; 683 case 0x10: 684 op = ASM_OP_FMERGE_S, fmt = ASM_FMT_F9; 685 break; 686 case 0x11: 687 op = ASM_OP_FMERGE_NS, fmt = ASM_FMT_F9; 688 break; 689 case 0x12: 690 op = ASM_OP_FMERGE_SE, fmt = ASM_FMT_F9; 691 break; 692 case 0x14: 693 op = ASM_OP_FMIN, fmt = ASM_FMT_F8; 694 break; 695 case 0x15: 696 op = ASM_OP_FMAX, fmt = ASM_FMT_F8; 697 break; 698 case 0x16: 699 op = ASM_OP_FAMIN, fmt = ASM_FMT_F8; 700 break; 701 case 0x17: 702 op = ASM_OP_FAMAX, fmt = ASM_FMT_F8; 703 break; 704 case 0x18: 705 op = ASM_OP_FCVT_FX, fmt = ASM_FMT_F10; 706 break; 707 case 0x19: 708 op = ASM_OP_FCVT_FXU, fmt = ASM_FMT_F10; 709 break; 710 case 0x1A: 711 op = ASM_OP_FCVT_FX_TRUNC, fmt = ASM_FMT_F10; 712 break; 713 case 0x1B: 714 op = ASM_OP_FCVT_FXU_TRUNC, fmt = ASM_FMT_F10; 715 break; 716 case 0x1C: 717 op = ASM_OP_FCVT_XF, fmt = ASM_FMT_F11; 718 break; 719 case 0x28: 720 op = ASM_OP_FPACK, fmt = ASM_FMT_F9; 721 break; 722 case 0x2C: 723 op = ASM_OP_FAND, fmt = ASM_FMT_F9; 724 break; 725 case 0x2D: 726 op = ASM_OP_FANDCM, fmt = ASM_FMT_F9; 727 break; 728 case 0x2E: 729 op = ASM_OP_FOR, fmt = ASM_FMT_F9; 730 break; 731 case 0x2F: 732 op = ASM_OP_FXOR, fmt = ASM_FMT_F9; 733 break; 734 case 0x34: 735 op = ASM_OP_FSWAP_, fmt = ASM_FMT_F9; 736 break; 737 case 0x35: 738 op = ASM_OP_FSWAP_NL, fmt = ASM_FMT_F9; 739 break; 740 case 0x36: 741 op = ASM_OP_FSWAP_NR, fmt = ASM_FMT_F9; 742 break; 743 case 0x39: 744 op = ASM_OP_FMIX_LR, fmt = ASM_FMT_F9; 745 break; 746 case 0x3A: 747 op = ASM_OP_FMIX_R, fmt = ASM_FMT_F9; 748 break; 749 case 0x3B: 750 op = ASM_OP_FMIX_L, fmt = ASM_FMT_F9; 751 break; 752 case 0x3C: 753 op = ASM_OP_FSXT_R, fmt = ASM_FMT_F9; 754 break; 755 case 0x3D: 756 op = ASM_OP_FSXT_L, fmt = ASM_FMT_F9; 757 break; 758 } 759 } else { 760 if (FIELD(bits, 36, 1) == 0) /* q */ 761 op = ASM_OP_FRCPA, fmt = ASM_FMT_F6; 762 else 763 op = ASM_OP_FRSQRTA, fmt = ASM_FMT_F7; 764 } 765 break; 766 case 0x1: 767 if (FIELD(bits, 33, 1) == 0) { /* x */ 768 switch (FIELD(bits, 27, 6)) { /* x6 */ 769 case 0x10: 770 op = ASM_OP_FPMERGE_S, fmt = ASM_FMT_F9; 771 break; 772 case 0x11: 773 op = ASM_OP_FPMERGE_NS, fmt = ASM_FMT_F9; 774 break; 775 case 0x12: 776 op = ASM_OP_FPMERGE_SE, fmt = ASM_FMT_F9; 777 break; 778 case 0x14: 779 op = ASM_OP_FPMIN, fmt = ASM_FMT_F8; 780 break; 781 case 0x15: 782 op = ASM_OP_FPMAX, fmt = ASM_FMT_F8; 783 break; 784 case 0x16: 785 op = ASM_OP_FPAMIN, fmt = ASM_FMT_F8; 786 break; 787 case 0x17: 788 op = ASM_OP_FPAMAX, fmt = ASM_FMT_F8; 789 break; 790 case 0x18: 791 op = ASM_OP_FPCVT_FX, fmt = ASM_FMT_F10; 792 break; 793 case 0x19: 794 op = ASM_OP_FPCVT_FXU, fmt = ASM_FMT_F10; 795 break; 796 case 0x1A: 797 op = ASM_OP_FPCVT_FX_TRUNC, fmt = ASM_FMT_F10; 798 break; 799 case 0x1B: 800 op = ASM_OP_FPCVT_FXU_TRUNC, fmt = ASM_FMT_F10; 801 break; 802 case 0x30: 803 op = ASM_OP_FPCMP_EQ, fmt = ASM_FMT_F8; 804 break; 805 case 0x31: 806 op = ASM_OP_FPCMP_LT, fmt = ASM_FMT_F8; 807 break; 808 case 0x32: 809 op = ASM_OP_FPCMP_LE, fmt = ASM_FMT_F8; 810 break; 811 case 0x33: 812 op = ASM_OP_FPCMP_UNORD, fmt = ASM_FMT_F8; 813 break; 814 case 0x34: 815 op = ASM_OP_FPCMP_NEQ, fmt = ASM_FMT_F8; 816 break; 817 case 0x35: 818 op = ASM_OP_FPCMP_NLT, fmt = ASM_FMT_F8; 819 break; 820 case 0x36: 821 op = ASM_OP_FPCMP_NLE, fmt = ASM_FMT_F8; 822 break; 823 case 0x37: 824 op = ASM_OP_FPCMP_ORD, fmt = ASM_FMT_F8; 825 break; 826 } 827 } else { 828 if (FIELD(bits, 36, 1) == 0) /* q */ 829 op = ASM_OP_FPRCPA, fmt = ASM_FMT_F6; 830 else 831 op = ASM_OP_FPRSQRTA, fmt = ASM_FMT_F7; 832 } 833 break; 834 case 0x4: 835 op = ASM_OP_FCMP, fmt = ASM_FMT_F4; 836 break; 837 case 0x5: 838 op = ASM_OP_FCLASS_M, fmt = ASM_FMT_F5; 839 break; 840 case 0x8: 841 if (FIELD(bits, 36, 1) == 0) /* x */ 842 op = ASM_OP_FMA_, fmt = ASM_FMT_F1; 843 else 844 op = ASM_OP_FMA_S, fmt = ASM_FMT_F1; 845 break; 846 case 0x9: 847 if (FIELD(bits, 36, 1) == 0) /* x */ 848 op = ASM_OP_FMA_D, fmt = ASM_FMT_F1; 849 else 850 op = ASM_OP_FPMA, fmt = ASM_FMT_F1; 851 break; 852 case 0xA: 853 if (FIELD(bits, 36, 1) == 0) /* x */ 854 op = ASM_OP_FMS_, fmt = ASM_FMT_F1; 855 else 856 op = ASM_OP_FMS_S, fmt = ASM_FMT_F1; 857 break; 858 case 0xB: 859 if (FIELD(bits, 36, 1) == 0) /* x */ 860 op = ASM_OP_FMS_D, fmt = ASM_FMT_F1; 861 else 862 op = ASM_OP_FPMS, fmt = ASM_FMT_F1; 863 break; 864 case 0xC: 865 if (FIELD(bits, 36, 1) == 0) /* x */ 866 op = ASM_OP_FNMA_, fmt = ASM_FMT_F1; 867 else 868 op = ASM_OP_FNMA_S, fmt = ASM_FMT_F1; 869 break; 870 case 0xD: 871 if (FIELD(bits, 36, 1) == 0) /* x */ 872 op = ASM_OP_FNMA_D, fmt = ASM_FMT_F1; 873 else 874 op = ASM_OP_FPNMA, fmt = ASM_FMT_F1; 875 break; 876 case 0xE: 877 if (FIELD(bits, 36, 1) == 1) { /* x */ 878 switch (FIELD(bits, 34, 2)) { /* x2 */ 879 case 0x0: 880 op = ASM_OP_XMA_L, fmt = ASM_FMT_F2; 881 break; 882 case 0x2: 883 op = ASM_OP_XMA_HU, fmt = ASM_FMT_F2; 884 break; 885 case 0x3: 886 op = ASM_OP_XMA_H, fmt = ASM_FMT_F2; 887 break; 888 } 889 } else 890 op = ASM_OP_FSELECT, fmt = ASM_FMT_F3; 891 break; 892 } 893 894 if (op != ASM_OP_NONE) 895 return (asm_extract(op, fmt, bits, b, slot)); 896 return (0); 897 } 898 899 /* 900 * Decode I-unit instructions. 901 */ 902 static int 903 asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot) 904 { 905 uint64_t bits; 906 enum asm_fmt fmt; 907 enum asm_op op; 908 909 bits = SLOT(ip, slot); 910 if ((int)OPCODE(bits) >= 8) 911 return (asm_decodeA(bits, b, slot)); 912 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 913 914 switch((int)OPCODE(bits)) { 915 case 0x0: 916 switch (FIELD(bits, 33, 3)) { /* x3 */ 917 case 0x0: 918 switch (FIELD(bits, 27, 6)) { /* x6 */ 919 case 0x0: 920 op = ASM_OP_BREAK_I, fmt = ASM_FMT_I19; 921 break; 922 case 0x1: 923 if (FIELD(bits, 26, 1) == 0) /* y */ 924 op = ASM_OP_NOP_I, fmt = ASM_FMT_I18; 925 else 926 op = ASM_OP_HINT_I, fmt = ASM_FMT_I18; 927 break; 928 case 0xA: 929 op = ASM_OP_MOV_I, fmt = ASM_FMT_I27; 930 break; 931 case 0x10: 932 op = ASM_OP_ZXT1, fmt = ASM_FMT_I29; 933 break; 934 case 0x11: 935 op = ASM_OP_ZXT2, fmt = ASM_FMT_I29; 936 break; 937 case 0x12: 938 op = ASM_OP_ZXT4, fmt = ASM_FMT_I29; 939 break; 940 case 0x14: 941 op = ASM_OP_SXT1, fmt = ASM_FMT_I29; 942 break; 943 case 0x15: 944 op = ASM_OP_SXT2, fmt = ASM_FMT_I29; 945 break; 946 case 0x16: 947 op = ASM_OP_SXT4, fmt = ASM_FMT_I29; 948 break; 949 case 0x18: 950 op = ASM_OP_CZX1_L, fmt = ASM_FMT_I29; 951 break; 952 case 0x19: 953 op = ASM_OP_CZX2_L, fmt = ASM_FMT_I29; 954 break; 955 case 0x1C: 956 op = ASM_OP_CZX1_R, fmt = ASM_FMT_I29; 957 break; 958 case 0x1D: 959 op = ASM_OP_CZX2_R, fmt = ASM_FMT_I29; 960 break; 961 case 0x2A: 962 op = ASM_OP_MOV_I, fmt = ASM_FMT_I26; 963 break; 964 case 0x30: 965 op = ASM_OP_MOV_IP, fmt = ASM_FMT_I25; 966 break; 967 case 0x31: 968 op = ASM_OP_MOV_, fmt = ASM_FMT_I22; 969 break; 970 case 0x32: 971 op = ASM_OP_MOV_I, fmt = ASM_FMT_I28; 972 break; 973 case 0x33: 974 op = ASM_OP_MOV_PR, fmt = ASM_FMT_I25; 975 break; 976 } 977 break; 978 case 0x1: 979 op = ASM_OP_CHK_S_I, fmt = ASM_FMT_I20; 980 break; 981 case 0x2: 982 op = ASM_OP_MOV_, fmt = ASM_FMT_I24; 983 break; 984 case 0x3: 985 op = ASM_OP_MOV_, fmt = ASM_FMT_I23; 986 break; 987 case 0x7: 988 if (FIELD(bits, 22, 1) == 0) /* x */ 989 op = ASM_OP_MOV_, fmt = ASM_FMT_I21; 990 else 991 op = ASM_OP_MOV_RET, fmt = ASM_FMT_I21; 992 break; 993 } 994 break; 995 case 0x4: 996 op = ASM_OP_DEP_, fmt = ASM_FMT_I15; 997 break; 998 case 0x5: 999 switch (FIELD(bits, 33, 3)) { /* x + x2 */ 1000 case 0x0: 1001 if (FIELD(bits, 36, 1) == 0) { /* tb */ 1002 switch (FIELD(bits, 12, 2)) { /* c + y */ 1003 case 0x0: 1004 op = ASM_OP_TBIT_Z, fmt = ASM_FMT_I16; 1005 break; 1006 case 0x1: 1007 op = ASM_OP_TBIT_Z_UNC, 1008 fmt = ASM_FMT_I16; 1009 break; 1010 case 0x2: 1011 if (FIELD(bits, 19, 1) == 0) /* x */ 1012 op = ASM_OP_TNAT_Z, 1013 fmt = ASM_FMT_I17; 1014 else 1015 op = ASM_OP_TF_Z, 1016 fmt = ASM_FMT_I30; 1017 break; 1018 case 0x3: 1019 if (FIELD(bits, 19, 1) == 0) /* x */ 1020 op = ASM_OP_TNAT_Z_UNC, 1021 fmt = ASM_FMT_I17; 1022 else 1023 op = ASM_OP_TF_Z_UNC, 1024 fmt = ASM_FMT_I30; 1025 break; 1026 } 1027 } else { 1028 switch (FIELD(bits, 12, 2)) { /* c + y */ 1029 case 0x0: 1030 op = ASM_OP_TBIT_Z_AND, 1031 fmt = ASM_FMT_I16; 1032 break; 1033 case 0x1: 1034 op = ASM_OP_TBIT_NZ_AND, 1035 fmt = ASM_FMT_I16; 1036 break; 1037 case 0x2: 1038 if (FIELD(bits, 19, 1) == 0) /* x */ 1039 op = ASM_OP_TNAT_Z_AND, 1040 fmt = ASM_FMT_I17; 1041 else 1042 op = ASM_OP_TF_Z_AND, 1043 fmt = ASM_FMT_I30; 1044 break; 1045 case 0x3: 1046 if (FIELD(bits, 19, 1) == 0) /* x */ 1047 op = ASM_OP_TNAT_NZ_AND, 1048 fmt = ASM_FMT_I17; 1049 else 1050 op = ASM_OP_TF_NZ_AND, 1051 fmt = ASM_FMT_I30; 1052 break; 1053 } 1054 } 1055 break; 1056 case 0x1: 1057 if (FIELD(bits, 36, 1) == 0) { /* tb */ 1058 switch (FIELD(bits, 12, 2)) { /* c + y */ 1059 case 0x0: 1060 op = ASM_OP_TBIT_Z_OR, 1061 fmt = ASM_FMT_I16; 1062 break; 1063 case 0x1: 1064 op = ASM_OP_TBIT_NZ_OR, 1065 fmt = ASM_FMT_I16; 1066 break; 1067 case 0x2: 1068 if (FIELD(bits, 19, 1) == 0) /* x */ 1069 op = ASM_OP_TNAT_Z_OR, 1070 fmt = ASM_FMT_I17; 1071 else 1072 op = ASM_OP_TF_Z_OR, 1073 fmt = ASM_FMT_I30; 1074 break; 1075 case 0x3: 1076 if (FIELD(bits, 19, 1) == 0) /* x */ 1077 op = ASM_OP_TNAT_NZ_OR, 1078 fmt = ASM_FMT_I17; 1079 else 1080 op = ASM_OP_TF_NZ_OR, 1081 fmt = ASM_FMT_I30; 1082 break; 1083 } 1084 } else { 1085 switch (FIELD(bits, 12, 2)) { /* c + y */ 1086 case 0x0: 1087 op = ASM_OP_TBIT_Z_OR_ANDCM, 1088 fmt = ASM_FMT_I16; 1089 break; 1090 case 0x1: 1091 op = ASM_OP_TBIT_NZ_OR_ANDCM, 1092 fmt = ASM_FMT_I16; 1093 break; 1094 case 0x2: 1095 if (FIELD(bits, 19, 1) == 0) /* x */ 1096 op = ASM_OP_TNAT_Z_OR_ANDCM, 1097 fmt = ASM_FMT_I17; 1098 else 1099 op = ASM_OP_TF_Z_OR_ANDCM, 1100 fmt = ASM_FMT_I30; 1101 break; 1102 case 0x3: 1103 if (FIELD(bits, 19, 1) == 0) /* x */ 1104 op = ASM_OP_TNAT_NZ_OR_ANDCM, 1105 fmt = ASM_FMT_I17; 1106 else 1107 op = ASM_OP_TF_NZ_OR_ANDCM, 1108 fmt = ASM_FMT_I30; 1109 break; 1110 } 1111 } 1112 break; 1113 case 0x2: 1114 op = ASM_OP_EXTR, fmt = ASM_FMT_I11; 1115 break; 1116 case 0x3: 1117 if (FIELD(bits, 26, 1) == 0) /* y */ 1118 op = ASM_OP_DEP_Z, fmt = ASM_FMT_I12; 1119 else 1120 op = ASM_OP_DEP_Z, fmt = ASM_FMT_I13; 1121 break; 1122 case 0x6: 1123 op = ASM_OP_SHRP, fmt = ASM_FMT_I10; 1124 break; 1125 case 0x7: 1126 op = ASM_OP_DEP_, fmt = ASM_FMT_I14; 1127 break; 1128 } 1129 break; 1130 case 0x7: 1131 switch (FIELD(bits, 32, 5)) { /* ve + zb + x2a + za */ 1132 case 0x2: 1133 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1134 case 0x0: 1135 op = ASM_OP_PSHR2_U, fmt = ASM_FMT_I5; 1136 break; 1137 case 0x1: case 0x5: case 0x9: case 0xD: 1138 op = ASM_OP_PMPYSHR2_U, fmt = ASM_FMT_I1; 1139 break; 1140 case 0x2: 1141 op = ASM_OP_PSHR2_, fmt = ASM_FMT_I5; 1142 break; 1143 case 0x3: case 0x7: case 0xB: case 0xF: 1144 op = ASM_OP_PMPYSHR2_, fmt = ASM_FMT_I1; 1145 break; 1146 case 0x4: 1147 op = ASM_OP_PSHL2, fmt = ASM_FMT_I7; 1148 break; 1149 } 1150 break; 1151 case 0x6: 1152 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1153 case 0x1: 1154 op = ASM_OP_PSHR2_U, fmt = ASM_FMT_I6; 1155 break; 1156 case 0x3: 1157 op = ASM_OP_PSHR2_, fmt = ASM_FMT_I6; 1158 break; 1159 case 0x9: 1160 op = ASM_OP_POPCNT, fmt = ASM_FMT_I9; 1161 break; 1162 } 1163 break; 1164 case 0x8: 1165 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1166 case 0x1: 1167 op = ASM_OP_PMIN1_U, fmt = ASM_FMT_I2; 1168 break; 1169 case 0x4: 1170 op = ASM_OP_UNPACK1_H, fmt = ASM_FMT_I2; 1171 break; 1172 case 0x5: 1173 op = ASM_OP_PMAX1_U, fmt = ASM_FMT_I2; 1174 break; 1175 case 0x6: 1176 op = ASM_OP_UNPACK1_L, fmt = ASM_FMT_I2; 1177 break; 1178 case 0x8: 1179 op = ASM_OP_MIX1_R, fmt = ASM_FMT_I2; 1180 break; 1181 case 0xA: 1182 op = ASM_OP_MIX1_L, fmt = ASM_FMT_I2; 1183 break; 1184 case 0xB: 1185 op = ASM_OP_PSAD1, fmt = ASM_FMT_I2; 1186 break; 1187 } 1188 break; 1189 case 0xA: 1190 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1191 case 0x0: 1192 op = ASM_OP_PACK2_USS, fmt = ASM_FMT_I2; 1193 break; 1194 case 0x2: 1195 op = ASM_OP_PACK2_SSS, fmt = ASM_FMT_I2; 1196 break; 1197 case 0x3: 1198 op = ASM_OP_PMIN2, fmt = ASM_FMT_I2; 1199 break; 1200 case 0x4: 1201 op = ASM_OP_UNPACK2_H, fmt = ASM_FMT_I2; 1202 break; 1203 case 0x6: 1204 op = ASM_OP_UNPACK2_L, fmt = ASM_FMT_I2; 1205 break; 1206 case 0x7: 1207 op = ASM_OP_PMAX2, fmt = ASM_FMT_I2; 1208 break; 1209 case 0x8: 1210 op = ASM_OP_MIX2_R, fmt = ASM_FMT_I2; 1211 break; 1212 case 0xA: 1213 op = ASM_OP_MIX2_L, fmt = ASM_FMT_I2; 1214 break; 1215 case 0xD: 1216 op = ASM_OP_PMPY2_R, fmt = ASM_FMT_I2; 1217 break; 1218 case 0xF: 1219 op = ASM_OP_PMPY2_L, fmt = ASM_FMT_I2; 1220 break; 1221 } 1222 break; 1223 case 0xC: 1224 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1225 case 0xA: 1226 op = ASM_OP_MUX1, fmt = ASM_FMT_I3; 1227 break; 1228 } 1229 break; 1230 case 0xE: 1231 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1232 case 0x5: 1233 op = ASM_OP_PSHL2, fmt = ASM_FMT_I8; 1234 break; 1235 case 0xA: 1236 op = ASM_OP_MUX2, fmt = ASM_FMT_I4; 1237 break; 1238 } 1239 break; 1240 case 0x10: 1241 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1242 case 0x0: 1243 op = ASM_OP_PSHR4_U, fmt = ASM_FMT_I5; 1244 break; 1245 case 0x2: 1246 op = ASM_OP_PSHR4_, fmt = ASM_FMT_I5; 1247 break; 1248 case 0x4: 1249 op = ASM_OP_PSHL4, fmt = ASM_FMT_I7; 1250 break; 1251 } 1252 break; 1253 case 0x12: 1254 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1255 case 0x0: 1256 op = ASM_OP_SHR_U, fmt = ASM_FMT_I5; 1257 break; 1258 case 0x2: 1259 op = ASM_OP_SHR_, fmt = ASM_FMT_I5; 1260 break; 1261 case 0x4: 1262 op = ASM_OP_SHL, fmt = ASM_FMT_I7; 1263 break; 1264 } 1265 break; 1266 case 0x14: 1267 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1268 case 0x1: 1269 op = ASM_OP_PSHR4_U, fmt = ASM_FMT_I6; 1270 break; 1271 case 0x3: 1272 op = ASM_OP_PSHR4_, fmt = ASM_FMT_I6; 1273 break; 1274 } 1275 break; 1276 case 0x18: 1277 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1278 case 0x2: 1279 op = ASM_OP_PACK4_SSS, fmt = ASM_FMT_I2; 1280 break; 1281 case 0x4: 1282 op = ASM_OP_UNPACK4_H, fmt = ASM_FMT_I2; 1283 break; 1284 case 0x6: 1285 op = ASM_OP_UNPACK4_L, fmt = ASM_FMT_I2; 1286 break; 1287 case 0x8: 1288 op = ASM_OP_MIX4_R, fmt = ASM_FMT_I2; 1289 break; 1290 case 0xA: 1291 op = ASM_OP_MIX4_L, fmt = ASM_FMT_I2; 1292 break; 1293 } 1294 break; 1295 case 0x1C: 1296 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1297 case 0x5: 1298 op = ASM_OP_PSHL4, fmt = ASM_FMT_I8; 1299 break; 1300 } 1301 break; 1302 } 1303 break; 1304 } 1305 1306 if (op != ASM_OP_NONE) 1307 return (asm_extract(op, fmt, bits, b, slot)); 1308 return (0); 1309 } 1310 1311 /* 1312 * Decode M-unit instructions. 1313 */ 1314 static int 1315 asm_decodeM(uint64_t ip, struct asm_bundle *b, int slot) 1316 { 1317 uint64_t bits; 1318 enum asm_fmt fmt; 1319 enum asm_op op; 1320 1321 bits = SLOT(ip, slot); 1322 if ((int)OPCODE(bits) >= 8) 1323 return (asm_decodeA(bits, b, slot)); 1324 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 1325 1326 switch((int)OPCODE(bits)) { 1327 case 0x0: 1328 switch (FIELD(bits, 33, 3)) { /* x3 */ 1329 case 0x0: 1330 switch (FIELD(bits, 27, 6)) { /* x6 (x4 + x2) */ 1331 case 0x0: 1332 op = ASM_OP_BREAK_M, fmt = ASM_FMT_M37; 1333 break; 1334 case 0x1: 1335 if (FIELD(bits, 26, 1) == 0) /* y */ 1336 op = ASM_OP_NOP_M, fmt = ASM_FMT_M48; 1337 else 1338 op = ASM_OP_HINT_M, fmt = ASM_FMT_M48; 1339 break; 1340 case 0x4: case 0x14: case 0x24: case 0x34: 1341 op = ASM_OP_SUM, fmt = ASM_FMT_M44; 1342 break; 1343 case 0x5: case 0x15: case 0x25: case 0x35: 1344 op = ASM_OP_RUM, fmt = ASM_FMT_M44; 1345 break; 1346 case 0x6: case 0x16: case 0x26: case 0x36: 1347 op = ASM_OP_SSM, fmt = ASM_FMT_M44; 1348 break; 1349 case 0x7: case 0x17: case 0x27: case 0x37: 1350 op = ASM_OP_RSM, fmt = ASM_FMT_M44; 1351 break; 1352 case 0xA: 1353 op = ASM_OP_LOADRS, fmt = ASM_FMT_M25; 1354 break; 1355 case 0xC: 1356 op = ASM_OP_FLUSHRS, fmt = ASM_FMT_M25; 1357 break; 1358 case 0x10: 1359 op = ASM_OP_INVALA_, fmt = ASM_FMT_M24; 1360 break; 1361 case 0x12: 1362 op = ASM_OP_INVALA_E, fmt = ASM_FMT_M26; 1363 break; 1364 case 0x13: 1365 op = ASM_OP_INVALA_E, fmt = ASM_FMT_M27; 1366 break; 1367 case 0x20: 1368 op = ASM_OP_FWB, fmt = ASM_FMT_M24; 1369 break; 1370 case 0x22: 1371 op = ASM_OP_MF_, fmt = ASM_FMT_M24; 1372 break; 1373 case 0x23: 1374 op = ASM_OP_MF_A, fmt = ASM_FMT_M24; 1375 break; 1376 case 0x28: 1377 op = ASM_OP_MOV_M, fmt = ASM_FMT_M30; 1378 break; 1379 case 0x30: 1380 op = ASM_OP_SRLZ_D, fmt = ASM_FMT_M24; 1381 break; 1382 case 0x31: 1383 op = ASM_OP_SRLZ_I, fmt = ASM_FMT_M24; 1384 break; 1385 case 0x33: 1386 op = ASM_OP_SYNC_I, fmt = ASM_FMT_M24; 1387 break; 1388 } 1389 break; 1390 case 0x4: 1391 op = ASM_OP_CHK_A_NC, fmt = ASM_FMT_M22; 1392 break; 1393 case 0x5: 1394 op = ASM_OP_CHK_A_CLR, fmt = ASM_FMT_M22; 1395 break; 1396 case 0x6: 1397 op = ASM_OP_CHK_A_NC, fmt = ASM_FMT_M23; 1398 break; 1399 case 0x7: 1400 op = ASM_OP_CHK_A_CLR, fmt = ASM_FMT_M23; 1401 break; 1402 } 1403 break; 1404 case 0x1: 1405 switch (FIELD(bits, 33, 3)) { /* x3 */ 1406 case 0x0: 1407 switch (FIELD(bits, 27, 6)) { /* x6 (x4 + x2) */ 1408 case 0x0: 1409 op = ASM_OP_MOV_RR, fmt = ASM_FMT_M42; 1410 break; 1411 case 0x1: 1412 op = ASM_OP_MOV_DBR, fmt = ASM_FMT_M42; 1413 break; 1414 case 0x2: 1415 op = ASM_OP_MOV_IBR, fmt = ASM_FMT_M42; 1416 break; 1417 case 0x3: 1418 op = ASM_OP_MOV_PKR, fmt = ASM_FMT_M42; 1419 break; 1420 case 0x4: 1421 op = ASM_OP_MOV_PMC, fmt = ASM_FMT_M42; 1422 break; 1423 case 0x5: 1424 op = ASM_OP_MOV_PMD, fmt = ASM_FMT_M42; 1425 break; 1426 case 0x6: 1427 op = ASM_OP_MOV_MSR, fmt = ASM_FMT_M42; 1428 break; 1429 case 0x9: 1430 op = ASM_OP_PTC_L, fmt = ASM_FMT_M45; 1431 break; 1432 case 0xA: 1433 op = ASM_OP_PTC_G, fmt = ASM_FMT_M45; 1434 break; 1435 case 0xB: 1436 op = ASM_OP_PTC_GA, fmt = ASM_FMT_M45; 1437 break; 1438 case 0xC: 1439 op = ASM_OP_PTR_D, fmt = ASM_FMT_M45; 1440 break; 1441 case 0xD: 1442 op = ASM_OP_PTR_I, fmt = ASM_FMT_M45; 1443 break; 1444 case 0xE: 1445 op = ASM_OP_ITR_D, fmt = ASM_FMT_M42; 1446 break; 1447 case 0xF: 1448 op = ASM_OP_ITR_I, fmt = ASM_FMT_M42; 1449 break; 1450 case 0x10: 1451 op = ASM_OP_MOV_RR, fmt = ASM_FMT_M43; 1452 break; 1453 case 0x11: 1454 op = ASM_OP_MOV_DBR, fmt = ASM_FMT_M43; 1455 break; 1456 case 0x12: 1457 op = ASM_OP_MOV_IBR, fmt = ASM_FMT_M43; 1458 break; 1459 case 0x13: 1460 op = ASM_OP_MOV_PKR, fmt = ASM_FMT_M43; 1461 break; 1462 case 0x14: 1463 op = ASM_OP_MOV_PMC, fmt = ASM_FMT_M43; 1464 break; 1465 case 0x15: 1466 op = ASM_OP_MOV_PMD, fmt = ASM_FMT_M43; 1467 break; 1468 case 0x16: 1469 op = ASM_OP_MOV_MSR, fmt = ASM_FMT_M43; 1470 break; 1471 case 0x17: 1472 op = ASM_OP_MOV_CPUID, fmt = ASM_FMT_M43; 1473 break; 1474 case 0x18: 1475 op = ASM_OP_PROBE_R, fmt = ASM_FMT_M39; 1476 break; 1477 case 0x19: 1478 op = ASM_OP_PROBE_W, fmt = ASM_FMT_M39; 1479 break; 1480 case 0x1A: 1481 op = ASM_OP_THASH, fmt = ASM_FMT_M46; 1482 break; 1483 case 0x1B: 1484 op = ASM_OP_TTAG, fmt = ASM_FMT_M46; 1485 break; 1486 case 0x1E: 1487 op = ASM_OP_TPA, fmt = ASM_FMT_M46; 1488 break; 1489 case 0x1F: 1490 op = ASM_OP_TAK, fmt = ASM_FMT_M46; 1491 break; 1492 case 0x21: 1493 op = ASM_OP_MOV_PSR_UM, fmt = ASM_FMT_M36; 1494 break; 1495 case 0x22: 1496 op = ASM_OP_MOV_M, fmt = ASM_FMT_M31; 1497 break; 1498 case 0x24: 1499 op = ASM_OP_MOV_, fmt = ASM_FMT_M33; 1500 break; 1501 case 0x25: 1502 op = ASM_OP_MOV_PSR, fmt = ASM_FMT_M36; 1503 break; 1504 case 0x29: 1505 op = ASM_OP_MOV_PSR_UM, fmt = ASM_FMT_M35; 1506 break; 1507 case 0x2A: 1508 op = ASM_OP_MOV_M, fmt = ASM_FMT_M29; 1509 break; 1510 case 0x2C: 1511 op = ASM_OP_MOV_, fmt = ASM_FMT_M32; 1512 break; 1513 case 0x2D: 1514 op = ASM_OP_MOV_PSR_L, fmt = ASM_FMT_M35; 1515 break; 1516 case 0x2E: 1517 op = ASM_OP_ITC_D, fmt = ASM_FMT_M41; 1518 break; 1519 case 0x2F: 1520 op = ASM_OP_ITC_I, fmt = ASM_FMT_M41; 1521 break; 1522 case 0x30: 1523 if (FIELD(bits, 36, 1) == 0) /* x */ 1524 op = ASM_OP_FC_, fmt = ASM_FMT_M28; 1525 else 1526 op = ASM_OP_FC_I, fmt = ASM_FMT_M28; 1527 break; 1528 case 0x31: 1529 op = ASM_OP_PROBE_RW_FAULT, fmt = ASM_FMT_M40; 1530 break; 1531 case 0x32: 1532 op = ASM_OP_PROBE_R_FAULT, fmt = ASM_FMT_M40; 1533 break; 1534 case 0x33: 1535 op = ASM_OP_PROBE_W_FAULT, fmt = ASM_FMT_M40; 1536 break; 1537 case 0x34: 1538 op = ASM_OP_PTC_E, fmt = ASM_FMT_M47; 1539 break; 1540 case 0x38: 1541 op = ASM_OP_PROBE_R, fmt = ASM_FMT_M38; 1542 break; 1543 case 0x39: 1544 op = ASM_OP_PROBE_W, fmt = ASM_FMT_M38; 1545 break; 1546 } 1547 break; 1548 case 0x1: 1549 op = ASM_OP_CHK_S_M, fmt = ASM_FMT_M20; 1550 break; 1551 case 0x3: 1552 op = ASM_OP_CHK_S, fmt = ASM_FMT_M21; 1553 break; 1554 case 0x6: 1555 op = ASM_OP_ALLOC, fmt = ASM_FMT_M34; 1556 break; 1557 } 1558 break; 1559 case 0x4: 1560 if (FIELD(bits, 27, 1) == 0) { /* x */ 1561 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1562 case 0x0: 1563 op = ASM_OP_LD1_, fmt = ASM_FMT_M1; 1564 break; 1565 case 0x1: 1566 op = ASM_OP_LD2_, fmt = ASM_FMT_M1; 1567 break; 1568 case 0x2: 1569 op = ASM_OP_LD4_, fmt = ASM_FMT_M1; 1570 break; 1571 case 0x3: 1572 op = ASM_OP_LD8_, fmt = ASM_FMT_M1; 1573 break; 1574 case 0x4: 1575 op = ASM_OP_LD1_S, fmt = ASM_FMT_M1; 1576 break; 1577 case 0x5: 1578 op = ASM_OP_LD2_S, fmt = ASM_FMT_M1; 1579 break; 1580 case 0x6: 1581 op = ASM_OP_LD4_S, fmt = ASM_FMT_M1; 1582 break; 1583 case 0x7: 1584 op = ASM_OP_LD8_S, fmt = ASM_FMT_M1; 1585 break; 1586 case 0x8: 1587 op = ASM_OP_LD1_A, fmt = ASM_FMT_M1; 1588 break; 1589 case 0x9: 1590 op = ASM_OP_LD2_A, fmt = ASM_FMT_M1; 1591 break; 1592 case 0xA: 1593 op = ASM_OP_LD4_A, fmt = ASM_FMT_M1; 1594 break; 1595 case 0xB: 1596 op = ASM_OP_LD8_A, fmt = ASM_FMT_M1; 1597 break; 1598 case 0xC: 1599 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M1; 1600 break; 1601 case 0xD: 1602 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M1; 1603 break; 1604 case 0xE: 1605 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M1; 1606 break; 1607 case 0xF: 1608 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M1; 1609 break; 1610 case 0x10: 1611 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M1; 1612 break; 1613 case 0x11: 1614 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M1; 1615 break; 1616 case 0x12: 1617 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M1; 1618 break; 1619 case 0x13: 1620 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M1; 1621 break; 1622 case 0x14: 1623 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M1; 1624 break; 1625 case 0x15: 1626 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M1; 1627 break; 1628 case 0x16: 1629 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M1; 1630 break; 1631 case 0x17: 1632 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M1; 1633 break; 1634 case 0x1B: 1635 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M1; 1636 break; 1637 case 0x20: 1638 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M1; 1639 break; 1640 case 0x21: 1641 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M1; 1642 break; 1643 case 0x22: 1644 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M1; 1645 break; 1646 case 0x23: 1647 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M1; 1648 break; 1649 case 0x24: 1650 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M1; 1651 break; 1652 case 0x25: 1653 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M1; 1654 break; 1655 case 0x26: 1656 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M1; 1657 break; 1658 case 0x27: 1659 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M1; 1660 break; 1661 case 0x28: 1662 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M1; 1663 break; 1664 case 0x29: 1665 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M1; 1666 break; 1667 case 0x2A: 1668 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M1; 1669 break; 1670 case 0x2B: 1671 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M1; 1672 break; 1673 case 0x30: 1674 op = ASM_OP_ST1_, fmt = ASM_FMT_M4; 1675 break; 1676 case 0x31: 1677 op = ASM_OP_ST2_, fmt = ASM_FMT_M4; 1678 break; 1679 case 0x32: 1680 op = ASM_OP_ST4_, fmt = ASM_FMT_M4; 1681 break; 1682 case 0x33: 1683 op = ASM_OP_ST8_, fmt = ASM_FMT_M4; 1684 break; 1685 case 0x34: 1686 op = ASM_OP_ST1_REL, fmt = ASM_FMT_M4; 1687 break; 1688 case 0x35: 1689 op = ASM_OP_ST2_REL, fmt = ASM_FMT_M4; 1690 break; 1691 case 0x36: 1692 op = ASM_OP_ST4_REL, fmt = ASM_FMT_M4; 1693 break; 1694 case 0x37: 1695 op = ASM_OP_ST8_REL, fmt = ASM_FMT_M4; 1696 break; 1697 case 0x3B: 1698 op = ASM_OP_ST8_SPILL, fmt = ASM_FMT_M4; 1699 break; 1700 case 0x40: 1701 op = ASM_OP_LD1_, fmt = ASM_FMT_M2; 1702 break; 1703 case 0x41: 1704 op = ASM_OP_LD2_, fmt = ASM_FMT_M2; 1705 break; 1706 case 0x42: 1707 op = ASM_OP_LD4_, fmt = ASM_FMT_M2; 1708 break; 1709 case 0x43: 1710 op = ASM_OP_LD8_, fmt = ASM_FMT_M2; 1711 break; 1712 case 0x44: 1713 op = ASM_OP_LD1_S, fmt = ASM_FMT_M2; 1714 break; 1715 case 0x45: 1716 op = ASM_OP_LD2_S, fmt = ASM_FMT_M2; 1717 break; 1718 case 0x46: 1719 op = ASM_OP_LD4_S, fmt = ASM_FMT_M2; 1720 break; 1721 case 0x47: 1722 op = ASM_OP_LD8_S, fmt = ASM_FMT_M2; 1723 break; 1724 case 0x48: 1725 op = ASM_OP_LD1_A, fmt = ASM_FMT_M2; 1726 break; 1727 case 0x49: 1728 op = ASM_OP_LD2_A, fmt = ASM_FMT_M2; 1729 break; 1730 case 0x4A: 1731 op = ASM_OP_LD4_A, fmt = ASM_FMT_M2; 1732 break; 1733 case 0x4B: 1734 op = ASM_OP_LD8_A, fmt = ASM_FMT_M2; 1735 break; 1736 case 0x4C: 1737 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M2; 1738 break; 1739 case 0x4D: 1740 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M2; 1741 break; 1742 case 0x4E: 1743 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M2; 1744 break; 1745 case 0x4F: 1746 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M2; 1747 break; 1748 case 0x50: 1749 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M2; 1750 break; 1751 case 0x51: 1752 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M2; 1753 break; 1754 case 0x52: 1755 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M2; 1756 break; 1757 case 0x53: 1758 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M2; 1759 break; 1760 case 0x54: 1761 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M2; 1762 break; 1763 case 0x55: 1764 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M2; 1765 break; 1766 case 0x56: 1767 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M2; 1768 break; 1769 case 0x57: 1770 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M2; 1771 break; 1772 case 0x5B: 1773 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M2; 1774 break; 1775 case 0x60: 1776 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M2; 1777 break; 1778 case 0x61: 1779 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M2; 1780 break; 1781 case 0x62: 1782 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M2; 1783 break; 1784 case 0x63: 1785 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M2; 1786 break; 1787 case 0x64: 1788 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M2; 1789 break; 1790 case 0x65: 1791 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M2; 1792 break; 1793 case 0x66: 1794 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M2; 1795 break; 1796 case 0x67: 1797 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M2; 1798 break; 1799 case 0x68: 1800 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M2; 1801 break; 1802 case 0x69: 1803 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M2; 1804 break; 1805 case 0x6A: 1806 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M2; 1807 break; 1808 case 0x6B: 1809 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M2; 1810 break; 1811 } 1812 } else { 1813 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1814 case 0x0: 1815 op = ASM_OP_CMPXCHG1_ACQ, fmt = ASM_FMT_M16; 1816 break; 1817 case 0x1: 1818 op = ASM_OP_CMPXCHG2_ACQ, fmt = ASM_FMT_M16; 1819 break; 1820 case 0x2: 1821 op = ASM_OP_CMPXCHG4_ACQ, fmt = ASM_FMT_M16; 1822 break; 1823 case 0x3: 1824 op = ASM_OP_CMPXCHG8_ACQ, fmt = ASM_FMT_M16; 1825 break; 1826 case 0x4: 1827 op = ASM_OP_CMPXCHG1_REL, fmt = ASM_FMT_M16; 1828 break; 1829 case 0x5: 1830 op = ASM_OP_CMPXCHG2_REL, fmt = ASM_FMT_M16; 1831 break; 1832 case 0x6: 1833 op = ASM_OP_CMPXCHG4_REL, fmt = ASM_FMT_M16; 1834 break; 1835 case 0x7: 1836 op = ASM_OP_CMPXCHG8_REL, fmt = ASM_FMT_M16; 1837 break; 1838 case 0x8: 1839 op = ASM_OP_XCHG1, fmt = ASM_FMT_M16; 1840 break; 1841 case 0x9: 1842 op = ASM_OP_XCHG2, fmt = ASM_FMT_M16; 1843 break; 1844 case 0xA: 1845 op = ASM_OP_XCHG4, fmt = ASM_FMT_M16; 1846 break; 1847 case 0xB: 1848 op = ASM_OP_XCHG8, fmt = ASM_FMT_M16; 1849 break; 1850 case 0x12: 1851 op = ASM_OP_FETCHADD4_ACQ, fmt = ASM_FMT_M17; 1852 break; 1853 case 0x13: 1854 op = ASM_OP_FETCHADD8_ACQ, fmt = ASM_FMT_M17; 1855 break; 1856 case 0x16: 1857 op = ASM_OP_FETCHADD4_REL, fmt = ASM_FMT_M17; 1858 break; 1859 case 0x17: 1860 op = ASM_OP_FETCHADD8_REL, fmt = ASM_FMT_M17; 1861 break; 1862 case 0x1C: 1863 op = ASM_OP_GETF_SIG, fmt = ASM_FMT_M19; 1864 break; 1865 case 0x1D: 1866 op = ASM_OP_GETF_EXP, fmt = ASM_FMT_M19; 1867 break; 1868 case 0x1E: 1869 op = ASM_OP_GETF_S, fmt = ASM_FMT_M19; 1870 break; 1871 case 0x1F: 1872 op = ASM_OP_GETF_D, fmt = ASM_FMT_M19; 1873 break; 1874 case 0x20: 1875 op = ASM_OP_CMP8XCHG16_ACQ, fmt = ASM_FMT_M16; 1876 break; 1877 case 0x24: 1878 op = ASM_OP_CMP8XCHG16_REL, fmt = ASM_FMT_M16; 1879 break; 1880 case 0x28: 1881 op = ASM_OP_LD16_, fmt = ASM_FMT_M1; 1882 break; 1883 case 0x2C: 1884 op = ASM_OP_LD16_ACQ, fmt = ASM_FMT_M1; 1885 break; 1886 case 0x30: 1887 op = ASM_OP_ST16_, fmt = ASM_FMT_M4; 1888 break; 1889 case 0x34: 1890 op = ASM_OP_ST16_REL, fmt = ASM_FMT_M4; 1891 break; 1892 } 1893 } 1894 break; 1895 case 0x5: 1896 switch (FIELD(bits, 30, 6)) { /* x6 */ 1897 case 0x0: 1898 op = ASM_OP_LD1_, fmt = ASM_FMT_M3; 1899 break; 1900 case 0x1: 1901 op = ASM_OP_LD2_, fmt = ASM_FMT_M3; 1902 break; 1903 case 0x2: 1904 op = ASM_OP_LD4_, fmt = ASM_FMT_M3; 1905 break; 1906 case 0x3: 1907 op = ASM_OP_LD8_, fmt = ASM_FMT_M3; 1908 break; 1909 case 0x4: 1910 op = ASM_OP_LD1_S, fmt = ASM_FMT_M3; 1911 break; 1912 case 0x5: 1913 op = ASM_OP_LD2_S, fmt = ASM_FMT_M3; 1914 break; 1915 case 0x6: 1916 op = ASM_OP_LD4_S, fmt = ASM_FMT_M3; 1917 break; 1918 case 0x7: 1919 op = ASM_OP_LD8_S, fmt = ASM_FMT_M3; 1920 break; 1921 case 0x8: 1922 op = ASM_OP_LD1_A, fmt = ASM_FMT_M3; 1923 break; 1924 case 0x9: 1925 op = ASM_OP_LD2_A, fmt = ASM_FMT_M3; 1926 break; 1927 case 0xA: 1928 op = ASM_OP_LD4_A, fmt = ASM_FMT_M3; 1929 break; 1930 case 0xB: 1931 op = ASM_OP_LD8_A, fmt = ASM_FMT_M3; 1932 break; 1933 case 0xC: 1934 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M3; 1935 break; 1936 case 0xD: 1937 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M3; 1938 break; 1939 case 0xE: 1940 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M3; 1941 break; 1942 case 0xF: 1943 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M3; 1944 break; 1945 case 0x10: 1946 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M3; 1947 break; 1948 case 0x11: 1949 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M3; 1950 break; 1951 case 0x12: 1952 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M3; 1953 break; 1954 case 0x13: 1955 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M3; 1956 break; 1957 case 0x14: 1958 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M3; 1959 break; 1960 case 0x15: 1961 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M3; 1962 break; 1963 case 0x16: 1964 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M3; 1965 break; 1966 case 0x17: 1967 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M3; 1968 break; 1969 case 0x1B: 1970 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M3; 1971 break; 1972 case 0x20: 1973 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M3; 1974 break; 1975 case 0x21: 1976 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M3; 1977 break; 1978 case 0x22: 1979 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M3; 1980 break; 1981 case 0x23: 1982 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M3; 1983 break; 1984 case 0x24: 1985 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M3; 1986 break; 1987 case 0x25: 1988 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M3; 1989 break; 1990 case 0x26: 1991 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M3; 1992 break; 1993 case 0x27: 1994 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M3; 1995 break; 1996 case 0x28: 1997 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M3; 1998 break; 1999 case 0x29: 2000 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M3; 2001 break; 2002 case 0x2A: 2003 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M3; 2004 break; 2005 case 0x2B: 2006 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M3; 2007 break; 2008 case 0x30: 2009 op = ASM_OP_ST1_, fmt = ASM_FMT_M5; 2010 break; 2011 case 0x31: 2012 op = ASM_OP_ST2_, fmt = ASM_FMT_M5; 2013 break; 2014 case 0x32: 2015 op = ASM_OP_ST4_, fmt = ASM_FMT_M5; 2016 break; 2017 case 0x33: 2018 op = ASM_OP_ST8_, fmt = ASM_FMT_M5; 2019 break; 2020 case 0x34: 2021 op = ASM_OP_ST1_REL, fmt = ASM_FMT_M5; 2022 break; 2023 case 0x35: 2024 op = ASM_OP_ST2_REL, fmt = ASM_FMT_M5; 2025 break; 2026 case 0x36: 2027 op = ASM_OP_ST4_REL, fmt = ASM_FMT_M5; 2028 break; 2029 case 0x37: 2030 op = ASM_OP_ST8_REL, fmt = ASM_FMT_M5; 2031 break; 2032 case 0x3B: 2033 op = ASM_OP_ST8_SPILL, fmt = ASM_FMT_M5; 2034 break; 2035 } 2036 break; 2037 case 0x6: 2038 if (FIELD(bits, 27, 1) == 0) { /* x */ 2039 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 2040 case 0x0: 2041 op = ASM_OP_LDFE_, fmt = ASM_FMT_M6; 2042 break; 2043 case 0x1: 2044 op = ASM_OP_LDF8_, fmt = ASM_FMT_M6; 2045 break; 2046 case 0x2: 2047 op = ASM_OP_LDFS_, fmt = ASM_FMT_M6; 2048 break; 2049 case 0x3: 2050 op = ASM_OP_LDFD_, fmt = ASM_FMT_M6; 2051 break; 2052 case 0x4: 2053 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M6; 2054 break; 2055 case 0x5: 2056 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M6; 2057 break; 2058 case 0x6: 2059 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M6; 2060 break; 2061 case 0x7: 2062 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M6; 2063 break; 2064 case 0x8: 2065 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M6; 2066 break; 2067 case 0x9: 2068 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M6; 2069 break; 2070 case 0xA: 2071 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M6; 2072 break; 2073 case 0xB: 2074 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M6; 2075 break; 2076 case 0xC: 2077 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M6; 2078 break; 2079 case 0xD: 2080 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M6; 2081 break; 2082 case 0xE: 2083 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M6; 2084 break; 2085 case 0xF: 2086 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M6; 2087 break; 2088 case 0x1B: 2089 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M6; 2090 break; 2091 case 0x20: 2092 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M6; 2093 break; 2094 case 0x21: 2095 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M6; 2096 break; 2097 case 0x22: 2098 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M6; 2099 break; 2100 case 0x23: 2101 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M6; 2102 break; 2103 case 0x24: 2104 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M6; 2105 break; 2106 case 0x25: 2107 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M6; 2108 break; 2109 case 0x26: 2110 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M6; 2111 break; 2112 case 0x27: 2113 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M6; 2114 break; 2115 case 0x2C: 2116 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M13; 2117 break; 2118 case 0x2D: 2119 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M13; 2120 break; 2121 case 0x2E: 2122 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M13; 2123 break; 2124 case 0x2F: 2125 op = ASM_OP_LFETCH_FAULT_EXCL, 2126 fmt = ASM_FMT_M13; 2127 break; 2128 case 0x30: 2129 op = ASM_OP_STFE, fmt = ASM_FMT_M9; 2130 break; 2131 case 0x31: 2132 op = ASM_OP_STF8, fmt = ASM_FMT_M9; 2133 break; 2134 case 0x32: 2135 op = ASM_OP_STFS, fmt = ASM_FMT_M9; 2136 break; 2137 case 0x33: 2138 op = ASM_OP_STFD, fmt = ASM_FMT_M9; 2139 break; 2140 case 0x3B: 2141 op = ASM_OP_STF_SPILL, fmt = ASM_FMT_M9; 2142 break; 2143 case 0x40: 2144 op = ASM_OP_LDFE_, fmt = ASM_FMT_M7; 2145 break; 2146 case 0x41: 2147 op = ASM_OP_LDF8_, fmt = ASM_FMT_M7; 2148 break; 2149 case 0x42: 2150 op = ASM_OP_LDFS_, fmt = ASM_FMT_M7; 2151 break; 2152 case 0x43: 2153 op = ASM_OP_LDFD_, fmt = ASM_FMT_M7; 2154 break; 2155 case 0x44: 2156 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M7; 2157 break; 2158 case 0x45: 2159 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M7; 2160 break; 2161 case 0x46: 2162 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M7; 2163 break; 2164 case 0x47: 2165 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M7; 2166 break; 2167 case 0x48: 2168 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M7; 2169 break; 2170 case 0x49: 2171 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M7; 2172 break; 2173 case 0x4A: 2174 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M7; 2175 break; 2176 case 0x4B: 2177 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M7; 2178 break; 2179 case 0x4C: 2180 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M7; 2181 break; 2182 case 0x4D: 2183 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M7; 2184 break; 2185 case 0x4E: 2186 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M7; 2187 break; 2188 case 0x4F: 2189 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M7; 2190 break; 2191 case 0x5B: 2192 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M7; 2193 break; 2194 case 0x60: 2195 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M7; 2196 break; 2197 case 0x61: 2198 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M7; 2199 break; 2200 case 0x62: 2201 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M7; 2202 break; 2203 case 0x63: 2204 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M7; 2205 break; 2206 case 0x64: 2207 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M7; 2208 break; 2209 case 0x65: 2210 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M7; 2211 break; 2212 case 0x66: 2213 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M7; 2214 break; 2215 case 0x67: 2216 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M7; 2217 break; 2218 case 0x6C: 2219 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M14; 2220 break; 2221 case 0x6D: 2222 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M14; 2223 break; 2224 case 0x6E: 2225 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M14; 2226 break; 2227 case 0x6F: 2228 op = ASM_OP_LFETCH_FAULT_EXCL, 2229 fmt = ASM_FMT_M14; 2230 break; 2231 } 2232 } else { 2233 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 2234 case 0x1: 2235 op = ASM_OP_LDFP8_, fmt = ASM_FMT_M11; 2236 break; 2237 case 0x2: 2238 op = ASM_OP_LDFPS_, fmt = ASM_FMT_M11; 2239 break; 2240 case 0x3: 2241 op = ASM_OP_LDFPD_, fmt = ASM_FMT_M11; 2242 break; 2243 case 0x5: 2244 op = ASM_OP_LDFP8_S, fmt = ASM_FMT_M11; 2245 break; 2246 case 0x6: 2247 op = ASM_OP_LDFPS_S, fmt = ASM_FMT_M11; 2248 break; 2249 case 0x7: 2250 op = ASM_OP_LDFPD_S, fmt = ASM_FMT_M11; 2251 break; 2252 case 0x9: 2253 op = ASM_OP_LDFP8_A, fmt = ASM_FMT_M11; 2254 break; 2255 case 0xA: 2256 op = ASM_OP_LDFPS_A, fmt = ASM_FMT_M11; 2257 break; 2258 case 0xB: 2259 op = ASM_OP_LDFPD_A, fmt = ASM_FMT_M11; 2260 break; 2261 case 0xD: 2262 op = ASM_OP_LDFP8_SA, fmt = ASM_FMT_M11; 2263 break; 2264 case 0xE: 2265 op = ASM_OP_LDFPS_SA, fmt = ASM_FMT_M11; 2266 break; 2267 case 0xF: 2268 op = ASM_OP_LDFPD_SA, fmt = ASM_FMT_M11; 2269 break; 2270 case 0x1C: 2271 op = ASM_OP_SETF_SIG, fmt = ASM_FMT_M18; 2272 break; 2273 case 0x1D: 2274 op = ASM_OP_SETF_EXP, fmt = ASM_FMT_M18; 2275 break; 2276 case 0x1E: 2277 op = ASM_OP_SETF_S, fmt = ASM_FMT_M18; 2278 break; 2279 case 0x1F: 2280 op = ASM_OP_SETF_D, fmt = ASM_FMT_M18; 2281 break; 2282 case 0x21: 2283 op = ASM_OP_LDFP8_C_CLR, fmt = ASM_FMT_M11; 2284 break; 2285 case 0x22: 2286 op = ASM_OP_LDFPS_C_CLR, fmt = ASM_FMT_M11; 2287 break; 2288 case 0x23: 2289 op = ASM_OP_LDFPD_C_CLR, fmt = ASM_FMT_M11; 2290 break; 2291 case 0x25: 2292 op = ASM_OP_LDFP8_C_NC, fmt = ASM_FMT_M11; 2293 break; 2294 case 0x26: 2295 op = ASM_OP_LDFPS_C_NC, fmt = ASM_FMT_M11; 2296 break; 2297 case 0x27: 2298 op = ASM_OP_LDFPD_C_NC, fmt = ASM_FMT_M11; 2299 break; 2300 case 0x41: 2301 op = ASM_OP_LDFP8_, fmt = ASM_FMT_M12; 2302 break; 2303 case 0x42: 2304 op = ASM_OP_LDFPS_, fmt = ASM_FMT_M12; 2305 break; 2306 case 0x43: 2307 op = ASM_OP_LDFPD_, fmt = ASM_FMT_M12; 2308 break; 2309 case 0x45: 2310 op = ASM_OP_LDFP8_S, fmt = ASM_FMT_M12; 2311 break; 2312 case 0x46: 2313 op = ASM_OP_LDFPS_S, fmt = ASM_FMT_M12; 2314 break; 2315 case 0x47: 2316 op = ASM_OP_LDFPD_S, fmt = ASM_FMT_M12; 2317 break; 2318 case 0x49: 2319 op = ASM_OP_LDFP8_A, fmt = ASM_FMT_M12; 2320 break; 2321 case 0x4A: 2322 op = ASM_OP_LDFPS_A, fmt = ASM_FMT_M12; 2323 break; 2324 case 0x4B: 2325 op = ASM_OP_LDFPD_A, fmt = ASM_FMT_M12; 2326 break; 2327 case 0x4D: 2328 op = ASM_OP_LDFP8_SA, fmt = ASM_FMT_M12; 2329 break; 2330 case 0x4E: 2331 op = ASM_OP_LDFPS_SA, fmt = ASM_FMT_M12; 2332 break; 2333 case 0x4F: 2334 op = ASM_OP_LDFPD_SA, fmt = ASM_FMT_M12; 2335 break; 2336 case 0x61: 2337 op = ASM_OP_LDFP8_C_CLR, fmt = ASM_FMT_M12; 2338 break; 2339 case 0x62: 2340 op = ASM_OP_LDFPS_C_CLR, fmt = ASM_FMT_M12; 2341 break; 2342 case 0x63: 2343 op = ASM_OP_LDFPD_C_CLR, fmt = ASM_FMT_M12; 2344 break; 2345 case 0x65: 2346 op = ASM_OP_LDFP8_C_NC, fmt = ASM_FMT_M12; 2347 break; 2348 case 0x66: 2349 op = ASM_OP_LDFPS_C_NC, fmt = ASM_FMT_M12; 2350 break; 2351 case 0x67: 2352 op = ASM_OP_LDFPD_C_NC, fmt = ASM_FMT_M12; 2353 break; 2354 } 2355 } 2356 break; 2357 case 0x7: 2358 switch (FIELD(bits, 30, 6)) { /* x6 */ 2359 case 0x0: 2360 op = ASM_OP_LDFE_, fmt = ASM_FMT_M8; 2361 break; 2362 case 0x1: 2363 op = ASM_OP_LDF8_, fmt = ASM_FMT_M8; 2364 break; 2365 case 0x2: 2366 op = ASM_OP_LDFS_, fmt = ASM_FMT_M8; 2367 break; 2368 case 0x3: 2369 op = ASM_OP_LDFD_, fmt = ASM_FMT_M8; 2370 break; 2371 case 0x4: 2372 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M8; 2373 break; 2374 case 0x5: 2375 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M8; 2376 break; 2377 case 0x6: 2378 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M8; 2379 break; 2380 case 0x7: 2381 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M8; 2382 break; 2383 case 0x8: 2384 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M8; 2385 break; 2386 case 0x9: 2387 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M8; 2388 break; 2389 case 0xA: 2390 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M8; 2391 break; 2392 case 0xB: 2393 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M8; 2394 break; 2395 case 0xC: 2396 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M8; 2397 break; 2398 case 0xD: 2399 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M8; 2400 break; 2401 case 0xE: 2402 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M8; 2403 break; 2404 case 0xF: 2405 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M8; 2406 break; 2407 case 0x1B: 2408 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M8; 2409 break; 2410 case 0x20: 2411 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M8; 2412 break; 2413 case 0x21: 2414 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M8; 2415 break; 2416 case 0x22: 2417 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M8; 2418 break; 2419 case 0x23: 2420 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M8; 2421 break; 2422 case 0x24: 2423 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M8; 2424 break; 2425 case 0x25: 2426 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M8; 2427 break; 2428 case 0x26: 2429 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M8; 2430 break; 2431 case 0x27: 2432 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M8; 2433 break; 2434 case 0x2C: 2435 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M15; 2436 break; 2437 case 0x2D: 2438 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M15; 2439 break; 2440 case 0x2E: 2441 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M15; 2442 break; 2443 case 0x2F: 2444 op = ASM_OP_LFETCH_FAULT_EXCL, fmt = ASM_FMT_M15; 2445 break; 2446 case 0x30: 2447 op = ASM_OP_STFE, fmt = ASM_FMT_M10; 2448 break; 2449 case 0x31: 2450 op = ASM_OP_STF8, fmt = ASM_FMT_M10; 2451 break; 2452 case 0x32: 2453 op = ASM_OP_STFS, fmt = ASM_FMT_M10; 2454 break; 2455 case 0x33: 2456 op = ASM_OP_STFD, fmt = ASM_FMT_M10; 2457 break; 2458 case 0x3B: 2459 op = ASM_OP_STF_SPILL, fmt = ASM_FMT_M10; 2460 break; 2461 } 2462 break; 2463 } 2464 2465 if (op != ASM_OP_NONE) 2466 return (asm_extract(op, fmt, bits, b, slot)); 2467 return (0); 2468 } 2469 2470 /* 2471 * Decode X-unit instructions. 2472 */ 2473 static int 2474 asm_decodeX(uint64_t ip, struct asm_bundle *b, int slot) 2475 { 2476 uint64_t bits; 2477 enum asm_fmt fmt; 2478 enum asm_op op; 2479 2480 KASSERT(slot == 2); 2481 bits = SLOT(ip, slot); 2482 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 2483 /* Initialize slot 1 (slot - 1) */ 2484 b->b_inst[slot - 1].i_format = ASM_FMT_NONE; 2485 b->b_inst[slot - 1].i_bits = SLOT(ip, slot - 1); 2486 2487 switch((int)OPCODE(bits)) { 2488 case 0x0: 2489 if (FIELD(bits, 33, 3) == 0) { /* x3 */ 2490 switch (FIELD(bits, 27, 6)) { /* x6 */ 2491 case 0x0: 2492 op = ASM_OP_BREAK_X, fmt = ASM_FMT_X1; 2493 break; 2494 case 0x1: 2495 if (FIELD(bits, 26, 1) == 0) /* y */ 2496 op = ASM_OP_NOP_X, fmt = ASM_FMT_X5; 2497 else 2498 op = ASM_OP_HINT_X, fmt = ASM_FMT_X5; 2499 break; 2500 } 2501 } 2502 break; 2503 case 0x6: 2504 if (FIELD(bits, 20, 1) == 0) 2505 op = ASM_OP_MOVL, fmt = ASM_FMT_X2; 2506 break; 2507 case 0xC: 2508 if (FIELD(bits, 6, 3) == 0) /* btype */ 2509 op = ASM_OP_BRL_COND, fmt = ASM_FMT_X3; 2510 break; 2511 case 0xD: 2512 op = ASM_OP_BRL_CALL, fmt = ASM_FMT_X4; 2513 break; 2514 } 2515 2516 if (op != ASM_OP_NONE) 2517 return (asm_extract(op, fmt, bits, b, slot)); 2518 return (0); 2519 } 2520 2521 int 2522 asm_decode(uint64_t ip, struct asm_bundle *b) 2523 { 2524 const char *tp; 2525 unsigned int slot; 2526 int ok; 2527 2528 memset(b, 0, sizeof(*b)); 2529 2530 b->b_templ = asm_templname[TMPL(ip)]; 2531 if (b->b_templ == 0) 2532 return (0); 2533 2534 slot = 0; 2535 tp = b->b_templ; 2536 2537 ok = 1; 2538 while (ok && *tp != 0) { 2539 switch (*tp++) { 2540 case 'B': 2541 ok = asm_decodeB(ip, b, slot++); 2542 break; 2543 case 'F': 2544 ok = asm_decodeF(ip, b, slot++); 2545 break; 2546 case 'I': 2547 ok = asm_decodeI(ip, b, slot++); 2548 break; 2549 case 'L': 2550 ok = (slot++ == 1) ? 1 : 0; 2551 break; 2552 case 'M': 2553 ok = asm_decodeM(ip, b, slot++); 2554 break; 2555 case 'X': 2556 ok = asm_decodeX(ip, b, slot++); 2557 break; 2558 case ';': 2559 ok = 1; 2560 break; 2561 default: 2562 ok = 0; 2563 break; 2564 } 2565 } 2566 return (ok); 2567 } 2568
Indexes created Sat Sep 20 22:09:52 GMT 2025