1 /* $NetBSD: ast_main.c,v 1.3 2021/12/18 23:45:27 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: Dave Airlie <airlied (at) redhat.com> 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ast_main.c,v 1.3 2021/12/18 23:45:27 riastradh Exp $"); 33 34 #include <linux/pci.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <drm/drm_fb_helper.h> 39 #include <drm/drm_gem.h> 40 #include <drm/drm_gem_framebuffer_helper.h> 41 #include <drm/drm_gem_vram_helper.h> 42 43 #include "ast_drv.h" 44 45 void ast_set_index_reg_mask(struct ast_private *ast, 46 uint32_t base, uint8_t index, 47 uint8_t mask, uint8_t val) 48 { 49 u8 tmp; 50 ast_io_write8(ast, base, index); 51 tmp = (ast_io_read8(ast, base + 1) & mask) | val; 52 ast_set_index_reg(ast, base, index, tmp); 53 } 54 55 uint8_t ast_get_index_reg(struct ast_private *ast, 56 uint32_t base, uint8_t index) 57 { 58 uint8_t ret; 59 ast_io_write8(ast, base, index); 60 ret = ast_io_read8(ast, base + 1); 61 return ret; 62 } 63 64 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 65 uint32_t base, uint8_t index, uint8_t mask) 66 { 67 uint8_t ret; 68 ast_io_write8(ast, base, index); 69 ret = ast_io_read8(ast, base + 1) & mask; 70 return ret; 71 } 72 73 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) 74 { 75 struct device_node *np = dev->pdev->dev.of_node; 76 struct ast_private *ast = dev->dev_private; 77 uint32_t data, jregd0, jregd1; 78 79 /* Defaults */ 80 ast->config_mode = ast_use_defaults; 81 *scu_rev = 0xffffffff; 82 83 /* Check if we have device-tree properties */ 84 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", 85 scu_rev)) { 86 /* We do, disable P2A access */ 87 ast->config_mode = ast_use_dt; 88 DRM_INFO("Using device-tree for configuration\n"); 89 return; 90 } 91 92 /* Not all families have a P2A bridge */ 93 if (dev->pdev->device != PCI_CHIP_AST2000) 94 return; 95 96 /* 97 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 98 * is disabled. We force using P2A if VGA only mode bit 99 * is set D[7] 100 */ 101 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 102 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 103 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 104 /* Double check it's actually working */ 105 data = ast_read32(ast, 0xf004); 106 if (data != 0xFFFFFFFF) { 107 /* P2A works, grab silicon revision */ 108 ast->config_mode = ast_use_p2a; 109 110 DRM_INFO("Using P2A bridge for configuration\n"); 111 112 /* Read SCU7c (silicon revision register) */ 113 ast_write32(ast, 0xf004, 0x1e6e0000); 114 ast_write32(ast, 0xf000, 0x1); 115 *scu_rev = ast_read32(ast, 0x1207c); 116 return; 117 } 118 } 119 120 /* We have a P2A bridge but it's disabled */ 121 DRM_INFO("P2A bridge disabled, using default configuration\n"); 122 } 123 124 static int ast_detect_chip(struct drm_device *dev, bool *need_post) 125 { 126 struct ast_private *ast = dev->dev_private; 127 uint32_t jreg, scu_rev; 128 129 /* 130 * If VGA isn't enabled, we need to enable now or subsequent 131 * access to the scratch registers will fail. We also inform 132 * our caller that it needs to POST the chip 133 * (Assumption: VGA not enabled -> need to POST) 134 */ 135 if (!ast_is_vga_enabled(dev)) { 136 ast_enable_vga(dev); 137 DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); 138 *need_post = true; 139 } else 140 *need_post = false; 141 142 143 /* Enable extended register access */ 144 ast_open_key(ast); 145 ast_enable_mmio(dev); 146 147 /* Find out whether P2A works or whether to use device-tree */ 148 ast_detect_config_mode(dev, &scu_rev); 149 150 /* Identify chipset */ 151 if (dev->pdev->device == PCI_CHIP_AST1180) { 152 ast->chip = AST1100; 153 DRM_INFO("AST 1180 detected\n"); 154 } else { 155 if (dev->pdev->revision >= 0x40) { 156 ast->chip = AST2500; 157 DRM_INFO("AST 2500 detected\n"); 158 } else if (dev->pdev->revision >= 0x30) { 159 ast->chip = AST2400; 160 DRM_INFO("AST 2400 detected\n"); 161 } else if (dev->pdev->revision >= 0x20) { 162 ast->chip = AST2300; 163 DRM_INFO("AST 2300 detected\n"); 164 } else if (dev->pdev->revision >= 0x10) { 165 switch (scu_rev & 0x0300) { 166 case 0x0200: 167 ast->chip = AST1100; 168 DRM_INFO("AST 1100 detected\n"); 169 break; 170 case 0x0100: 171 ast->chip = AST2200; 172 DRM_INFO("AST 2200 detected\n"); 173 break; 174 case 0x0000: 175 ast->chip = AST2150; 176 DRM_INFO("AST 2150 detected\n"); 177 break; 178 default: 179 ast->chip = AST2100; 180 DRM_INFO("AST 2100 detected\n"); 181 break; 182 } 183 ast->vga2_clone = false; 184 } else { 185 ast->chip = AST2000; 186 DRM_INFO("AST 2000 detected\n"); 187 } 188 } 189 190 /* Check if we support wide screen */ 191 switch (ast->chip) { 192 case AST1180: 193 ast->support_wide_screen = true; 194 break; 195 case AST2000: 196 ast->support_wide_screen = false; 197 break; 198 default: 199 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 200 if (!(jreg & 0x80)) 201 ast->support_wide_screen = true; 202 else if (jreg & 0x01) 203 ast->support_wide_screen = true; 204 else { 205 ast->support_wide_screen = false; 206 if (ast->chip == AST2300 && 207 (scu_rev & 0x300) == 0x0) /* ast1300 */ 208 ast->support_wide_screen = true; 209 if (ast->chip == AST2400 && 210 (scu_rev & 0x300) == 0x100) /* ast1400 */ 211 ast->support_wide_screen = true; 212 if (ast->chip == AST2500 && 213 scu_rev == 0x100) /* ast2510 */ 214 ast->support_wide_screen = true; 215 } 216 break; 217 } 218 219 /* Check 3rd Tx option (digital output afaik) */ 220 ast->tx_chip_type = AST_TX_NONE; 221 222 /* 223 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 224 * enabled, in that case, assume we have a SIL164 TMDS transmitter 225 * 226 * Don't make that assumption if we the chip wasn't enabled and 227 * is at power-on reset, otherwise we'll incorrectly "detect" a 228 * SIL164 when there is none. 229 */ 230 if (!*need_post) { 231 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 232 if (jreg & 0x80) 233 ast->tx_chip_type = AST_TX_SIL164; 234 } 235 236 if ((ast->chip == AST2300) || (ast->chip == AST2400)) { 237 /* 238 * On AST2300 and 2400, look the configuration set by the SoC in 239 * the SOC scratch register #1 bits 11:8 (interestingly marked 240 * as "reserved" in the spec) 241 */ 242 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 243 switch (jreg) { 244 case 0x04: 245 ast->tx_chip_type = AST_TX_SIL164; 246 break; 247 case 0x08: 248 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); 249 if (ast->dp501_fw_addr) { 250 /* backup firmware */ 251 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 252 kfree(ast->dp501_fw_addr); 253 ast->dp501_fw_addr = NULL; 254 } 255 } 256 /* fallthrough */ 257 case 0x0c: 258 ast->tx_chip_type = AST_TX_DP501; 259 } 260 } 261 262 /* Print stuff for diagnostic purposes */ 263 switch(ast->tx_chip_type) { 264 case AST_TX_SIL164: 265 DRM_INFO("Using Sil164 TMDS transmitter\n"); 266 break; 267 case AST_TX_DP501: 268 DRM_INFO("Using DP501 DisplayPort transmitter\n"); 269 break; 270 default: 271 DRM_INFO("Analog VGA only\n"); 272 } 273 return 0; 274 } 275 276 static int ast_get_dram_info(struct drm_device *dev) 277 { 278 struct device_node *np = dev->pdev->dev.of_node; 279 struct ast_private *ast = dev->dev_private; 280 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 281 uint32_t denum, num, div, ref_pll, dsel; 282 283 switch (ast->config_mode) { 284 case ast_use_dt: 285 /* 286 * If some properties are missing, use reasonable 287 * defaults for AST2400 288 */ 289 if (of_property_read_u32(np, "aspeed,mcr-configuration", 290 &mcr_cfg)) 291 mcr_cfg = 0x00000577; 292 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 293 &mcr_scu_mpll)) 294 mcr_scu_mpll = 0x000050C0; 295 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 296 &mcr_scu_strap)) 297 mcr_scu_strap = 0; 298 break; 299 case ast_use_p2a: 300 ast_write32(ast, 0xf004, 0x1e6e0000); 301 ast_write32(ast, 0xf000, 0x1); 302 mcr_cfg = ast_read32(ast, 0x10004); 303 mcr_scu_mpll = ast_read32(ast, 0x10120); 304 mcr_scu_strap = ast_read32(ast, 0x10170); 305 break; 306 case ast_use_defaults: 307 default: 308 ast->dram_bus_width = 16; 309 ast->dram_type = AST_DRAM_1Gx16; 310 if (ast->chip == AST2500) 311 ast->mclk = 800; 312 else 313 ast->mclk = 396; 314 return 0; 315 } 316 317 if (mcr_cfg & 0x40) 318 ast->dram_bus_width = 16; 319 else 320 ast->dram_bus_width = 32; 321 322 if (ast->chip == AST2500) { 323 switch (mcr_cfg & 0x03) { 324 case 0: 325 ast->dram_type = AST_DRAM_1Gx16; 326 break; 327 default: 328 case 1: 329 ast->dram_type = AST_DRAM_2Gx16; 330 break; 331 case 2: 332 ast->dram_type = AST_DRAM_4Gx16; 333 break; 334 case 3: 335 ast->dram_type = AST_DRAM_8Gx16; 336 break; 337 } 338 } else if (ast->chip == AST2300 || ast->chip == AST2400) { 339 switch (mcr_cfg & 0x03) { 340 case 0: 341 ast->dram_type = AST_DRAM_512Mx16; 342 break; 343 default: 344 case 1: 345 ast->dram_type = AST_DRAM_1Gx16; 346 break; 347 case 2: 348 ast->dram_type = AST_DRAM_2Gx16; 349 break; 350 case 3: 351 ast->dram_type = AST_DRAM_4Gx16; 352 break; 353 } 354 } else { 355 switch (mcr_cfg & 0x0c) { 356 case 0: 357 case 4: 358 ast->dram_type = AST_DRAM_512Mx16; 359 break; 360 case 8: 361 if (mcr_cfg & 0x40) 362 ast->dram_type = AST_DRAM_1Gx16; 363 else 364 ast->dram_type = AST_DRAM_512Mx32; 365 break; 366 case 0xc: 367 ast->dram_type = AST_DRAM_1Gx32; 368 break; 369 } 370 } 371 372 if (mcr_scu_strap & 0x2000) 373 ref_pll = 14318; 374 else 375 ref_pll = 12000; 376 377 denum = mcr_scu_mpll & 0x1f; 378 num = (mcr_scu_mpll & 0x3fe0) >> 5; 379 dsel = (mcr_scu_mpll & 0xc000) >> 14; 380 switch (dsel) { 381 case 3: 382 div = 0x4; 383 break; 384 case 2: 385 case 1: 386 div = 0x2; 387 break; 388 default: 389 div = 0x1; 390 break; 391 } 392 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 393 return 0; 394 } 395 396 enum drm_mode_status ast_mode_config_mode_valid(struct drm_device *dev, 397 const struct drm_display_mode *mode) 398 { 399 static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGBA8888 */ 400 401 struct ast_private *ast = dev->dev_private; 402 unsigned long fbsize, fbpages, max_fbpages; 403 404 /* To support double buffering, a framebuffer may not 405 * consume more than half of the available VRAM. 406 */ 407 max_fbpages = (ast->vram_size / 2) >> PAGE_SHIFT; 408 409 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 410 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 411 412 if (fbpages > max_fbpages) 413 return MODE_MEM; 414 415 return MODE_OK; 416 } 417 418 static const struct drm_mode_config_funcs ast_mode_funcs = { 419 .fb_create = drm_gem_fb_create, 420 .mode_valid = ast_mode_config_mode_valid, 421 .atomic_check = drm_atomic_helper_check, 422 .atomic_commit = drm_atomic_helper_commit, 423 }; 424 425 static u32 ast_get_vram_info(struct drm_device *dev) 426 { 427 struct ast_private *ast = dev->dev_private; 428 u8 jreg; 429 u32 vram_size; 430 ast_open_key(ast); 431 432 vram_size = AST_VIDMEM_DEFAULT_SIZE; 433 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); 434 switch (jreg & 3) { 435 case 0: vram_size = AST_VIDMEM_SIZE_8M; break; 436 case 1: vram_size = AST_VIDMEM_SIZE_16M; break; 437 case 2: vram_size = AST_VIDMEM_SIZE_32M; break; 438 case 3: vram_size = AST_VIDMEM_SIZE_64M; break; 439 } 440 441 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); 442 switch (jreg & 0x03) { 443 case 1: 444 vram_size -= 0x100000; 445 break; 446 case 2: 447 vram_size -= 0x200000; 448 break; 449 case 3: 450 vram_size -= 0x400000; 451 break; 452 } 453 454 return vram_size; 455 } 456 457 int ast_driver_load(struct drm_device *dev, unsigned long flags) 458 { 459 struct ast_private *ast; 460 bool need_post; 461 int ret = 0; 462 463 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL); 464 if (!ast) 465 return -ENOMEM; 466 467 dev->dev_private = ast; 468 ast->dev = dev; 469 470 ast->regs = pci_iomap(dev->pdev, 1, 0); 471 if (!ast->regs) { 472 ret = -EIO; 473 goto out_free; 474 } 475 476 /* 477 * If we don't have IO space at all, use MMIO now and 478 * assume the chip has MMIO enabled by default (rev 0x20 479 * and higher). 480 */ 481 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) { 482 DRM_INFO("platform has no IO space, trying MMIO\n"); 483 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 484 } 485 486 /* "map" IO regs if the above hasn't done so already */ 487 if (!ast->ioregs) { 488 ast->ioregs = pci_iomap(dev->pdev, 2, 0); 489 if (!ast->ioregs) { 490 ret = -EIO; 491 goto out_free; 492 } 493 } 494 495 ast_detect_chip(dev, &need_post); 496 497 if (need_post) 498 ast_post_gpu(dev); 499 500 if (ast->chip != AST1180) { 501 ret = ast_get_dram_info(dev); 502 if (ret) 503 goto out_free; 504 ast->vram_size = ast_get_vram_info(dev); 505 DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", 506 ast->mclk, ast->dram_type, 507 ast->dram_bus_width, ast->vram_size); 508 } 509 510 ret = ast_mm_init(ast); 511 if (ret) 512 goto out_free; 513 514 drm_mode_config_init(dev); 515 516 dev->mode_config.funcs = (void *)&ast_mode_funcs; 517 dev->mode_config.min_width = 0; 518 dev->mode_config.min_height = 0; 519 dev->mode_config.preferred_depth = 24; 520 dev->mode_config.prefer_shadow = 1; 521 dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0); 522 523 if (ast->chip == AST2100 || 524 ast->chip == AST2200 || 525 ast->chip == AST2300 || 526 ast->chip == AST2400 || 527 ast->chip == AST2500 || 528 ast->chip == AST1180) { 529 dev->mode_config.max_width = 1920; 530 dev->mode_config.max_height = 2048; 531 } else { 532 dev->mode_config.max_width = 1600; 533 dev->mode_config.max_height = 1200; 534 } 535 536 ret = ast_mode_init(dev); 537 if (ret) 538 goto out_free; 539 540 drm_mode_config_reset(dev); 541 542 ret = drm_fbdev_generic_setup(dev, 32); 543 if (ret) 544 goto out_free; 545 546 return 0; 547 out_free: 548 kfree(ast); 549 dev->dev_private = NULL; 550 return ret; 551 } 552 553 void ast_driver_unload(struct drm_device *dev) 554 { 555 struct ast_private *ast = dev->dev_private; 556 557 /* enable standard VGA decode */ 558 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 559 560 ast_release_firmware(dev); 561 kfree(ast->dp501_fw_addr); 562 ast_mode_fini(dev); 563 drm_mode_config_cleanup(dev); 564 565 ast_mm_fini(ast); 566 if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET) 567 pci_iounmap(dev->pdev, ast->ioregs); 568 pci_iounmap(dev->pdev, ast->regs); 569 kfree(ast); 570 } 571
Indexes created Sun Sep 21 16:09:51 GMT 2025