1 /* $NetBSD: intel_display_power.h,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 /* 5 * Copyright 2019 Intel Corporation 6 */ 7 8 #ifndef __INTEL_DISPLAY_POWER_H__ 9 #define __INTEL_DISPLAY_POWER_H__ 10 11 #include "intel_display.h" 12 #include "intel_runtime_pm.h" 13 #include "i915_reg.h" 14 15 struct drm_i915_private; 16 struct intel_encoder; 17 18 enum intel_display_power_domain { 19 POWER_DOMAIN_DISPLAY_CORE, 20 POWER_DOMAIN_PIPE_A, 21 POWER_DOMAIN_PIPE_B, 22 POWER_DOMAIN_PIPE_C, 23 POWER_DOMAIN_PIPE_D, 24 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 25 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 26 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 27 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 28 POWER_DOMAIN_TRANSCODER_A, 29 POWER_DOMAIN_TRANSCODER_B, 30 POWER_DOMAIN_TRANSCODER_C, 31 POWER_DOMAIN_TRANSCODER_D, 32 POWER_DOMAIN_TRANSCODER_EDP, 33 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 34 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 35 POWER_DOMAIN_TRANSCODER_DSI_A, 36 POWER_DOMAIN_TRANSCODER_DSI_C, 37 POWER_DOMAIN_PORT_DDI_A_LANES, 38 POWER_DOMAIN_PORT_DDI_B_LANES, 39 POWER_DOMAIN_PORT_DDI_C_LANES, 40 POWER_DOMAIN_PORT_DDI_D_LANES, 41 POWER_DOMAIN_PORT_DDI_E_LANES, 42 POWER_DOMAIN_PORT_DDI_F_LANES, 43 POWER_DOMAIN_PORT_DDI_G_LANES, 44 POWER_DOMAIN_PORT_DDI_H_LANES, 45 POWER_DOMAIN_PORT_DDI_I_LANES, 46 POWER_DOMAIN_PORT_DDI_A_IO, 47 POWER_DOMAIN_PORT_DDI_B_IO, 48 POWER_DOMAIN_PORT_DDI_C_IO, 49 POWER_DOMAIN_PORT_DDI_D_IO, 50 POWER_DOMAIN_PORT_DDI_E_IO, 51 POWER_DOMAIN_PORT_DDI_F_IO, 52 POWER_DOMAIN_PORT_DDI_G_IO, 53 POWER_DOMAIN_PORT_DDI_H_IO, 54 POWER_DOMAIN_PORT_DDI_I_IO, 55 POWER_DOMAIN_PORT_DSI, 56 POWER_DOMAIN_PORT_CRT, 57 POWER_DOMAIN_PORT_OTHER, 58 POWER_DOMAIN_VGA, 59 POWER_DOMAIN_AUDIO, 60 POWER_DOMAIN_AUX_A, 61 POWER_DOMAIN_AUX_B, 62 POWER_DOMAIN_AUX_C, 63 POWER_DOMAIN_AUX_D, 64 POWER_DOMAIN_AUX_E, 65 POWER_DOMAIN_AUX_F, 66 POWER_DOMAIN_AUX_G, 67 POWER_DOMAIN_AUX_H, 68 POWER_DOMAIN_AUX_I, 69 POWER_DOMAIN_AUX_IO_A, 70 POWER_DOMAIN_AUX_C_TBT, 71 POWER_DOMAIN_AUX_D_TBT, 72 POWER_DOMAIN_AUX_E_TBT, 73 POWER_DOMAIN_AUX_F_TBT, 74 POWER_DOMAIN_AUX_G_TBT, 75 POWER_DOMAIN_AUX_H_TBT, 76 POWER_DOMAIN_AUX_I_TBT, 77 POWER_DOMAIN_GMBUS, 78 POWER_DOMAIN_MODESET, 79 POWER_DOMAIN_GT_IRQ, 80 POWER_DOMAIN_DPLL_DC_OFF, 81 POWER_DOMAIN_INIT, 82 83 POWER_DOMAIN_NUM, 84 }; 85 86 /* 87 * i915_power_well_id: 88 * 89 * IDs used to look up power wells. Power wells accessed directly bypassing 90 * the power domains framework must be assigned a unique ID. The rest of power 91 * wells must be assigned DISP_PW_ID_NONE. 92 */ 93 enum i915_power_well_id { 94 DISP_PW_ID_NONE, 95 96 VLV_DISP_PW_DISP2D, 97 BXT_DISP_PW_DPIO_CMN_A, 98 VLV_DISP_PW_DPIO_CMN_BC, 99 GLK_DISP_PW_DPIO_CMN_C, 100 CHV_DISP_PW_DPIO_CMN_D, 101 HSW_DISP_PW_GLOBAL, 102 SKL_DISP_PW_MISC_IO, 103 SKL_DISP_PW_1, 104 SKL_DISP_PW_2, 105 SKL_DISP_DC_OFF, 106 }; 107 108 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 109 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 110 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 111 #define POWER_DOMAIN_TRANSCODER(tran) \ 112 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 113 (tran) + POWER_DOMAIN_TRANSCODER_A) 114 115 struct i915_power_well; 116 117 struct i915_power_well_ops { 118 /* 119 * Synchronize the well's hw state to match the current sw state, for 120 * example enable/disable it based on the current refcount. Called 121 * during driver init and resume time, possibly after first calling 122 * the enable/disable handlers. 123 */ 124 void (*sync_hw)(struct drm_i915_private *dev_priv, 125 struct i915_power_well *power_well); 126 /* 127 * Enable the well and resources that depend on it (for example 128 * interrupts located on the well). Called after the 0->1 refcount 129 * transition. 130 */ 131 void (*enable)(struct drm_i915_private *dev_priv, 132 struct i915_power_well *power_well); 133 /* 134 * Disable the well and resources that depend on it. Called after 135 * the 1->0 refcount transition. 136 */ 137 void (*disable)(struct drm_i915_private *dev_priv, 138 struct i915_power_well *power_well); 139 /* Returns the hw enabled state. */ 140 bool (*is_enabled)(struct drm_i915_private *dev_priv, 141 struct i915_power_well *power_well); 142 }; 143 144 struct i915_power_well_regs { 145 i915_reg_t bios; 146 i915_reg_t driver; 147 i915_reg_t kvmr; 148 i915_reg_t debug; 149 }; 150 151 /* Power well structure for haswell */ 152 struct i915_power_well_desc { 153 const char *name; 154 bool always_on; 155 u64 domains; 156 /* unique identifier for this power well */ 157 enum i915_power_well_id id; 158 /* 159 * Arbitraty data associated with this power well. Platform and power 160 * well specific. 161 */ 162 union { 163 struct { 164 /* 165 * request/status flag index in the PUNIT power well 166 * control/status registers. 167 */ 168 u8 idx; 169 } vlv; 170 struct { 171 enum dpio_phy phy; 172 } bxt; 173 struct { 174 const struct i915_power_well_regs *regs; 175 /* 176 * request/status flag index in the power well 177 * constrol/status registers. 178 */ 179 u8 idx; 180 /* Mask of pipes whose IRQ logic is backed by the pw */ 181 u8 irq_pipe_mask; 182 /* The pw is backing the VGA functionality */ 183 bool has_vga:1; 184 bool has_fuses:1; 185 /* 186 * The pw is for an ICL+ TypeC PHY port in 187 * Thunderbolt mode. 188 */ 189 bool is_tc_tbt:1; 190 } hsw; 191 }; 192 const struct i915_power_well_ops *ops; 193 }; 194 195 struct i915_power_well { 196 const struct i915_power_well_desc *desc; 197 /* power well enable/disable usage count */ 198 int count; 199 /* cached hw enabled state */ 200 bool hw_enabled; 201 }; 202 203 struct i915_power_domains { 204 /* 205 * Power wells needed for initialization at driver init and suspend 206 * time are on. They are kept on until after the first modeset. 207 */ 208 bool initializing; 209 bool display_core_suspended; 210 int power_well_count; 211 212 intel_wakeref_t wakeref; 213 214 struct mutex lock; 215 int domain_use_count[POWER_DOMAIN_NUM]; 216 217 struct delayed_work async_put_work; 218 intel_wakeref_t async_put_wakeref; 219 u64 async_put_domains[2]; 220 221 struct i915_power_well *power_wells; 222 }; 223 224 #define for_each_power_domain(domain, mask) \ 225 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 226 for_each_if(BIT_ULL(domain) & (mask)) 227 228 #define for_each_power_well(__dev_priv, __power_well) \ 229 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 230 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 231 (__dev_priv)->power_domains.power_well_count; \ 232 (__power_well)++) 233 234 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 235 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 236 (__dev_priv)->power_domains.power_well_count - 1; \ 237 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 238 (__power_well)--) 239 240 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 241 for_each_power_well(__dev_priv, __power_well) \ 242 for_each_if((__power_well)->desc->domains & (__domain_mask)) 243 244 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 245 for_each_power_well_reverse(__dev_priv, __power_well) \ 246 for_each_if((__power_well)->desc->domains & (__domain_mask)) 247 248 int intel_power_domains_init(struct drm_i915_private *dev_priv); 249 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 250 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 251 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 252 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 253 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 254 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 255 enum i915_drm_suspend_mode); 256 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 257 258 void intel_display_power_suspend_late(struct drm_i915_private *i915); 259 void intel_display_power_resume_early(struct drm_i915_private *i915); 260 void intel_display_power_suspend(struct drm_i915_private *i915); 261 void intel_display_power_resume(struct drm_i915_private *i915); 262 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 263 u32 state); 264 265 const char * 266 intel_display_power_domain_str(enum intel_display_power_domain domain); 267 268 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 269 enum intel_display_power_domain domain); 270 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 271 enum intel_display_power_domain domain); 272 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 273 enum intel_display_power_domain domain); 274 intel_wakeref_t 275 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 276 enum intel_display_power_domain domain); 277 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 278 enum intel_display_power_domain domain); 279 void __intel_display_power_put_async(struct drm_i915_private *i915, 280 enum intel_display_power_domain domain, 281 intel_wakeref_t wakeref); 282 void intel_display_power_flush_work(struct drm_i915_private *i915); 283 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 284 void intel_display_power_put(struct drm_i915_private *dev_priv, 285 enum intel_display_power_domain domain, 286 intel_wakeref_t wakeref); 287 static inline void 288 intel_display_power_put_async(struct drm_i915_private *i915, 289 enum intel_display_power_domain domain, 290 intel_wakeref_t wakeref) 291 { 292 __intel_display_power_put_async(i915, domain, wakeref); 293 } 294 #else 295 static inline void 296 intel_display_power_put(struct drm_i915_private *i915, 297 enum intel_display_power_domain domain, 298 intel_wakeref_t wakeref) 299 { 300 intel_display_power_put_unchecked(i915, domain); 301 } 302 303 static inline void 304 intel_display_power_put_async(struct drm_i915_private *i915, 305 enum intel_display_power_domain domain, 306 intel_wakeref_t wakeref) 307 { 308 __intel_display_power_put_async(i915, domain, -1); 309 } 310 #endif 311 312 #define with_intel_display_power(i915, domain, wf) \ 313 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 314 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 315 316 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 317 u8 req_slices); 318 319 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 320 bool override, unsigned int mask); 321 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 322 enum dpio_channel ch, bool override); 323 324 #endif /* __INTEL_DISPLAY_POWER_H__ */ 325
Indexes created Sat Sep 20 22:09:52 GMT 2025