1 /* $NetBSD: radeon_atombios_encoders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-11 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_atombios_encoders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <linux/backlight.h> 33 #include <linux/dmi.h> 34 #include <linux/pci.h> 35 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_file.h> 38 #include <drm/radeon_drm.h> 39 40 #include "atom.h" 41 #include "radeon.h" 42 #include "radeon_asic.h" 43 #include "radeon_audio.h" 44 45 extern int atom_debug; 46 47 static u8 48 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 49 { 50 u8 backlight_level; 51 u32 bios_2_scratch; 52 53 if (rdev->family >= CHIP_R600) 54 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 55 else 56 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 57 58 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 59 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 60 61 return backlight_level; 62 } 63 64 static void 65 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 66 u8 backlight_level) 67 { 68 u32 bios_2_scratch; 69 70 if (rdev->family >= CHIP_R600) 71 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 72 else 73 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 74 75 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 76 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 77 ATOM_S2_CURRENT_BL_LEVEL_MASK); 78 79 if (rdev->family >= CHIP_R600) 80 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 81 else 82 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 83 } 84 85 u8 86 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 87 { 88 struct drm_device *dev = radeon_encoder->base.dev; 89 struct radeon_device *rdev = dev->dev_private; 90 91 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 92 return 0; 93 94 return radeon_atom_get_backlight_level_from_reg(rdev); 95 } 96 97 void 98 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 99 { 100 struct drm_encoder *encoder = &radeon_encoder->base; 101 struct drm_device *dev = radeon_encoder->base.dev; 102 struct radeon_device *rdev = dev->dev_private; 103 struct radeon_encoder_atom_dig *dig; 104 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 105 int index; 106 107 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 108 return; 109 110 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 111 radeon_encoder->enc_priv) { 112 dig = radeon_encoder->enc_priv; 113 dig->backlight_level = level; 114 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 115 116 switch (radeon_encoder->encoder_id) { 117 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 118 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 119 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 120 if (dig->backlight_level == 0) { 121 args.ucAction = ATOM_LCD_BLOFF; 122 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 123 } else { 124 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 125 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 126 args.ucAction = ATOM_LCD_BLON; 127 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 128 } 129 break; 130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 131 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 133 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 135 if (dig->backlight_level == 0) 136 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 137 else { 138 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 139 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 140 } 141 break; 142 default: 143 break; 144 } 145 } 146 } 147 148 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) || IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 149 150 static u8 radeon_atom_bl_level(struct backlight_device *bd) 151 { 152 u8 level; 153 154 /* Convert brightness to hardware level */ 155 if (bd->props.brightness < 0) 156 level = 0; 157 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 158 level = RADEON_MAX_BL_LEVEL; 159 else 160 level = bd->props.brightness; 161 162 return level; 163 } 164 165 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 166 { 167 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 168 struct radeon_encoder *radeon_encoder = pdata->encoder; 169 170 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 171 172 return 0; 173 } 174 175 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 176 { 177 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 178 struct radeon_encoder *radeon_encoder = pdata->encoder; 179 struct drm_device *dev = radeon_encoder->base.dev; 180 struct radeon_device *rdev = dev->dev_private; 181 182 return radeon_atom_get_backlight_level_from_reg(rdev); 183 } 184 185 static const struct backlight_ops radeon_atom_backlight_ops = { 186 .get_brightness = radeon_atom_backlight_get_brightness, 187 .update_status = radeon_atom_backlight_update_status, 188 }; 189 190 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 191 struct drm_connector *drm_connector) 192 { 193 struct drm_device *dev = radeon_encoder->base.dev; 194 struct radeon_device *rdev = dev->dev_private; 195 struct backlight_device *bd; 196 struct backlight_properties props; 197 struct radeon_backlight_privdata *pdata; 198 struct radeon_encoder_atom_dig *dig; 199 char bl_name[16]; 200 201 /* Mac laptops with multiple GPUs use the gmux driver for backlight 202 * so don't register a backlight device 203 */ 204 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 205 (rdev->pdev->device == 0x6741)) 206 return; 207 208 if (!radeon_encoder->enc_priv) 209 return; 210 211 if (!rdev->is_atom_bios) 212 return; 213 214 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 215 return; 216 217 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 218 if (!pdata) { 219 DRM_ERROR("Memory allocation failed\n"); 220 goto error; 221 } 222 223 memset(&props, 0, sizeof(props)); 224 props.max_brightness = RADEON_MAX_BL_LEVEL; 225 props.type = BACKLIGHT_RAW; 226 snprintf(bl_name, sizeof(bl_name), 227 "radeon_bl%d", dev->primary->index); 228 bd = backlight_device_register(bl_name, drm_connector->kdev, 229 pdata, &radeon_atom_backlight_ops, &props); 230 if (IS_ERR(bd)) { 231 DRM_ERROR("Backlight registration failed\n"); 232 goto error; 233 } 234 235 pdata->encoder = radeon_encoder; 236 237 dig = radeon_encoder->enc_priv; 238 dig->bl_dev = bd; 239 240 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 241 /* Set a reasonable default here if the level is 0 otherwise 242 * fbdev will attempt to turn the backlight on after console 243 * unblanking and it will try and restore 0 which turns the backlight 244 * off again. 245 */ 246 if (bd->props.brightness == 0) 247 bd->props.brightness = RADEON_MAX_BL_LEVEL; 248 bd->props.power = FB_BLANK_UNBLANK; 249 backlight_update_status(bd); 250 251 DRM_INFO("radeon atom DIG backlight initialized\n"); 252 rdev->mode_info.bl_encoder = radeon_encoder; 253 254 return; 255 256 error: 257 kfree(pdata); 258 return; 259 } 260 261 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 262 { 263 struct drm_device *dev = radeon_encoder->base.dev; 264 struct radeon_device *rdev = dev->dev_private; 265 struct backlight_device *bd = NULL; 266 struct radeon_encoder_atom_dig *dig; 267 268 if (!radeon_encoder->enc_priv) 269 return; 270 271 if (!rdev->is_atom_bios) 272 return; 273 274 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 275 return; 276 277 dig = radeon_encoder->enc_priv; 278 bd = dig->bl_dev; 279 dig->bl_dev = NULL; 280 281 if (bd) { 282 struct radeon_legacy_backlight_privdata *pdata; 283 284 pdata = bl_get_data(bd); 285 backlight_device_unregister(bd); 286 kfree(pdata); 287 288 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 289 } 290 } 291 292 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 293 294 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 295 { 296 } 297 298 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 299 { 300 } 301 302 #endif 303 304 /* evil but including atombios.h is much worse */ 305 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 306 struct drm_display_mode *mode); 307 308 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 309 const struct drm_display_mode *mode, 310 struct drm_display_mode *adjusted_mode) 311 { 312 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 313 struct drm_device *dev = encoder->dev; 314 struct radeon_device *rdev = dev->dev_private; 315 316 /* set the active encoder to connector routing */ 317 radeon_encoder_set_active_device(encoder); 318 drm_mode_set_crtcinfo(adjusted_mode, 0); 319 320 /* hw bug */ 321 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 322 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 323 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 324 325 /* vertical FP must be at least 1 */ 326 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 327 adjusted_mode->crtc_vsync_start++; 328 329 /* get the native mode for scaling */ 330 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 331 radeon_panel_mode_fixup(encoder, adjusted_mode); 332 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 333 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 334 if (tv_dac) { 335 if (tv_dac->tv_std == TV_STD_NTSC || 336 tv_dac->tv_std == TV_STD_NTSC_J || 337 tv_dac->tv_std == TV_STD_PAL_M) 338 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 339 else 340 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 341 } 342 } else if (radeon_encoder->rmx_type != RMX_OFF) { 343 radeon_panel_mode_fixup(encoder, adjusted_mode); 344 } 345 346 if (ASIC_IS_DCE3(rdev) && 347 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 348 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 349 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 350 radeon_dp_set_link_config(connector, adjusted_mode); 351 } 352 353 return true; 354 } 355 356 static void 357 atombios_dac_setup(struct drm_encoder *encoder, int action) 358 { 359 struct drm_device *dev = encoder->dev; 360 struct radeon_device *rdev = dev->dev_private; 361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 362 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 363 int index = 0; 364 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 365 366 memset(&args, 0, sizeof(args)); 367 368 switch (radeon_encoder->encoder_id) { 369 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 370 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 371 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 372 break; 373 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 374 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 375 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 376 break; 377 } 378 379 args.ucAction = action; 380 381 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 382 args.ucDacStandard = ATOM_DAC1_PS2; 383 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 384 args.ucDacStandard = ATOM_DAC1_CV; 385 else { 386 switch (dac_info->tv_std) { 387 case TV_STD_PAL: 388 case TV_STD_PAL_M: 389 case TV_STD_SCART_PAL: 390 case TV_STD_SECAM: 391 case TV_STD_PAL_CN: 392 args.ucDacStandard = ATOM_DAC1_PAL; 393 break; 394 case TV_STD_NTSC: 395 case TV_STD_NTSC_J: 396 case TV_STD_PAL_60: 397 default: 398 args.ucDacStandard = ATOM_DAC1_NTSC; 399 break; 400 } 401 } 402 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 403 404 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 405 406 } 407 408 static void 409 atombios_tv_setup(struct drm_encoder *encoder, int action) 410 { 411 struct drm_device *dev = encoder->dev; 412 struct radeon_device *rdev = dev->dev_private; 413 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 414 TV_ENCODER_CONTROL_PS_ALLOCATION args; 415 int index = 0; 416 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 417 418 memset(&args, 0, sizeof(args)); 419 420 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 421 422 args.sTVEncoder.ucAction = action; 423 424 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 425 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 426 else { 427 switch (dac_info->tv_std) { 428 case TV_STD_NTSC: 429 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 430 break; 431 case TV_STD_PAL: 432 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 433 break; 434 case TV_STD_PAL_M: 435 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 436 break; 437 case TV_STD_PAL_60: 438 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 439 break; 440 case TV_STD_NTSC_J: 441 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 442 break; 443 case TV_STD_SCART_PAL: 444 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 445 break; 446 case TV_STD_SECAM: 447 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 448 break; 449 case TV_STD_PAL_CN: 450 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 451 break; 452 default: 453 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 454 break; 455 } 456 } 457 458 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 459 460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 461 462 } 463 464 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 465 { 466 int bpc = 8; 467 468 if (encoder->crtc) { 469 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 470 bpc = radeon_crtc->bpc; 471 } 472 473 switch (bpc) { 474 case 0: 475 return PANEL_BPC_UNDEFINE; 476 case 6: 477 return PANEL_6BIT_PER_COLOR; 478 case 8: 479 default: 480 return PANEL_8BIT_PER_COLOR; 481 case 10: 482 return PANEL_10BIT_PER_COLOR; 483 case 12: 484 return PANEL_12BIT_PER_COLOR; 485 case 16: 486 return PANEL_16BIT_PER_COLOR; 487 } 488 } 489 490 union dvo_encoder_control { 491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 495 }; 496 497 void 498 atombios_dvo_setup(struct drm_encoder *encoder, int action) 499 { 500 struct drm_device *dev = encoder->dev; 501 struct radeon_device *rdev = dev->dev_private; 502 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 503 union dvo_encoder_control args; 504 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 505 uint8_t frev, crev; 506 507 memset(&args, 0, sizeof(args)); 508 509 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 510 return; 511 512 /* some R4xx chips have the wrong frev */ 513 if (rdev->family <= CHIP_RV410) 514 frev = 1; 515 516 switch (frev) { 517 case 1: 518 switch (crev) { 519 case 1: 520 /* R4xx, R5xx */ 521 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 522 523 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 524 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 525 526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 527 break; 528 case 2: 529 /* RS600/690/740 */ 530 args.dvo.sDVOEncoder.ucAction = action; 531 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 532 /* DFP1, CRT1, TV1 depending on the type of port */ 533 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 534 535 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 536 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 537 break; 538 case 3: 539 /* R6xx */ 540 args.dvo_v3.ucAction = action; 541 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 542 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 543 break; 544 case 4: 545 /* DCE8 */ 546 args.dvo_v4.ucAction = action; 547 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 548 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 549 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 550 break; 551 default: 552 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 553 break; 554 } 555 break; 556 default: 557 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 558 break; 559 } 560 561 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 562 } 563 564 union lvds_encoder_control { 565 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 566 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 567 }; 568 569 void 570 atombios_digital_setup(struct drm_encoder *encoder, int action) 571 { 572 struct drm_device *dev = encoder->dev; 573 struct radeon_device *rdev = dev->dev_private; 574 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 576 union lvds_encoder_control args; 577 int index = 0; 578 int hdmi_detected = 0; 579 uint8_t frev, crev; 580 581 if (!dig) 582 return; 583 584 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 585 hdmi_detected = 1; 586 587 memset(&args, 0, sizeof(args)); 588 589 switch (radeon_encoder->encoder_id) { 590 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 592 break; 593 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 595 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 596 break; 597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 599 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 600 else 601 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 602 break; 603 } 604 605 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 606 return; 607 608 switch (frev) { 609 case 1: 610 case 2: 611 switch (crev) { 612 case 1: 613 args.v1.ucMisc = 0; 614 args.v1.ucAction = action; 615 if (hdmi_detected) 616 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 617 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 618 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 619 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 620 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 621 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 622 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 623 } else { 624 if (dig->linkb) 625 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 626 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 627 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 628 /*if (pScrn->rgbBits == 8) */ 629 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 630 } 631 break; 632 case 2: 633 case 3: 634 args.v2.ucMisc = 0; 635 args.v2.ucAction = action; 636 if (crev == 3) { 637 if (dig->coherent_mode) 638 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 639 } 640 if (hdmi_detected) 641 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 642 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 643 args.v2.ucTruncate = 0; 644 args.v2.ucSpatial = 0; 645 args.v2.ucTemporal = 0; 646 args.v2.ucFRC = 0; 647 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 648 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 650 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 651 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 652 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 653 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 654 } 655 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 656 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 657 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 658 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 659 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 660 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 661 } 662 } else { 663 if (dig->linkb) 664 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 665 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 666 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 667 } 668 break; 669 default: 670 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 671 break; 672 } 673 break; 674 default: 675 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 676 break; 677 } 678 679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 680 } 681 682 int 683 atombios_get_encoder_mode(struct drm_encoder *encoder) 684 { 685 struct drm_device *dev = encoder->dev; 686 struct radeon_device *rdev = dev->dev_private; 687 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 688 struct drm_connector *connector; 689 struct radeon_connector *radeon_connector; 690 struct radeon_connector_atom_dig *dig_connector; 691 struct radeon_encoder_atom_dig *dig_enc; 692 693 if (radeon_encoder_is_digital(encoder)) { 694 dig_enc = radeon_encoder->enc_priv; 695 if (dig_enc->active_mst_links) 696 return ATOM_ENCODER_MODE_DP_MST; 697 } 698 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) 699 return ATOM_ENCODER_MODE_DP_MST; 700 /* dp bridges are always DP */ 701 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 702 return ATOM_ENCODER_MODE_DP; 703 704 /* DVO is always DVO */ 705 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 706 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 707 return ATOM_ENCODER_MODE_DVO; 708 709 connector = radeon_get_connector_for_encoder(encoder); 710 /* if we don't have an active device yet, just use one of 711 * the connectors tied to the encoder. 712 */ 713 if (!connector) 714 connector = radeon_get_connector_for_encoder_init(encoder); 715 radeon_connector = to_radeon_connector(connector); 716 717 switch (connector->connector_type) { 718 case DRM_MODE_CONNECTOR_DVII: 719 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 720 if (radeon_audio != 0) { 721 if (radeon_connector->use_digital && 722 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 723 return ATOM_ENCODER_MODE_HDMI; 724 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 725 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 726 return ATOM_ENCODER_MODE_HDMI; 727 else if (radeon_connector->use_digital) 728 return ATOM_ENCODER_MODE_DVI; 729 else 730 return ATOM_ENCODER_MODE_CRT; 731 } else if (radeon_connector->use_digital) { 732 return ATOM_ENCODER_MODE_DVI; 733 } else { 734 return ATOM_ENCODER_MODE_CRT; 735 } 736 break; 737 case DRM_MODE_CONNECTOR_DVID: 738 case DRM_MODE_CONNECTOR_HDMIA: 739 default: 740 if (radeon_audio != 0) { 741 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 742 return ATOM_ENCODER_MODE_HDMI; 743 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 744 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 745 return ATOM_ENCODER_MODE_HDMI; 746 else 747 return ATOM_ENCODER_MODE_DVI; 748 } else { 749 return ATOM_ENCODER_MODE_DVI; 750 } 751 break; 752 case DRM_MODE_CONNECTOR_LVDS: 753 return ATOM_ENCODER_MODE_LVDS; 754 break; 755 case DRM_MODE_CONNECTOR_DisplayPort: 756 dig_connector = radeon_connector->con_priv; 757 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 758 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 759 if (radeon_audio != 0 && 760 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 761 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 762 return ATOM_ENCODER_MODE_DP_AUDIO; 763 return ATOM_ENCODER_MODE_DP; 764 } else if (radeon_audio != 0) { 765 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 766 return ATOM_ENCODER_MODE_HDMI; 767 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 768 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 769 return ATOM_ENCODER_MODE_HDMI; 770 else 771 return ATOM_ENCODER_MODE_DVI; 772 } else { 773 return ATOM_ENCODER_MODE_DVI; 774 } 775 break; 776 case DRM_MODE_CONNECTOR_eDP: 777 if (radeon_audio != 0 && 778 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 779 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 780 return ATOM_ENCODER_MODE_DP_AUDIO; 781 return ATOM_ENCODER_MODE_DP; 782 case DRM_MODE_CONNECTOR_DVIA: 783 case DRM_MODE_CONNECTOR_VGA: 784 return ATOM_ENCODER_MODE_CRT; 785 break; 786 case DRM_MODE_CONNECTOR_Composite: 787 case DRM_MODE_CONNECTOR_SVIDEO: 788 case DRM_MODE_CONNECTOR_9PinDIN: 789 /* fix me */ 790 return ATOM_ENCODER_MODE_TV; 791 /*return ATOM_ENCODER_MODE_CV;*/ 792 break; 793 } 794 } 795 796 /* 797 * DIG Encoder/Transmitter Setup 798 * 799 * DCE 3.0/3.1 800 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 801 * Supports up to 3 digital outputs 802 * - 2 DIG encoder blocks. 803 * DIG1 can drive UNIPHY link A or link B 804 * DIG2 can drive UNIPHY link B or LVTMA 805 * 806 * DCE 3.2 807 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 808 * Supports up to 5 digital outputs 809 * - 2 DIG encoder blocks. 810 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 811 * 812 * DCE 4.0/5.0/6.0 813 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 814 * Supports up to 6 digital outputs 815 * - 6 DIG encoder blocks. 816 * - DIG to PHY mapping is hardcoded 817 * DIG1 drives UNIPHY0 link A, A+B 818 * DIG2 drives UNIPHY0 link B 819 * DIG3 drives UNIPHY1 link A, A+B 820 * DIG4 drives UNIPHY1 link B 821 * DIG5 drives UNIPHY2 link A, A+B 822 * DIG6 drives UNIPHY2 link B 823 * 824 * DCE 4.1 825 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 826 * Supports up to 6 digital outputs 827 * - 2 DIG encoder blocks. 828 * llano 829 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 830 * ontario 831 * DIG1 drives UNIPHY0/1/2 link A 832 * DIG2 drives UNIPHY0/1/2 link B 833 * 834 * Routing 835 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 836 * Examples: 837 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 838 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 839 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 840 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 841 */ 842 843 union dig_encoder_control { 844 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 845 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 846 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 847 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 848 }; 849 850 void 851 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 852 { 853 struct drm_device *dev = encoder->dev; 854 struct radeon_device *rdev = dev->dev_private; 855 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 856 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 857 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 858 union dig_encoder_control args; 859 int index = 0; 860 uint8_t frev, crev; 861 int dp_clock = 0; 862 int dp_lane_count = 0; 863 int hpd_id = RADEON_HPD_NONE; 864 865 if (connector) { 866 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 867 struct radeon_connector_atom_dig *dig_connector = 868 radeon_connector->con_priv; 869 870 dp_clock = dig_connector->dp_clock; 871 dp_lane_count = dig_connector->dp_lane_count; 872 hpd_id = radeon_connector->hpd.hpd; 873 } 874 875 /* no dig encoder assigned */ 876 if (dig->dig_encoder == -1) 877 return; 878 879 memset(&args, 0, sizeof(args)); 880 881 if (ASIC_IS_DCE4(rdev)) 882 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 883 else { 884 if (dig->dig_encoder) 885 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 886 else 887 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 888 } 889 890 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 891 return; 892 893 switch (frev) { 894 case 1: 895 switch (crev) { 896 case 1: 897 args.v1.ucAction = action; 898 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 899 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 900 args.v3.ucPanelMode = panel_mode; 901 else 902 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 903 904 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 905 args.v1.ucLaneNum = dp_lane_count; 906 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 907 args.v1.ucLaneNum = 8; 908 else 909 args.v1.ucLaneNum = 4; 910 911 switch (radeon_encoder->encoder_id) { 912 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 914 break; 915 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 917 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 918 break; 919 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 920 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 921 break; 922 } 923 if (dig->linkb) 924 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 925 else 926 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 927 928 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 929 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 930 931 break; 932 case 2: 933 case 3: 934 args.v3.ucAction = action; 935 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 936 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 937 args.v3.ucPanelMode = panel_mode; 938 else 939 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 940 941 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 942 args.v3.ucLaneNum = dp_lane_count; 943 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 944 args.v3.ucLaneNum = 8; 945 else 946 args.v3.ucLaneNum = 4; 947 948 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 949 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 950 if (enc_override != -1) 951 args.v3.acConfig.ucDigSel = enc_override; 952 else 953 args.v3.acConfig.ucDigSel = dig->dig_encoder; 954 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 955 break; 956 case 4: 957 args.v4.ucAction = action; 958 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 959 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 960 args.v4.ucPanelMode = panel_mode; 961 else 962 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 963 964 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 965 args.v4.ucLaneNum = dp_lane_count; 966 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 967 args.v4.ucLaneNum = 8; 968 else 969 args.v4.ucLaneNum = 4; 970 971 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 972 if (dp_clock == 540000) 973 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 974 else if (dp_clock == 324000) 975 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 976 else if (dp_clock == 270000) 977 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 978 else 979 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 980 } 981 982 if (enc_override != -1) 983 args.v4.acConfig.ucDigSel = enc_override; 984 else 985 args.v4.acConfig.ucDigSel = dig->dig_encoder; 986 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 987 if (hpd_id == RADEON_HPD_NONE) 988 args.v4.ucHPD_ID = 0; 989 else 990 args.v4.ucHPD_ID = hpd_id + 1; 991 break; 992 default: 993 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 994 break; 995 } 996 break; 997 default: 998 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 999 break; 1000 } 1001 1002 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1003 1004 } 1005 1006 void 1007 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 1008 { 1009 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 1010 } 1011 1012 union dig_transmitter_control { 1013 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1014 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1015 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1016 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1017 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1018 }; 1019 1020 void 1021 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1022 { 1023 struct drm_device *dev = encoder->dev; 1024 struct radeon_device *rdev = dev->dev_private; 1025 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1026 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1027 struct drm_connector *connector; 1028 union dig_transmitter_control args; 1029 int index = 0; 1030 uint8_t frev, crev; 1031 bool is_dp = false; 1032 int pll_id = 0; 1033 int dp_clock = 0; 1034 int dp_lane_count = 0; 1035 int connector_object_id = 0; 1036 int igp_lane_info = 0; 1037 int dig_encoder = dig->dig_encoder; 1038 int hpd_id = RADEON_HPD_NONE; 1039 1040 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1041 connector = radeon_get_connector_for_encoder_init(encoder); 1042 /* just needed to avoid bailing in the encoder check. the encoder 1043 * isn't used for init 1044 */ 1045 dig_encoder = 0; 1046 } else 1047 connector = radeon_get_connector_for_encoder(encoder); 1048 1049 if (connector) { 1050 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1051 struct radeon_connector_atom_dig *dig_connector = 1052 radeon_connector->con_priv; 1053 1054 hpd_id = radeon_connector->hpd.hpd; 1055 dp_clock = dig_connector->dp_clock; 1056 dp_lane_count = dig_connector->dp_lane_count; 1057 connector_object_id = 1058 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1059 igp_lane_info = dig_connector->igp_lane_info; 1060 } 1061 1062 if (encoder->crtc) { 1063 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1064 pll_id = radeon_crtc->pll_id; 1065 } 1066 1067 /* no dig encoder assigned */ 1068 if (dig_encoder == -1) 1069 return; 1070 1071 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1072 is_dp = true; 1073 1074 memset(&args, 0, sizeof(args)); 1075 1076 switch (radeon_encoder->encoder_id) { 1077 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1078 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1079 break; 1080 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1081 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1083 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1084 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1085 break; 1086 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1087 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1088 break; 1089 } 1090 1091 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1092 return; 1093 1094 switch (frev) { 1095 case 1: 1096 switch (crev) { 1097 case 1: 1098 args.v1.ucAction = action; 1099 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1100 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1101 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1102 args.v1.asMode.ucLaneSel = lane_num; 1103 args.v1.asMode.ucLaneSet = lane_set; 1104 } else { 1105 if (is_dp) 1106 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1107 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1108 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1109 else 1110 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1111 } 1112 1113 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1114 1115 if (dig_encoder) 1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1117 else 1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1119 1120 if ((rdev->flags & RADEON_IS_IGP) && 1121 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1122 if (is_dp || 1123 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1124 if (igp_lane_info & 0x1) 1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1126 else if (igp_lane_info & 0x2) 1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1128 else if (igp_lane_info & 0x4) 1129 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1130 else if (igp_lane_info & 0x8) 1131 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1132 } else { 1133 if (igp_lane_info & 0x3) 1134 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1135 else if (igp_lane_info & 0xc) 1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1137 } 1138 } 1139 1140 if (dig->linkb) 1141 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1142 else 1143 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1144 1145 if (is_dp) 1146 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1147 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1148 if (dig->coherent_mode) 1149 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1150 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1151 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1152 } 1153 break; 1154 case 2: 1155 args.v2.ucAction = action; 1156 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1157 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1158 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1159 args.v2.asMode.ucLaneSel = lane_num; 1160 args.v2.asMode.ucLaneSet = lane_set; 1161 } else { 1162 if (is_dp) 1163 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1164 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1165 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1166 else 1167 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1168 } 1169 1170 args.v2.acConfig.ucEncoderSel = dig_encoder; 1171 if (dig->linkb) 1172 args.v2.acConfig.ucLinkSel = 1; 1173 1174 switch (radeon_encoder->encoder_id) { 1175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1176 args.v2.acConfig.ucTransmitterSel = 0; 1177 break; 1178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1179 args.v2.acConfig.ucTransmitterSel = 1; 1180 break; 1181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1182 args.v2.acConfig.ucTransmitterSel = 2; 1183 break; 1184 } 1185 1186 if (is_dp) { 1187 args.v2.acConfig.fCoherentMode = 1; 1188 args.v2.acConfig.fDPConnector = 1; 1189 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1190 if (dig->coherent_mode) 1191 args.v2.acConfig.fCoherentMode = 1; 1192 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1193 args.v2.acConfig.fDualLinkConnector = 1; 1194 } 1195 break; 1196 case 3: 1197 args.v3.ucAction = action; 1198 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1199 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1200 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1201 args.v3.asMode.ucLaneSel = lane_num; 1202 args.v3.asMode.ucLaneSet = lane_set; 1203 } else { 1204 if (is_dp) 1205 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1206 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1207 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1208 else 1209 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1210 } 1211 1212 if (is_dp) 1213 args.v3.ucLaneNum = dp_lane_count; 1214 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1215 args.v3.ucLaneNum = 8; 1216 else 1217 args.v3.ucLaneNum = 4; 1218 1219 if (dig->linkb) 1220 args.v3.acConfig.ucLinkSel = 1; 1221 if (dig_encoder & 1) 1222 args.v3.acConfig.ucEncoderSel = 1; 1223 1224 /* Select the PLL for the PHY 1225 * DP PHY should be clocked from external src if there is 1226 * one. 1227 */ 1228 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1229 if (is_dp && rdev->clock.dp_extclk) 1230 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1231 else 1232 args.v3.acConfig.ucRefClkSource = pll_id; 1233 1234 switch (radeon_encoder->encoder_id) { 1235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1236 args.v3.acConfig.ucTransmitterSel = 0; 1237 break; 1238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1239 args.v3.acConfig.ucTransmitterSel = 1; 1240 break; 1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1242 args.v3.acConfig.ucTransmitterSel = 2; 1243 break; 1244 } 1245 1246 if (is_dp) 1247 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1248 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1249 if (dig->coherent_mode) 1250 args.v3.acConfig.fCoherentMode = 1; 1251 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1252 args.v3.acConfig.fDualLinkConnector = 1; 1253 } 1254 break; 1255 case 4: 1256 args.v4.ucAction = action; 1257 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1258 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1259 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1260 args.v4.asMode.ucLaneSel = lane_num; 1261 args.v4.asMode.ucLaneSet = lane_set; 1262 } else { 1263 if (is_dp) 1264 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1265 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1266 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1267 else 1268 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1269 } 1270 1271 if (is_dp) 1272 args.v4.ucLaneNum = dp_lane_count; 1273 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1274 args.v4.ucLaneNum = 8; 1275 else 1276 args.v4.ucLaneNum = 4; 1277 1278 if (dig->linkb) 1279 args.v4.acConfig.ucLinkSel = 1; 1280 if (dig_encoder & 1) 1281 args.v4.acConfig.ucEncoderSel = 1; 1282 1283 /* Select the PLL for the PHY 1284 * DP PHY should be clocked from external src if there is 1285 * one. 1286 */ 1287 /* On DCE5 DCPLL usually generates the DP ref clock */ 1288 if (is_dp) { 1289 if (rdev->clock.dp_extclk) 1290 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1291 else 1292 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1293 } else 1294 args.v4.acConfig.ucRefClkSource = pll_id; 1295 1296 switch (radeon_encoder->encoder_id) { 1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1298 args.v4.acConfig.ucTransmitterSel = 0; 1299 break; 1300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1301 args.v4.acConfig.ucTransmitterSel = 1; 1302 break; 1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1304 args.v4.acConfig.ucTransmitterSel = 2; 1305 break; 1306 } 1307 1308 if (is_dp) 1309 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1310 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1311 if (dig->coherent_mode) 1312 args.v4.acConfig.fCoherentMode = 1; 1313 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1314 args.v4.acConfig.fDualLinkConnector = 1; 1315 } 1316 break; 1317 case 5: 1318 args.v5.ucAction = action; 1319 if (is_dp) 1320 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1321 else 1322 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1323 1324 switch (radeon_encoder->encoder_id) { 1325 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1326 if (dig->linkb) 1327 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1328 else 1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1330 break; 1331 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1332 if (dig->linkb) 1333 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1334 else 1335 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1336 break; 1337 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1338 if (dig->linkb) 1339 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1340 else 1341 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1342 break; 1343 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1344 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1345 break; 1346 } 1347 if (is_dp) 1348 args.v5.ucLaneNum = dp_lane_count; 1349 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1350 args.v5.ucLaneNum = 8; 1351 else 1352 args.v5.ucLaneNum = 4; 1353 args.v5.ucConnObjId = connector_object_id; 1354 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1355 1356 if (is_dp && rdev->clock.dp_extclk) 1357 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1358 else 1359 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1360 1361 if (is_dp) 1362 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1363 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1364 if (dig->coherent_mode) 1365 args.v5.asConfig.ucCoherentMode = 1; 1366 } 1367 if (hpd_id == RADEON_HPD_NONE) 1368 args.v5.asConfig.ucHPDSel = 0; 1369 else 1370 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1371 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1372 args.v5.ucDPLaneSet = lane_set; 1373 break; 1374 default: 1375 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1376 break; 1377 } 1378 break; 1379 default: 1380 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1381 break; 1382 } 1383 1384 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1385 } 1386 1387 void 1388 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1389 { 1390 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1391 } 1392 1393 bool 1394 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1395 { 1396 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1397 struct drm_device *dev = radeon_connector->base.dev; 1398 struct radeon_device *rdev = dev->dev_private; 1399 union dig_transmitter_control args; 1400 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1401 uint8_t frev, crev; 1402 1403 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1404 goto done; 1405 1406 if (!ASIC_IS_DCE4(rdev)) 1407 goto done; 1408 1409 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1410 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1411 goto done; 1412 1413 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1414 goto done; 1415 1416 memset(&args, 0, sizeof(args)); 1417 1418 args.v1.ucAction = action; 1419 1420 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1421 1422 /* wait for the panel to power up */ 1423 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1424 int i; 1425 1426 for (i = 0; i < 300; i++) { 1427 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1428 return true; 1429 mdelay(1); 1430 } 1431 return false; 1432 } 1433 done: 1434 return true; 1435 } 1436 1437 union external_encoder_control { 1438 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1439 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1440 }; 1441 1442 static void 1443 atombios_external_encoder_setup(struct drm_encoder *encoder, 1444 struct drm_encoder *ext_encoder, 1445 int action) 1446 { 1447 struct drm_device *dev = encoder->dev; 1448 struct radeon_device *rdev = dev->dev_private; 1449 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1450 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1451 union external_encoder_control args; 1452 struct drm_connector *connector; 1453 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1454 u8 frev, crev; 1455 int dp_clock = 0; 1456 int dp_lane_count = 0; 1457 int connector_object_id = 0; 1458 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1459 1460 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1461 connector = radeon_get_connector_for_encoder_init(encoder); 1462 else 1463 connector = radeon_get_connector_for_encoder(encoder); 1464 1465 if (connector) { 1466 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1467 struct radeon_connector_atom_dig *dig_connector = 1468 radeon_connector->con_priv; 1469 1470 dp_clock = dig_connector->dp_clock; 1471 dp_lane_count = dig_connector->dp_lane_count; 1472 connector_object_id = 1473 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1474 } 1475 1476 memset(&args, 0, sizeof(args)); 1477 1478 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1479 return; 1480 1481 switch (frev) { 1482 case 1: 1483 /* no params on frev 1 */ 1484 break; 1485 case 2: 1486 switch (crev) { 1487 case 1: 1488 case 2: 1489 args.v1.sDigEncoder.ucAction = action; 1490 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1491 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1492 1493 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1494 if (dp_clock == 270000) 1495 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1496 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1497 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1498 args.v1.sDigEncoder.ucLaneNum = 8; 1499 else 1500 args.v1.sDigEncoder.ucLaneNum = 4; 1501 break; 1502 case 3: 1503 args.v3.sExtEncoder.ucAction = action; 1504 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1505 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1506 else 1507 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1508 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1509 1510 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1511 if (dp_clock == 270000) 1512 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1513 else if (dp_clock == 540000) 1514 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1515 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1516 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1517 args.v3.sExtEncoder.ucLaneNum = 8; 1518 else 1519 args.v3.sExtEncoder.ucLaneNum = 4; 1520 switch (ext_enum) { 1521 case GRAPH_OBJECT_ENUM_ID1: 1522 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1523 break; 1524 case GRAPH_OBJECT_ENUM_ID2: 1525 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1526 break; 1527 case GRAPH_OBJECT_ENUM_ID3: 1528 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1529 break; 1530 } 1531 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1532 break; 1533 default: 1534 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1535 return; 1536 } 1537 break; 1538 default: 1539 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1540 return; 1541 } 1542 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1543 } 1544 1545 static void 1546 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1547 { 1548 struct drm_device *dev = encoder->dev; 1549 struct radeon_device *rdev = dev->dev_private; 1550 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1551 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1552 ENABLE_YUV_PS_ALLOCATION args; 1553 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1554 uint32_t temp, reg; 1555 1556 memset(&args, 0, sizeof(args)); 1557 1558 if (rdev->family >= CHIP_R600) 1559 reg = R600_BIOS_3_SCRATCH; 1560 else 1561 reg = RADEON_BIOS_3_SCRATCH; 1562 1563 /* XXX: fix up scratch reg handling */ 1564 temp = RREG32(reg); 1565 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1566 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1567 (radeon_crtc->crtc_id << 18))); 1568 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1569 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1570 else 1571 WREG32(reg, 0); 1572 1573 if (enable) 1574 args.ucEnable = ATOM_ENABLE; 1575 args.ucCRTC = radeon_crtc->crtc_id; 1576 1577 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1578 1579 WREG32(reg, temp); 1580 } 1581 1582 static void 1583 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1584 { 1585 struct drm_device *dev = encoder->dev; 1586 struct radeon_device *rdev = dev->dev_private; 1587 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1588 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1589 int index = 0; 1590 1591 memset(&args, 0, sizeof(args)); 1592 1593 switch (radeon_encoder->encoder_id) { 1594 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1596 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1597 break; 1598 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1599 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1600 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1601 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1602 break; 1603 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1604 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1605 break; 1606 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1607 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1608 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1609 else 1610 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1611 break; 1612 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1614 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1615 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1616 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1617 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1618 else 1619 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1620 break; 1621 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1623 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1624 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1625 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1626 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1627 else 1628 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1629 break; 1630 default: 1631 return; 1632 } 1633 1634 switch (mode) { 1635 case DRM_MODE_DPMS_ON: 1636 args.ucAction = ATOM_ENABLE; 1637 /* workaround for DVOOutputControl on some RS690 systems */ 1638 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1639 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1640 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1641 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1642 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1643 } else 1644 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1645 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1646 if (rdev->mode_info.bl_encoder) { 1647 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1648 1649 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1650 } else { 1651 args.ucAction = ATOM_LCD_BLON; 1652 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1653 } 1654 } 1655 break; 1656 case DRM_MODE_DPMS_STANDBY: 1657 case DRM_MODE_DPMS_SUSPEND: 1658 case DRM_MODE_DPMS_OFF: 1659 args.ucAction = ATOM_DISABLE; 1660 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1661 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1662 args.ucAction = ATOM_LCD_BLOFF; 1663 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1664 } 1665 break; 1666 } 1667 } 1668 1669 static void 1670 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1671 { 1672 struct drm_device *dev = encoder->dev; 1673 struct radeon_device *rdev = dev->dev_private; 1674 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1675 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1676 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1677 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1678 struct radeon_connector *radeon_connector = NULL; 1679 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1680 bool travis_quirk = false; 1681 1682 if (connector) { 1683 radeon_connector = to_radeon_connector(connector); 1684 radeon_dig_connector = radeon_connector->con_priv; 1685 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1686 ENCODER_OBJECT_ID_TRAVIS) && 1687 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1688 !ASIC_IS_DCE5(rdev)) 1689 travis_quirk = true; 1690 } 1691 1692 switch (mode) { 1693 case DRM_MODE_DPMS_ON: 1694 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1695 if (!connector) 1696 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1697 else 1698 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1699 1700 /* setup and enable the encoder */ 1701 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1702 atombios_dig_encoder_setup(encoder, 1703 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1704 dig->panel_mode); 1705 if (ext_encoder) { 1706 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1707 atombios_external_encoder_setup(encoder, ext_encoder, 1708 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1709 } 1710 } else if (ASIC_IS_DCE4(rdev)) { 1711 /* setup and enable the encoder */ 1712 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1713 } else { 1714 /* setup and enable the encoder and transmitter */ 1715 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1716 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1717 } 1718 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1719 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1720 atombios_set_edp_panel_power(connector, 1721 ATOM_TRANSMITTER_ACTION_POWER_ON); 1722 radeon_dig_connector->edp_on = true; 1723 } 1724 } 1725 /* enable the transmitter */ 1726 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1727 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1728 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1729 radeon_dp_link_train(encoder, connector); 1730 if (ASIC_IS_DCE4(rdev)) 1731 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1732 } 1733 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1734 if (rdev->mode_info.bl_encoder) 1735 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1736 else 1737 atombios_dig_transmitter_setup(encoder, 1738 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1739 } 1740 if (ext_encoder) 1741 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1742 break; 1743 case DRM_MODE_DPMS_STANDBY: 1744 case DRM_MODE_DPMS_SUSPEND: 1745 case DRM_MODE_DPMS_OFF: 1746 1747 /* don't power off encoders with active MST links */ 1748 if (dig->active_mst_links) 1749 return; 1750 1751 if (ASIC_IS_DCE4(rdev)) { 1752 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1753 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1754 } 1755 if (ext_encoder) 1756 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1757 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1758 atombios_dig_transmitter_setup(encoder, 1759 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1760 1761 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1762 connector && !travis_quirk) 1763 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1764 if (ASIC_IS_DCE4(rdev)) { 1765 /* disable the transmitter */ 1766 atombios_dig_transmitter_setup(encoder, 1767 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1768 } else { 1769 /* disable the encoder and transmitter */ 1770 atombios_dig_transmitter_setup(encoder, 1771 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1772 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1773 } 1774 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1775 if (travis_quirk) 1776 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1777 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1778 atombios_set_edp_panel_power(connector, 1779 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1780 radeon_dig_connector->edp_on = false; 1781 } 1782 } 1783 break; 1784 } 1785 } 1786 1787 static void 1788 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1789 { 1790 struct drm_device *dev = encoder->dev; 1791 struct radeon_device *rdev = dev->dev_private; 1792 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1793 int encoder_mode = atombios_get_encoder_mode(encoder); 1794 1795 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1796 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1797 radeon_encoder->active_device); 1798 1799 if ((radeon_audio != 0) && 1800 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1801 ENCODER_MODE_IS_DP(encoder_mode))) 1802 radeon_audio_dpms(encoder, mode); 1803 1804 switch (radeon_encoder->encoder_id) { 1805 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1806 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1807 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1808 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1809 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1810 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1811 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1813 radeon_atom_encoder_dpms_avivo(encoder, mode); 1814 break; 1815 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1816 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1817 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1818 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1819 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1820 radeon_atom_encoder_dpms_dig(encoder, mode); 1821 break; 1822 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1823 if (ASIC_IS_DCE5(rdev)) { 1824 switch (mode) { 1825 case DRM_MODE_DPMS_ON: 1826 atombios_dvo_setup(encoder, ATOM_ENABLE); 1827 break; 1828 case DRM_MODE_DPMS_STANDBY: 1829 case DRM_MODE_DPMS_SUSPEND: 1830 case DRM_MODE_DPMS_OFF: 1831 atombios_dvo_setup(encoder, ATOM_DISABLE); 1832 break; 1833 } 1834 } else if (ASIC_IS_DCE3(rdev)) 1835 radeon_atom_encoder_dpms_dig(encoder, mode); 1836 else 1837 radeon_atom_encoder_dpms_avivo(encoder, mode); 1838 break; 1839 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1840 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1841 if (ASIC_IS_DCE5(rdev)) { 1842 switch (mode) { 1843 case DRM_MODE_DPMS_ON: 1844 atombios_dac_setup(encoder, ATOM_ENABLE); 1845 break; 1846 case DRM_MODE_DPMS_STANDBY: 1847 case DRM_MODE_DPMS_SUSPEND: 1848 case DRM_MODE_DPMS_OFF: 1849 atombios_dac_setup(encoder, ATOM_DISABLE); 1850 break; 1851 } 1852 } else 1853 radeon_atom_encoder_dpms_avivo(encoder, mode); 1854 break; 1855 default: 1856 return; 1857 } 1858 1859 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1860 1861 } 1862 1863 union crtc_source_param { 1864 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1865 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1866 }; 1867 1868 static void 1869 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1870 { 1871 struct drm_device *dev = encoder->dev; 1872 struct radeon_device *rdev = dev->dev_private; 1873 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1874 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1875 union crtc_source_param args; 1876 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1877 uint8_t frev, crev; 1878 struct radeon_encoder_atom_dig *dig; 1879 1880 memset(&args, 0, sizeof(args)); 1881 1882 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1883 return; 1884 1885 switch (frev) { 1886 case 1: 1887 switch (crev) { 1888 case 1: 1889 default: 1890 if (ASIC_IS_AVIVO(rdev)) 1891 args.v1.ucCRTC = radeon_crtc->crtc_id; 1892 else { 1893 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) 1894 args.v1.ucCRTC = radeon_crtc->crtc_id; 1895 else 1896 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1897 } 1898 switch (radeon_encoder->encoder_id) { 1899 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1901 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1902 break; 1903 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1904 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1905 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1906 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1907 else 1908 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1909 break; 1910 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1911 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1913 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1914 break; 1915 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1917 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1918 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1919 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1920 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1921 else 1922 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1923 break; 1924 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1925 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1926 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1927 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1928 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1929 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1930 else 1931 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1932 break; 1933 } 1934 break; 1935 case 2: 1936 args.v2.ucCRTC = radeon_crtc->crtc_id; 1937 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1938 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1939 1940 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1941 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1942 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1943 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1944 else 1945 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1946 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1947 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1948 } else { 1949 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1950 } 1951 switch (radeon_encoder->encoder_id) { 1952 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1953 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1954 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1955 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1956 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1957 dig = radeon_encoder->enc_priv; 1958 switch (dig->dig_encoder) { 1959 case 0: 1960 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1961 break; 1962 case 1: 1963 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1964 break; 1965 case 2: 1966 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1967 break; 1968 case 3: 1969 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1970 break; 1971 case 4: 1972 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1973 break; 1974 case 5: 1975 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1976 break; 1977 case 6: 1978 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1979 break; 1980 } 1981 break; 1982 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1983 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1984 break; 1985 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1986 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1987 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1988 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1989 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1990 else 1991 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1992 break; 1993 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1994 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1995 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1996 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1997 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1998 else 1999 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 2000 break; 2001 } 2002 break; 2003 } 2004 break; 2005 default: 2006 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 2007 return; 2008 } 2009 2010 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2011 2012 /* update scratch regs with new routing */ 2013 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2014 } 2015 2016 void 2017 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) 2018 { 2019 struct drm_device *dev = encoder->dev; 2020 struct radeon_device *rdev = dev->dev_private; 2021 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2022 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 2023 uint8_t frev, crev; 2024 union crtc_source_param args; 2025 2026 memset(&args, 0, sizeof(args)); 2027 2028 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2029 return; 2030 2031 if (frev != 1 && crev != 2) 2032 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); 2033 2034 args.v2.ucCRTC = radeon_crtc->crtc_id; 2035 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; 2036 2037 switch (fe) { 2038 case 0: 2039 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2040 break; 2041 case 1: 2042 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2043 break; 2044 case 2: 2045 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2046 break; 2047 case 3: 2048 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2049 break; 2050 case 4: 2051 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2052 break; 2053 case 5: 2054 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2055 break; 2056 case 6: 2057 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2058 break; 2059 } 2060 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2061 } 2062 2063 static void 2064 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2065 struct drm_display_mode *mode) 2066 { 2067 struct drm_device *dev = encoder->dev; 2068 struct radeon_device *rdev = dev->dev_private; 2069 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2070 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2071 2072 /* Funky macbooks */ 2073 if ((dev->pdev->device == 0x71C5) && 2074 (dev->pdev->subsystem_vendor == 0x106b) && 2075 (dev->pdev->subsystem_device == 0x0080)) { 2076 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2077 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2078 2079 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2080 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2081 2082 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2083 } 2084 } 2085 2086 /* set scaler clears this on some chips */ 2087 if (ASIC_IS_AVIVO(rdev) && 2088 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2089 if (ASIC_IS_DCE8(rdev)) { 2090 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2091 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2092 CIK_INTERLEAVE_EN); 2093 else 2094 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2095 } else if (ASIC_IS_DCE4(rdev)) { 2096 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2097 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2098 EVERGREEN_INTERLEAVE_EN); 2099 else 2100 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2101 } else { 2102 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2103 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2104 AVIVO_D1MODE_INTERLEAVE_EN); 2105 else 2106 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2107 } 2108 } 2109 } 2110 2111 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2112 { 2113 if (enc_idx < 0) 2114 return; 2115 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2116 } 2117 2118 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2119 { 2120 struct drm_device *dev = encoder->dev; 2121 struct radeon_device *rdev = dev->dev_private; 2122 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2123 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2124 struct drm_encoder *test_encoder; 2125 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2126 uint32_t dig_enc_in_use = 0; 2127 int enc_idx = -1; 2128 2129 if (fe_idx >= 0) { 2130 enc_idx = fe_idx; 2131 goto assigned; 2132 } 2133 if (ASIC_IS_DCE6(rdev)) { 2134 /* DCE6 */ 2135 switch (radeon_encoder->encoder_id) { 2136 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2137 if (dig->linkb) 2138 enc_idx = 1; 2139 else 2140 enc_idx = 0; 2141 break; 2142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2143 if (dig->linkb) 2144 enc_idx = 3; 2145 else 2146 enc_idx = 2; 2147 break; 2148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2149 if (dig->linkb) 2150 enc_idx = 5; 2151 else 2152 enc_idx = 4; 2153 break; 2154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2155 enc_idx = 6; 2156 break; 2157 } 2158 goto assigned; 2159 } else if (ASIC_IS_DCE4(rdev)) { 2160 /* DCE4/5 */ 2161 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2162 /* ontario follows DCE4 */ 2163 if (rdev->family == CHIP_PALM) { 2164 if (dig->linkb) 2165 enc_idx = 1; 2166 else 2167 enc_idx = 0; 2168 } else 2169 /* llano follows DCE3.2 */ 2170 enc_idx = radeon_crtc->crtc_id; 2171 } else { 2172 switch (radeon_encoder->encoder_id) { 2173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2174 if (dig->linkb) 2175 enc_idx = 1; 2176 else 2177 enc_idx = 0; 2178 break; 2179 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2180 if (dig->linkb) 2181 enc_idx = 3; 2182 else 2183 enc_idx = 2; 2184 break; 2185 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2186 if (dig->linkb) 2187 enc_idx = 5; 2188 else 2189 enc_idx = 4; 2190 break; 2191 } 2192 } 2193 goto assigned; 2194 } 2195 2196 /* 2197 * On DCE32 any encoder can drive any block so usually just use crtc id, 2198 * but Apple thinks different at least on iMac10,1, so there use linkb, 2199 * otherwise the internal eDP panel will stay dark. 2200 */ 2201 if (ASIC_IS_DCE32(rdev)) { 2202 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) 2203 enc_idx = (dig->linkb) ? 1 : 0; 2204 else 2205 enc_idx = radeon_crtc->crtc_id; 2206 2207 goto assigned; 2208 } 2209 2210 /* on DCE3 - LVTMA can only be driven by DIGB */ 2211 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2212 struct radeon_encoder *radeon_test_encoder; 2213 2214 if (encoder == test_encoder) 2215 continue; 2216 2217 if (!radeon_encoder_is_digital(test_encoder)) 2218 continue; 2219 2220 radeon_test_encoder = to_radeon_encoder(test_encoder); 2221 dig = radeon_test_encoder->enc_priv; 2222 2223 if (dig->dig_encoder >= 0) 2224 dig_enc_in_use |= (1 << dig->dig_encoder); 2225 } 2226 2227 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2228 if (dig_enc_in_use & 0x2) 2229 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2230 return 1; 2231 } 2232 if (!(dig_enc_in_use & 1)) 2233 return 0; 2234 return 1; 2235 2236 assigned: 2237 if (enc_idx == -1) { 2238 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2239 return 0; 2240 } 2241 if (rdev->mode_info.active_encoders & (1 << enc_idx)) 2242 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2243 2244 rdev->mode_info.active_encoders |= (1 << enc_idx); 2245 return enc_idx; 2246 } 2247 2248 /* This only needs to be called once at startup */ 2249 void 2250 radeon_atom_encoder_init(struct radeon_device *rdev) 2251 { 2252 struct drm_device *dev = rdev->ddev; 2253 struct drm_encoder *encoder; 2254 2255 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2256 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2257 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2258 2259 switch (radeon_encoder->encoder_id) { 2260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2261 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2264 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2265 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2266 break; 2267 default: 2268 break; 2269 } 2270 2271 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2272 atombios_external_encoder_setup(encoder, ext_encoder, 2273 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2274 } 2275 } 2276 2277 static void 2278 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2279 struct drm_display_mode *mode, 2280 struct drm_display_mode *adjusted_mode) 2281 { 2282 struct drm_device *dev = encoder->dev; 2283 struct radeon_device *rdev = dev->dev_private; 2284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2285 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2286 int encoder_mode; 2287 2288 radeon_encoder->pixel_clock = adjusted_mode->clock; 2289 2290 /* need to call this here rather than in prepare() since we need some crtc info */ 2291 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2292 2293 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2294 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2295 atombios_yuv_setup(encoder, true); 2296 else 2297 atombios_yuv_setup(encoder, false); 2298 } 2299 2300 switch (radeon_encoder->encoder_id) { 2301 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2302 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2303 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2304 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2305 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2306 break; 2307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2311 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2312 /* handled in dpms */ 2313 break; 2314 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2315 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2316 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2317 atombios_dvo_setup(encoder, ATOM_ENABLE); 2318 break; 2319 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2321 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2322 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2323 atombios_dac_setup(encoder, ATOM_ENABLE); 2324 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2325 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2326 atombios_tv_setup(encoder, ATOM_ENABLE); 2327 else 2328 atombios_tv_setup(encoder, ATOM_DISABLE); 2329 } 2330 break; 2331 } 2332 2333 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2334 2335 encoder_mode = atombios_get_encoder_mode(encoder); 2336 if (connector && (radeon_audio != 0) && 2337 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2338 ENCODER_MODE_IS_DP(encoder_mode))) 2339 radeon_audio_mode_set(encoder, adjusted_mode); 2340 } 2341 2342 static bool 2343 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2344 { 2345 struct drm_device *dev = encoder->dev; 2346 struct radeon_device *rdev = dev->dev_private; 2347 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2348 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2349 2350 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2351 ATOM_DEVICE_CV_SUPPORT | 2352 ATOM_DEVICE_CRT_SUPPORT)) { 2353 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2354 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2355 uint8_t frev, crev; 2356 2357 memset(&args, 0, sizeof(args)); 2358 2359 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2360 return false; 2361 2362 args.sDacload.ucMisc = 0; 2363 2364 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2365 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2366 args.sDacload.ucDacType = ATOM_DAC_A; 2367 else 2368 args.sDacload.ucDacType = ATOM_DAC_B; 2369 2370 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2371 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2372 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2373 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2374 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2375 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2376 if (crev >= 3) 2377 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2378 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2379 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2380 if (crev >= 3) 2381 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2382 } 2383 2384 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2385 2386 return true; 2387 } else 2388 return false; 2389 } 2390 2391 static enum drm_connector_status 2392 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2393 { 2394 struct drm_device *dev = encoder->dev; 2395 struct radeon_device *rdev = dev->dev_private; 2396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2397 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2398 uint32_t bios_0_scratch; 2399 2400 if (!atombios_dac_load_detect(encoder, connector)) { 2401 DRM_DEBUG_KMS("detect returned false \n"); 2402 return connector_status_unknown; 2403 } 2404 2405 if (rdev->family >= CHIP_R600) 2406 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2407 else 2408 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2409 2410 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2411 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2412 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2413 return connector_status_connected; 2414 } 2415 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2416 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2417 return connector_status_connected; 2418 } 2419 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2420 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2421 return connector_status_connected; 2422 } 2423 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2424 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2425 return connector_status_connected; /* CTV */ 2426 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2427 return connector_status_connected; /* STV */ 2428 } 2429 return connector_status_disconnected; 2430 } 2431 2432 static enum drm_connector_status 2433 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2434 { 2435 struct drm_device *dev = encoder->dev; 2436 struct radeon_device *rdev = dev->dev_private; 2437 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2438 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2439 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2440 u32 bios_0_scratch; 2441 2442 if (!ASIC_IS_DCE4(rdev)) 2443 return connector_status_unknown; 2444 2445 if (!ext_encoder) 2446 return connector_status_unknown; 2447 2448 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2449 return connector_status_unknown; 2450 2451 /* load detect on the dp bridge */ 2452 atombios_external_encoder_setup(encoder, ext_encoder, 2453 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2454 2455 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2456 2457 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2458 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2459 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2460 return connector_status_connected; 2461 } 2462 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2463 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2464 return connector_status_connected; 2465 } 2466 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2467 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2468 return connector_status_connected; 2469 } 2470 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2471 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2472 return connector_status_connected; /* CTV */ 2473 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2474 return connector_status_connected; /* STV */ 2475 } 2476 return connector_status_disconnected; 2477 } 2478 2479 void 2480 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2481 { 2482 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2483 2484 if (ext_encoder) 2485 /* ddc_setup on the dp bridge */ 2486 atombios_external_encoder_setup(encoder, ext_encoder, 2487 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2488 2489 } 2490 2491 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2492 { 2493 struct radeon_device *rdev = encoder->dev->dev_private; 2494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2495 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2496 2497 if ((radeon_encoder->active_device & 2498 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2499 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2500 ENCODER_OBJECT_ID_NONE)) { 2501 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2502 if (dig) { 2503 if (dig->dig_encoder >= 0) 2504 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2505 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2506 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2507 if (rdev->family >= CHIP_R600) 2508 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2509 else 2510 /* RS600/690/740 have only 1 afmt block */ 2511 dig->afmt = rdev->mode_info.afmt[0]; 2512 } 2513 } 2514 } 2515 2516 radeon_atom_output_lock(encoder, true); 2517 2518 if (connector) { 2519 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2520 2521 /* select the clock/data port if it uses a router */ 2522 if (radeon_connector->router.cd_valid) 2523 radeon_router_select_cd_port(radeon_connector); 2524 2525 /* turn eDP panel on for mode set */ 2526 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2527 atombios_set_edp_panel_power(connector, 2528 ATOM_TRANSMITTER_ACTION_POWER_ON); 2529 } 2530 2531 /* this is needed for the pll/ss setup to work correctly in some cases */ 2532 atombios_set_encoder_crtc_source(encoder); 2533 /* set up the FMT blocks */ 2534 if (ASIC_IS_DCE8(rdev)) 2535 dce8_program_fmt(encoder); 2536 else if (ASIC_IS_DCE4(rdev)) 2537 dce4_program_fmt(encoder); 2538 else if (ASIC_IS_DCE3(rdev)) 2539 dce3_program_fmt(encoder); 2540 else if (ASIC_IS_AVIVO(rdev)) 2541 avivo_program_fmt(encoder); 2542 } 2543 2544 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2545 { 2546 /* need to call this here as we need the crtc set up */ 2547 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2548 radeon_atom_output_lock(encoder, false); 2549 } 2550 2551 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2552 { 2553 struct drm_device *dev = encoder->dev; 2554 struct radeon_device *rdev = dev->dev_private; 2555 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2556 struct radeon_encoder_atom_dig *dig; 2557 2558 /* check for pre-DCE3 cards with shared encoders; 2559 * can't really use the links individually, so don't disable 2560 * the encoder if it's in use by another connector 2561 */ 2562 if (!ASIC_IS_DCE3(rdev)) { 2563 struct drm_encoder *other_encoder; 2564 struct radeon_encoder *other_radeon_encoder; 2565 2566 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2567 other_radeon_encoder = to_radeon_encoder(other_encoder); 2568 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2569 drm_helper_encoder_in_use(other_encoder)) 2570 goto disable_done; 2571 } 2572 } 2573 2574 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2575 2576 switch (radeon_encoder->encoder_id) { 2577 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2579 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2580 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2581 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2582 break; 2583 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2584 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2585 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2586 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2588 /* handled in dpms */ 2589 break; 2590 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2591 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2592 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2593 atombios_dvo_setup(encoder, ATOM_DISABLE); 2594 break; 2595 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2596 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2597 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2598 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2599 atombios_dac_setup(encoder, ATOM_DISABLE); 2600 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2601 atombios_tv_setup(encoder, ATOM_DISABLE); 2602 break; 2603 } 2604 2605 disable_done: 2606 if (radeon_encoder_is_digital(encoder)) { 2607 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2608 if (rdev->asic->display.hdmi_enable) 2609 radeon_hdmi_enable(rdev, encoder, false); 2610 } 2611 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2612 dig = radeon_encoder->enc_priv; 2613 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2614 dig->dig_encoder = -1; 2615 radeon_encoder->active_device = 0; 2616 } 2617 } else 2618 radeon_encoder->active_device = 0; 2619 } 2620 2621 /* these are handled by the primary encoders */ 2622 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2623 { 2624 2625 } 2626 2627 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2628 { 2629 2630 } 2631 2632 static void 2633 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2634 struct drm_display_mode *mode, 2635 struct drm_display_mode *adjusted_mode) 2636 { 2637 2638 } 2639 2640 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2641 { 2642 2643 } 2644 2645 static void 2646 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2647 { 2648 2649 } 2650 2651 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2652 .dpms = radeon_atom_ext_dpms, 2653 .prepare = radeon_atom_ext_prepare, 2654 .mode_set = radeon_atom_ext_mode_set, 2655 .commit = radeon_atom_ext_commit, 2656 .disable = radeon_atom_ext_disable, 2657 /* no detect for TMDS/LVDS yet */ 2658 }; 2659 2660 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2661 .dpms = radeon_atom_encoder_dpms, 2662 .mode_fixup = radeon_atom_mode_fixup, 2663 .prepare = radeon_atom_encoder_prepare, 2664 .mode_set = radeon_atom_encoder_mode_set, 2665 .commit = radeon_atom_encoder_commit, 2666 .disable = radeon_atom_encoder_disable, 2667 .detect = radeon_atom_dig_detect, 2668 }; 2669 2670 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2671 .dpms = radeon_atom_encoder_dpms, 2672 .mode_fixup = radeon_atom_mode_fixup, 2673 .prepare = radeon_atom_encoder_prepare, 2674 .mode_set = radeon_atom_encoder_mode_set, 2675 .commit = radeon_atom_encoder_commit, 2676 .detect = radeon_atom_dac_detect, 2677 }; 2678 2679 void radeon_enc_destroy(struct drm_encoder *encoder) 2680 { 2681 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2682 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2683 radeon_atom_backlight_exit(radeon_encoder); 2684 kfree(radeon_encoder->enc_priv); 2685 drm_encoder_cleanup(encoder); 2686 kfree(radeon_encoder); 2687 } 2688 2689 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2690 .destroy = radeon_enc_destroy, 2691 }; 2692 2693 static struct radeon_encoder_atom_dac * 2694 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2695 { 2696 struct drm_device *dev = radeon_encoder->base.dev; 2697 struct radeon_device *rdev = dev->dev_private; 2698 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2699 2700 if (!dac) 2701 return NULL; 2702 2703 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2704 return dac; 2705 } 2706 2707 static struct radeon_encoder_atom_dig * 2708 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2709 { 2710 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2711 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2712 2713 if (!dig) 2714 return NULL; 2715 2716 /* coherent mode by default */ 2717 dig->coherent_mode = true; 2718 dig->dig_encoder = -1; 2719 2720 if (encoder_enum == 2) 2721 dig->linkb = true; 2722 else 2723 dig->linkb = false; 2724 2725 return dig; 2726 } 2727 2728 void 2729 radeon_add_atom_encoder(struct drm_device *dev, 2730 uint32_t encoder_enum, 2731 uint32_t supported_device, 2732 u16 caps) 2733 { 2734 struct radeon_device *rdev = dev->dev_private; 2735 struct drm_encoder *encoder; 2736 struct radeon_encoder *radeon_encoder; 2737 2738 /* see if we already added it */ 2739 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2740 radeon_encoder = to_radeon_encoder(encoder); 2741 if (radeon_encoder->encoder_enum == encoder_enum) { 2742 radeon_encoder->devices |= supported_device; 2743 return; 2744 } 2745 2746 } 2747 2748 /* add a new one */ 2749 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2750 if (!radeon_encoder) 2751 return; 2752 2753 encoder = &radeon_encoder->base; 2754 switch (rdev->num_crtc) { 2755 case 1: 2756 encoder->possible_crtcs = 0x1; 2757 break; 2758 case 2: 2759 default: 2760 encoder->possible_crtcs = 0x3; 2761 break; 2762 case 4: 2763 encoder->possible_crtcs = 0xf; 2764 break; 2765 case 6: 2766 encoder->possible_crtcs = 0x3f; 2767 break; 2768 } 2769 2770 radeon_encoder->enc_priv = NULL; 2771 2772 radeon_encoder->encoder_enum = encoder_enum; 2773 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2774 radeon_encoder->devices = supported_device; 2775 radeon_encoder->rmx_type = RMX_OFF; 2776 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2777 radeon_encoder->is_ext_encoder = false; 2778 radeon_encoder->caps = caps; 2779 2780 switch (radeon_encoder->encoder_id) { 2781 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2782 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2783 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2784 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2785 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2786 radeon_encoder->rmx_type = RMX_FULL; 2787 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2788 DRM_MODE_ENCODER_LVDS, NULL); 2789 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2790 } else { 2791 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2792 DRM_MODE_ENCODER_TMDS, NULL); 2793 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2794 } 2795 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2796 break; 2797 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2798 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2799 DRM_MODE_ENCODER_DAC, NULL); 2800 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2801 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2802 break; 2803 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2804 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2805 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2806 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2807 DRM_MODE_ENCODER_TVDAC, NULL); 2808 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2809 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2810 break; 2811 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2813 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2815 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2816 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2817 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2818 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2819 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2820 radeon_encoder->rmx_type = RMX_FULL; 2821 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2822 DRM_MODE_ENCODER_LVDS, NULL); 2823 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2824 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2825 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2826 DRM_MODE_ENCODER_DAC, NULL); 2827 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2828 } else { 2829 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2830 DRM_MODE_ENCODER_TMDS, NULL); 2831 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2832 } 2833 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2834 break; 2835 case ENCODER_OBJECT_ID_SI170B: 2836 case ENCODER_OBJECT_ID_CH7303: 2837 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2838 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2839 case ENCODER_OBJECT_ID_TITFP513: 2840 case ENCODER_OBJECT_ID_VT1623: 2841 case ENCODER_OBJECT_ID_HDMI_SI1930: 2842 case ENCODER_OBJECT_ID_TRAVIS: 2843 case ENCODER_OBJECT_ID_NUTMEG: 2844 /* these are handled by the primary encoders */ 2845 radeon_encoder->is_ext_encoder = true; 2846 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2847 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2848 DRM_MODE_ENCODER_LVDS, NULL); 2849 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2850 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2851 DRM_MODE_ENCODER_DAC, NULL); 2852 else 2853 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2854 DRM_MODE_ENCODER_TMDS, NULL); 2855 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2856 break; 2857 } 2858 } 2859
Indexes created Sat Sep 20 22:09:52 GMT 2025