1 /* $NetBSD: atppcvar.h,v 1.13 2024/08/13 16:23:48 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp 29 * 30 */ 31 32 #ifndef __ATPPCVAR_H 33 #define __ATPPCVAR_H 34 35 #include <sys/bus.h> 36 #include <machine/types.h> 37 #include <sys/device.h> 38 #include <sys/callout.h> 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 42 #include <dev/ppbus/ppbus_conf.h> 43 44 45 /* Maximum time to wait for device response */ 46 #define MAXBUSYWAIT (5 * (hz)) 47 48 /* Poll interval when waiting for device to become ready */ 49 #define ATPPC_POLL ((hz)/10) 50 51 52 /* Diagnostic and verbose printing macros */ 53 54 #ifdef ATPPC_DEBUG 55 extern int atppc_debug; 56 #define ATPPC_DPRINTF(arg) if(atppc_debug) printf arg 57 #else 58 #define ATPPC_DPRINTF(arg) 59 #endif 60 61 #ifdef ATPPC_VERBOSE 62 extern int atppc_verbose; 63 #define ATPPC_VPRINTF(arg) if(atppc_verbose) printf arg 64 #else 65 #define ATPPC_VPRINTF(arg) 66 #endif 67 68 69 /* Flag used in DMA transfer */ 70 #define ATPPC_DMA_MODE_READ 0x0 71 #define ATPPC_DMA_MODE_WRITE 0x1 72 73 74 /* Flags passed via config */ 75 #define ATPPC_FLAG_DISABLE_INTR 0x01 76 #define ATPPC_FLAG_DISABLE_DMA 0x02 77 78 /* Single softintr callback entry */ 79 struct atppc_handler_node { 80 void (*func)(void *); 81 void *arg; 82 SLIST_ENTRY(atppc_handler_node) entries; 83 }; 84 85 /* Generic structure to hold parallel port chipset info. */ 86 struct atppc_softc { 87 /* Generic device attributes */ 88 device_t sc_dev; 89 90 kmutex_t sc_lock; 91 kcondvar_t sc_out_cv; 92 kcondvar_t sc_in_cv; 93 94 /* Machine independent bus infrastructure */ 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 bus_dma_tag_t sc_dmat; 98 bus_dmamap_t sc_dmapt; 99 bus_size_t sc_dma_maxsize; 100 101 /* Child device */ 102 device_t child; 103 104 /* Opaque handle used for interrupt handler establishment */ 105 void *sc_ieh; 106 107 /* List of soft interrupts to call */ 108 SLIST_HEAD(handler_list, atppc_handler_node) sc_handler_listhead; 109 110 /* Input buffer: working pointers, and size in bytes. */ 111 char * sc_inb; 112 char * sc_inbstart; 113 u_int32_t sc_inb_nbytes; 114 int sc_inerr; 115 116 /* Output buffer pointer, working pointer, and size in bytes. */ 117 char * sc_outb; 118 char * sc_outbstart; 119 u_int32_t sc_outb_nbytes; 120 int sc_outerr; 121 122 /* DMA functions: setup by bus specific attach code */ 123 int (*sc_dma_start)(struct atppc_softc *, void *, u_int, u_int8_t); 124 int (*sc_dma_finish)(struct atppc_softc *); 125 int (*sc_dma_abort)(struct atppc_softc *); 126 int (*sc_dma_malloc)(device_t, void **, bus_addr_t *, 127 bus_size_t); 128 void (*sc_dma_free)(device_t, void **, bus_addr_t *, 129 bus_size_t); 130 131 /* Microsequence related members */ 132 char * sc_ptr; /* microseq current pointer */ 133 int sc_accum; /* microseq accumulator */ 134 135 /* Device attachment state */ 136 #define ATPPC_ATTACHED 1 137 #define ATPPC_NOATTACH 0 138 u_int8_t sc_dev_ok; 139 140 /* 141 * Hardware capabilities flags: standard mode and nibble mode are 142 * assumed to always be available since if they aren't you don't 143 * HAVE a parallel port. 144 */ 145 #define ATPPC_HAS_INTR 0x01 /* Interrupt available */ 146 #define ATPPC_HAS_DMA 0x02 /* DMA available */ 147 #define ATPPC_HAS_FIFO 0x04 /* FIFO available */ 148 #define ATPPC_HAS_PS2 0x08 /* PS2 mode capable */ 149 #define ATPPC_HAS_ECP 0x10 /* ECP mode available */ 150 #define ATPPC_HAS_EPP 0x20 /* EPP mode available */ 151 u_int8_t sc_has; /* Chipset detected capabilities */ 152 153 /* Flags specifying mode of chipset operation . */ 154 #define ATPPC_MODE_STD 0x01 /* Use centronics-compatible mode */ 155 #define ATPPC_MODE_PS2 0x02 /* Use PS2 mode */ 156 #define ATPPC_MODE_EPP 0x04 /* Use EPP mode */ 157 #define ATPPC_MODE_ECP 0x08 /* Use ECP mode */ 158 #define ATPPC_MODE_NIBBLE 0x10 /* Use nibble mode */ 159 #define ATPPC_MODE_FAST 0x20 /* Use Fast Centronics mode */ 160 u_int8_t sc_mode; /* Current operational mode */ 161 162 /* Flags which further define chipset operation */ 163 #define ATPPC_USE_INTR 0x01 /* Use interrupts */ 164 #define ATPPC_USE_DMA 0x02 /* Use DMA */ 165 u_int8_t sc_use; /* Capabilities to use */ 166 167 /* Parallel Port Chipset model. */ 168 #define SMC_LIKE 0 169 #define SMC_37C665GT 1 170 #define SMC_37C666GT 2 171 #define NS_PC87332 3 172 #define NS_PC87306 4 173 #define INTEL_820191AA 5 /* XXX not implemented */ 174 #define GENERIC 6 175 #define WINB_W83877F 7 176 #define WINB_W83877AF 8 177 #define WINB_UNKNOWN 9 178 #define NS_PC87334 10 179 #define SMC_37C935 11 180 #define NS_PC87303 12 181 u_int8_t sc_model; /* chipset model */ 182 183 /* EPP mode */ 184 #define ATPPC_EPP_1_9 0x0 185 #define ATPPC_EPP_1_7 0x1 186 u_int8_t sc_epp; 187 188 /* Parallel Port Chipset Type. SMC versus GENERIC (others) */ 189 #define ATPPC_TYPE_SMCLIKE 0 190 #define ATPPC_TYPE_GENERIC 1 191 u_int8_t sc_type; /* generic or smclike chipset type */ 192 193 /* Stored register values after an interrupt occurs */ 194 u_int8_t sc_ecr_intr; 195 u_int8_t sc_ctr_intr; 196 u_int8_t sc_str_intr; 197 198 #define ATPPC_IRQ_NONE 0x0 199 #define ATPPC_IRQ_nACK 0x1 200 #define ATPPC_IRQ_DMA 0x2 201 #define ATPPC_IRQ_FIFO 0x4 202 #define ATPPC_IRQ_nFAULT 0x8 203 u_int8_t sc_irqstat; /* Record irq settings */ 204 205 #define ATPPC_DMA_INIT 0x01 206 #define ATPPC_DMA_STARTED 0x02 207 #define ATPPC_DMA_COMPLETE 0x03 208 #define ATPPC_DMA_INTERRUPTED 0x04 209 #define ATPPC_DMA_ERROR 0x05 210 u_int8_t sc_dmastat; /* Record dma state */ 211 212 #define ATPPC_PWORD_MASK 0x30 213 #define ATPPC_PWORD_16 0x00 214 #define ATPPC_PWORD_8 0x10 215 #define ATPPC_PWORD_32 0x20 216 u_int8_t sc_pword; /* PWord size: used for FIFO DMA transfers */ 217 u_int8_t sc_fifo; /* FIFO size */ 218 219 /* Indicates number of PWords in FIFO queues that generate interrupt */ 220 u_int8_t sc_wthr; /* writeIntrThreshold */ 221 u_int8_t sc_rthr; /* readIntrThreshold */ 222 }; 223 224 225 226 #ifdef _KERNEL 227 228 /* Function prototypes */ 229 230 /* Soft config attach/detach routines */ 231 void atppc_sc_attach(struct atppc_softc *); 232 int atppc_sc_detach(struct atppc_softc *, int); 233 234 /* Detection routines */ 235 int atppc_detect_port(bus_space_tag_t, bus_space_handle_t); 236 237 /* Interrupt handler for atppc device */ 238 int atppcintr(void *); 239 240 #endif /* _KERNEL */ 241 242 #endif /* __ATPPCVAR_H */ 243
Indexes created Mon Sep 22 21:09:42 GMT 2025