1 /* $NetBSD: dc_hw_types.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef DC_HW_TYPES_H 29 #define DC_HW_TYPES_H 30 31 #include "os_types.h" 32 #include "fixed31_32.h" 33 #include "signal_types.h" 34 35 /****************************************************************************** 36 * Data types for Virtual HW Layer of DAL3. 37 * (see DAL3 design documents for HW Layer definition) 38 * 39 * The intended uses are: 40 * 1. Generation pseudocode sequences for HW programming. 41 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 42 * 43 * Note: do *not* add any types which are *not* used for HW programming - this 44 * will ensure separation of Logic layer from HW layer. 45 ******************************************************************************/ 46 47 union large_integer { 48 struct { 49 uint32_t low_part; 50 int32_t high_part; 51 }; 52 53 struct { 54 uint32_t low_part; 55 int32_t high_part; 56 } u; 57 58 int64_t quad_part; 59 }; 60 61 #define PHYSICAL_ADDRESS_LOC union large_integer 62 63 enum dc_plane_addr_type { 64 PLN_ADDR_TYPE_GRAPHICS = 0, 65 PLN_ADDR_TYPE_GRPH_STEREO, 66 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 67 }; 68 69 struct dc_plane_address { 70 enum dc_plane_addr_type type; 71 bool tmz_surface; 72 union { 73 struct{ 74 PHYSICAL_ADDRESS_LOC addr; 75 PHYSICAL_ADDRESS_LOC meta_addr; 76 union large_integer dcc_const_color; 77 } grph; 78 79 /*stereo*/ 80 struct { 81 PHYSICAL_ADDRESS_LOC left_addr; 82 PHYSICAL_ADDRESS_LOC left_meta_addr; 83 union large_integer left_dcc_const_color; 84 85 PHYSICAL_ADDRESS_LOC right_addr; 86 PHYSICAL_ADDRESS_LOC right_meta_addr; 87 union large_integer right_dcc_const_color; 88 89 } grph_stereo; 90 91 /*video progressive*/ 92 struct { 93 PHYSICAL_ADDRESS_LOC luma_addr; 94 PHYSICAL_ADDRESS_LOC luma_meta_addr; 95 union large_integer luma_dcc_const_color; 96 97 PHYSICAL_ADDRESS_LOC chroma_addr; 98 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 99 union large_integer chroma_dcc_const_color; 100 } video_progressive; 101 }; 102 103 union large_integer page_table_base; 104 105 uint8_t vmid; 106 }; 107 108 struct dc_size { 109 int width; 110 int height; 111 }; 112 113 struct rect { 114 int x; 115 int y; 116 int width; 117 int height; 118 }; 119 120 struct plane_size { 121 /* Graphic surface pitch in pixels. 122 * In LINEAR_GENERAL mode, pitch 123 * is 32 pixel aligned. 124 */ 125 int surface_pitch; 126 int chroma_pitch; 127 struct rect surface_size; 128 struct rect chroma_size; 129 }; 130 131 struct dc_plane_dcc_param { 132 bool enable; 133 134 int meta_pitch; 135 bool independent_64b_blks; 136 137 int meta_pitch_c; 138 bool independent_64b_blks_c; 139 }; 140 141 /*Displayable pixel format in fb*/ 142 enum surface_pixel_format { 143 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 144 /*TOBE REMOVED paletta 256 colors*/ 145 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 146 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 147 /*16 bpp*/ 148 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 149 /*16 bpp*/ 150 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 151 /*32 bpp*/ 152 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 153 /*32 bpp swaped*/ 154 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 155 156 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 157 /*swaped*/ 158 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 159 /*TOBE REMOVED swaped, XR_BIAS has no differance 160 * for pixel layout than previous and we can 161 * delete this after discusion*/ 162 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 163 /*64 bpp */ 164 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 165 /*float*/ 166 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 167 /*swaped & float*/ 168 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 169 /*grow graphics here if necessary */ 170 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 171 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 172 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 173 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 174 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 175 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 176 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 177 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 178 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 179 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 180 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 181 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, 182 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 183 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 184 SURFACE_PIXEL_FORMAT_INVALID 185 186 /*grow 444 video here if necessary */ 187 }; 188 189 190 191 /* Pixel format */ 192 enum pixel_format { 193 /*graph*/ 194 PIXEL_FORMAT_UNINITIALIZED, 195 PIXEL_FORMAT_INDEX8, 196 PIXEL_FORMAT_RGB565, 197 PIXEL_FORMAT_ARGB8888, 198 PIXEL_FORMAT_ARGB2101010, 199 PIXEL_FORMAT_ARGB2101010_XRBIAS, 200 PIXEL_FORMAT_FP16, 201 /*video*/ 202 PIXEL_FORMAT_420BPP8, 203 PIXEL_FORMAT_420BPP10, 204 /*end of pixel format definition*/ 205 PIXEL_FORMAT_INVALID, 206 207 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 208 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 209 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 210 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 211 PIXEL_FORMAT_UNKNOWN 212 }; 213 214 enum tile_split_values { 215 DC_DISPLAY_MICRO_TILING = 0x0, 216 DC_THIN_MICRO_TILING = 0x1, 217 DC_DEPTH_MICRO_TILING = 0x2, 218 DC_ROTATED_MICRO_TILING = 0x3, 219 }; 220 221 enum tripleBuffer_enable { 222 DC_TRIPLEBUFFER_DISABLE = 0x0, 223 DC_TRIPLEBUFFER_ENABLE = 0x1, 224 }; 225 226 /* TODO: These values come from hardware spec. We need to readdress this 227 * if they ever change. 228 */ 229 enum array_mode_values { 230 DC_ARRAY_LINEAR_GENERAL = 0, 231 DC_ARRAY_LINEAR_ALLIGNED, 232 DC_ARRAY_1D_TILED_THIN1, 233 DC_ARRAY_1D_TILED_THICK, 234 DC_ARRAY_2D_TILED_THIN1, 235 DC_ARRAY_PRT_TILED_THIN1, 236 DC_ARRAY_PRT_2D_TILED_THIN1, 237 DC_ARRAY_2D_TILED_THICK, 238 DC_ARRAY_2D_TILED_X_THICK, 239 DC_ARRAY_PRT_TILED_THICK, 240 DC_ARRAY_PRT_2D_TILED_THICK, 241 DC_ARRAY_PRT_3D_TILED_THIN1, 242 DC_ARRAY_3D_TILED_THIN1, 243 DC_ARRAY_3D_TILED_THICK, 244 DC_ARRAY_3D_TILED_X_THICK, 245 DC_ARRAY_PRT_3D_TILED_THICK, 246 }; 247 248 enum tile_mode_values { 249 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 250 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 251 }; 252 253 enum swizzle_mode_values { 254 DC_SW_LINEAR = 0, 255 DC_SW_256B_S = 1, 256 DC_SW_256_D = 2, 257 DC_SW_256_R = 3, 258 DC_SW_4KB_S = 5, 259 DC_SW_4KB_D = 6, 260 DC_SW_4KB_R = 7, 261 DC_SW_64KB_S = 9, 262 DC_SW_64KB_D = 10, 263 DC_SW_64KB_R = 11, 264 DC_SW_VAR_S = 13, 265 DC_SW_VAR_D = 14, 266 DC_SW_VAR_R = 15, 267 DC_SW_64KB_S_T = 17, 268 DC_SW_64KB_D_T = 18, 269 DC_SW_4KB_S_X = 21, 270 DC_SW_4KB_D_X = 22, 271 DC_SW_4KB_R_X = 23, 272 DC_SW_64KB_S_X = 25, 273 DC_SW_64KB_D_X = 26, 274 DC_SW_64KB_R_X = 27, 275 DC_SW_VAR_S_X = 29, 276 DC_SW_VAR_D_X = 30, 277 DC_SW_VAR_R_X = 31, 278 DC_SW_MAX = 32, 279 DC_SW_UNKNOWN = DC_SW_MAX 280 }; 281 282 union dc_tiling_info { 283 284 struct { 285 /* Specifies the number of memory banks for tiling 286 * purposes. 287 * Only applies to 2D and 3D tiling modes. 288 * POSSIBLE VALUES: 2,4,8,16 289 */ 290 unsigned int num_banks; 291 /* Specifies the number of tiles in the x direction 292 * to be incorporated into the same bank. 293 * Only applies to 2D and 3D tiling modes. 294 * POSSIBLE VALUES: 1,2,4,8 295 */ 296 unsigned int bank_width; 297 unsigned int bank_width_c; 298 /* Specifies the number of tiles in the y direction to 299 * be incorporated into the same bank. 300 * Only applies to 2D and 3D tiling modes. 301 * POSSIBLE VALUES: 1,2,4,8 302 */ 303 unsigned int bank_height; 304 unsigned int bank_height_c; 305 /* Specifies the macro tile aspect ratio. Only applies 306 * to 2D and 3D tiling modes. 307 */ 308 unsigned int tile_aspect; 309 unsigned int tile_aspect_c; 310 /* Specifies the number of bytes that will be stored 311 * contiguously for each tile. 312 * If the tile data requires more storage than this 313 * amount, it is split into multiple slices. 314 * This field must not be larger than 315 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 316 * Only applies to 2D and 3D tiling modes. 317 * For color render targets, TILE_SPLIT >= 256B. 318 */ 319 enum tile_split_values tile_split; 320 enum tile_split_values tile_split_c; 321 /* Specifies the addressing within a tile. 322 * 0x0 - DISPLAY_MICRO_TILING 323 * 0x1 - THIN_MICRO_TILING 324 * 0x2 - DEPTH_MICRO_TILING 325 * 0x3 - ROTATED_MICRO_TILING 326 */ 327 enum tile_mode_values tile_mode; 328 enum tile_mode_values tile_mode_c; 329 /* Specifies the number of pipes and how they are 330 * interleaved in the surface. 331 * Refer to memory addressing document for complete 332 * details and constraints. 333 */ 334 unsigned int pipe_config; 335 /* Specifies the tiling mode of the surface. 336 * THIN tiles use an 8x8x1 tile size. 337 * THICK tiles use an 8x8x4 tile size. 338 * 2D tiling modes rotate banks for successive Z slices 339 * 3D tiling modes rotate pipes and banks for Z slices 340 * Refer to memory addressing document for complete 341 * details and constraints. 342 */ 343 enum array_mode_values array_mode; 344 } gfx8; 345 346 struct { 347 enum swizzle_mode_values swizzle; 348 unsigned int num_pipes; 349 unsigned int max_compressed_frags; 350 unsigned int pipe_interleave; 351 352 unsigned int num_banks; 353 unsigned int num_shader_engines; 354 unsigned int num_rb_per_se; 355 bool shaderEnable; 356 357 bool meta_linear; 358 bool rb_aligned; 359 bool pipe_aligned; 360 } gfx9; 361 }; 362 363 /* Rotation angle */ 364 enum dc_rotation_angle { 365 ROTATION_ANGLE_0 = 0, 366 ROTATION_ANGLE_90, 367 ROTATION_ANGLE_180, 368 ROTATION_ANGLE_270, 369 ROTATION_ANGLE_COUNT 370 }; 371 372 enum dc_scan_direction { 373 SCAN_DIRECTION_UNKNOWN = 0, 374 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 375 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 376 }; 377 378 struct dc_cursor_position { 379 uint32_t x; 380 uint32_t y; 381 382 uint32_t x_hotspot; 383 uint32_t y_hotspot; 384 385 /* 386 * This parameter indicates whether HW cursor should be enabled 387 */ 388 bool enable; 389 390 }; 391 392 struct dc_cursor_mi_param { 393 unsigned int pixel_clk_khz; 394 unsigned int ref_clk_khz; 395 struct rect viewport; 396 struct fixed31_32 h_scale_ratio; 397 struct fixed31_32 v_scale_ratio; 398 enum dc_rotation_angle rotation; 399 bool mirror; 400 }; 401 402 /* IPP related types */ 403 404 enum { 405 GAMMA_RGB_256_ENTRIES = 256, 406 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 407 GAMMA_CS_TFM_1D_ENTRIES = 4096, 408 GAMMA_CUSTOM_ENTRIES = 4096, 409 GAMMA_MAX_ENTRIES = 4096 410 }; 411 412 enum dc_gamma_type { 413 GAMMA_RGB_256 = 1, 414 GAMMA_RGB_FLOAT_1024 = 2, 415 GAMMA_CS_TFM_1D = 3, 416 GAMMA_CUSTOM = 4, 417 }; 418 419 struct dc_csc_transform { 420 uint16_t matrix[12]; 421 bool enable_adjustment; 422 }; 423 424 struct dc_rgb_fixed { 425 struct fixed31_32 red; 426 struct fixed31_32 green; 427 struct fixed31_32 blue; 428 }; 429 430 struct dc_gamma { 431 struct kref refcount; 432 enum dc_gamma_type type; 433 unsigned int num_entries; 434 435 struct dc_gamma_entries { 436 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 437 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 438 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 439 } entries; 440 441 /* private to DC core */ 442 struct dc_context *ctx; 443 444 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 445 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 446 */ 447 bool is_identity; 448 }; 449 450 /* Used by both ipp amd opp functions*/ 451 /* TODO: to be consolidated with enum color_space */ 452 453 /* 454 * This enum is for programming CURSOR_MODE register field. What this register 455 * should be programmed to depends on OS requested cursor shape flags and what 456 * we stored in the cursor surface. 457 */ 458 enum dc_cursor_color_format { 459 CURSOR_MODE_MONO, 460 CURSOR_MODE_COLOR_1BIT_AND, 461 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 462 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 463 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 464 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 465 }; 466 467 /* 468 * This is all the parameters required by DAL in order to update the cursor 469 * attributes, including the new cursor image surface address, size, hotspot 470 * location, color format, etc. 471 */ 472 473 union dc_cursor_attribute_flags { 474 struct { 475 uint32_t ENABLE_MAGNIFICATION:1; 476 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 477 uint32_t HORIZONTAL_MIRROR:1; 478 uint32_t VERTICAL_MIRROR:1; 479 uint32_t INVERT_PIXEL_DATA:1; 480 uint32_t ZERO_EXPANSION:1; 481 uint32_t MIN_MAX_INVERT:1; 482 uint32_t ENABLE_CURSOR_DEGAMMA:1; 483 uint32_t RESERVED:24; 484 } bits; 485 uint32_t value; 486 }; 487 488 struct dc_cursor_attributes { 489 PHYSICAL_ADDRESS_LOC address; 490 uint32_t pitch; 491 492 /* Width and height should correspond to cursor surface width x heigh */ 493 uint32_t width; 494 uint32_t height; 495 496 enum dc_cursor_color_format color_format; 497 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 498 499 /* In case we support HW Cursor rotation in the future */ 500 enum dc_rotation_angle rotation_angle; 501 502 union dc_cursor_attribute_flags attribute_flags; 503 }; 504 505 struct dpp_cursor_attributes { 506 int bias; 507 int scale; 508 }; 509 510 /* OPP */ 511 512 enum dc_color_space { 513 COLOR_SPACE_UNKNOWN, 514 COLOR_SPACE_SRGB, 515 COLOR_SPACE_XR_RGB, 516 COLOR_SPACE_SRGB_LIMITED, 517 COLOR_SPACE_MSREF_SCRGB, 518 COLOR_SPACE_YCBCR601, 519 COLOR_SPACE_YCBCR709, 520 COLOR_SPACE_XV_YCC_709, 521 COLOR_SPACE_XV_YCC_601, 522 COLOR_SPACE_YCBCR601_LIMITED, 523 COLOR_SPACE_YCBCR709_LIMITED, 524 COLOR_SPACE_2020_RGB_FULLRANGE, 525 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 526 COLOR_SPACE_2020_YCBCR, 527 COLOR_SPACE_ADOBERGB, 528 COLOR_SPACE_DCIP3, 529 COLOR_SPACE_DISPLAYNATIVE, 530 COLOR_SPACE_DOLBYVISION, 531 COLOR_SPACE_APPCTRL, 532 COLOR_SPACE_CUSTOMPOINTS, 533 COLOR_SPACE_YCBCR709_BLACK, 534 }; 535 536 enum dc_dither_option { 537 DITHER_OPTION_DEFAULT, 538 DITHER_OPTION_DISABLE, 539 DITHER_OPTION_FM6, 540 DITHER_OPTION_FM8, 541 DITHER_OPTION_FM10, 542 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 543 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 544 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 545 DITHER_OPTION_SPATIAL6, 546 DITHER_OPTION_SPATIAL8, 547 DITHER_OPTION_SPATIAL10, 548 DITHER_OPTION_TRUN6, 549 DITHER_OPTION_TRUN8, 550 DITHER_OPTION_TRUN10, 551 DITHER_OPTION_TRUN10_SPATIAL8, 552 DITHER_OPTION_TRUN10_SPATIAL6, 553 DITHER_OPTION_TRUN10_FM8, 554 DITHER_OPTION_TRUN10_FM6, 555 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 556 DITHER_OPTION_SPATIAL10_FM8, 557 DITHER_OPTION_SPATIAL10_FM6, 558 DITHER_OPTION_TRUN8_SPATIAL6, 559 DITHER_OPTION_TRUN8_FM6, 560 DITHER_OPTION_SPATIAL8_FM6, 561 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 562 DITHER_OPTION_INVALID 563 }; 564 565 enum dc_quantization_range { 566 QUANTIZATION_RANGE_UNKNOWN, 567 QUANTIZATION_RANGE_FULL, 568 QUANTIZATION_RANGE_LIMITED 569 }; 570 571 enum dc_dynamic_expansion { 572 DYN_EXPANSION_AUTO, 573 DYN_EXPANSION_DISABLE 574 }; 575 576 /* XFM */ 577 578 /* used in struct dc_plane_state */ 579 struct scaling_taps { 580 uint32_t v_taps; 581 uint32_t h_taps; 582 uint32_t v_taps_c; 583 uint32_t h_taps_c; 584 bool integer_scaling; 585 }; 586 587 enum dc_timing_standard { 588 DC_TIMING_STANDARD_UNDEFINED, 589 DC_TIMING_STANDARD_DMT, 590 DC_TIMING_STANDARD_GTF, 591 DC_TIMING_STANDARD_CVT, 592 DC_TIMING_STANDARD_CVT_RB, 593 DC_TIMING_STANDARD_CEA770, 594 DC_TIMING_STANDARD_CEA861, 595 DC_TIMING_STANDARD_HDMI, 596 DC_TIMING_STANDARD_TV_NTSC, 597 DC_TIMING_STANDARD_TV_NTSC_J, 598 DC_TIMING_STANDARD_TV_PAL, 599 DC_TIMING_STANDARD_TV_PAL_M, 600 DC_TIMING_STANDARD_TV_PAL_CN, 601 DC_TIMING_STANDARD_TV_SECAM, 602 DC_TIMING_STANDARD_EXPLICIT, 603 /*!< For explicit timings from EDID, VBIOS, etc.*/ 604 DC_TIMING_STANDARD_USER_OVERRIDE, 605 /*!< For mode timing override by user*/ 606 DC_TIMING_STANDARD_MAX 607 }; 608 609 enum dc_color_depth { 610 COLOR_DEPTH_UNDEFINED, 611 COLOR_DEPTH_666, 612 COLOR_DEPTH_888, 613 COLOR_DEPTH_101010, 614 COLOR_DEPTH_121212, 615 COLOR_DEPTH_141414, 616 COLOR_DEPTH_161616, 617 COLOR_DEPTH_999, 618 COLOR_DEPTH_111111, 619 COLOR_DEPTH_COUNT 620 }; 621 622 enum dc_pixel_encoding { 623 PIXEL_ENCODING_UNDEFINED, 624 PIXEL_ENCODING_RGB, 625 PIXEL_ENCODING_YCBCR422, 626 PIXEL_ENCODING_YCBCR444, 627 PIXEL_ENCODING_YCBCR420, 628 PIXEL_ENCODING_COUNT 629 }; 630 631 enum dc_aspect_ratio { 632 ASPECT_RATIO_NO_DATA, 633 ASPECT_RATIO_4_3, 634 ASPECT_RATIO_16_9, 635 ASPECT_RATIO_64_27, 636 ASPECT_RATIO_256_135, 637 ASPECT_RATIO_FUTURE 638 }; 639 640 enum scanning_type { 641 SCANNING_TYPE_NODATA = 0, 642 SCANNING_TYPE_OVERSCAN, 643 SCANNING_TYPE_UNDERSCAN, 644 SCANNING_TYPE_FUTURE, 645 SCANNING_TYPE_UNDEFINED 646 }; 647 648 struct dc_crtc_timing_flags { 649 uint32_t INTERLACE :1; 650 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 651 it is positive polarity --reversed with dal1 or video bios define*/ 652 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 653 it is positive polarity --reversed with dal1 or video bios define*/ 654 655 uint32_t HORZ_COUNT_BY_TWO:1; 656 657 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 658 timing can be driven in 3D format only 659 and there is no corresponding 2D timing*/ 660 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 661 (right eye = '1', left eye = '0') */ 662 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 663 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 664 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 665 because corresponding 2D timing also present in the list*/ 666 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 667 and we want to match priority of corresponding 3D timing*/ 668 uint32_t Y_ONLY :1; 669 670 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 671 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 672 673 uint32_t FORCE_HDR :1; 674 675 /* HDMI 2.0 - Support scrambling for TMDS character 676 * rates less than or equal to 340Mcsc */ 677 uint32_t LTE_340MCSC_SCRAMBLE:1; 678 679 uint32_t DSC : 1; /* Use DSC with this timing */ 680 }; 681 682 enum dc_timing_3d_format { 683 TIMING_3D_FORMAT_NONE, 684 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 685 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 686 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 687 /* for active DP-HDMI dongle*/ 688 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 689 TIMING_3D_FORMAT_HW_FRAME_PACKING, 690 TIMING_3D_FORMAT_SW_FRAME_PACKING, 691 TIMING_3D_FORMAT_ROW_INTERLEAVE, 692 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 693 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 694 TIMING_3D_FORMAT_SIDE_BY_SIDE, 695 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 696 TIMING_3D_FORMAT_SBS_SW_PACKED, 697 /* Side-by-side, packed by application/driver into 2D frame*/ 698 TIMING_3D_FORMAT_TB_SW_PACKED, 699 /* Top-and-bottom, packed by application/driver into 2D frame*/ 700 701 TIMING_3D_FORMAT_MAX, 702 }; 703 704 struct dc_dsc_config { 705 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 706 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 707 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 708 bool block_pred_enable; /* DSC block prediction enable */ 709 uint32_t linebuf_depth; /* DSC line buffer depth */ 710 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 711 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 712 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 713 }; 714 struct dc_crtc_timing { 715 uint32_t h_total; 716 uint32_t h_border_left; 717 uint32_t h_addressable; 718 uint32_t h_border_right; 719 uint32_t h_front_porch; 720 uint32_t h_sync_width; 721 722 uint32_t v_total; 723 uint32_t v_border_top; 724 uint32_t v_addressable; 725 uint32_t v_border_bottom; 726 uint32_t v_front_porch; 727 uint32_t v_sync_width; 728 729 uint32_t pix_clk_100hz; 730 731 uint32_t vic; 732 uint32_t hdmi_vic; 733 enum dc_timing_3d_format timing_3d_format; 734 enum dc_color_depth display_color_depth; 735 enum dc_pixel_encoding pixel_encoding; 736 enum dc_aspect_ratio aspect_ratio; 737 enum scanning_type scan_type; 738 739 struct dc_crtc_timing_flags flags; 740 struct dc_dsc_config dsc_cfg; 741 }; 742 743 enum trigger_delay { 744 TRIGGER_DELAY_NEXT_PIXEL = 0, 745 TRIGGER_DELAY_NEXT_LINE, 746 }; 747 748 enum crtc_event { 749 CRTC_EVENT_VSYNC_RISING = 0, 750 CRTC_EVENT_VSYNC_FALLING 751 }; 752 753 struct crtc_trigger_info { 754 bool enabled; 755 struct dc_stream_state *event_source; 756 enum crtc_event event; 757 enum trigger_delay delay; 758 }; 759 760 struct dc_crtc_timing_adjust { 761 uint32_t v_total_min; 762 uint32_t v_total_max; 763 uint32_t v_total_mid; 764 uint32_t v_total_mid_frame_num; 765 }; 766 767 768 /* Passed on init */ 769 enum vram_type { 770 VIDEO_MEMORY_TYPE_GDDR5 = 2, 771 VIDEO_MEMORY_TYPE_DDR3 = 3, 772 VIDEO_MEMORY_TYPE_DDR4 = 4, 773 VIDEO_MEMORY_TYPE_HBM = 5, 774 VIDEO_MEMORY_TYPE_GDDR6 = 6, 775 }; 776 777 enum dwb_cnv_out_bpc { 778 DWB_CNV_OUT_BPC_8BPC = 0, 779 DWB_CNV_OUT_BPC_10BPC = 1, 780 }; 781 782 enum dwb_output_depth { 783 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 784 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 785 }; 786 787 enum dwb_capture_rate { 788 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 789 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 790 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 791 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 792 }; 793 794 enum dwb_scaler_mode { 795 dwb_scaler_mode_bypass444 = 0, 796 dwb_scaler_mode_rgb444 = 1, 797 dwb_scaler_mode_yuv444 = 2, 798 dwb_scaler_mode_yuv420 = 3 799 }; 800 801 enum dwb_subsample_position { 802 DWB_INTERSTITIAL_SUBSAMPLING = 0, 803 DWB_COSITED_SUBSAMPLING = 1 804 }; 805 806 enum dwb_stereo_eye_select { 807 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 808 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 809 }; 810 811 enum dwb_stereo_type { 812 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 813 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 814 }; 815 816 #define MCIF_BUF_COUNT 4 817 818 struct mcif_buf_params { 819 unsigned long long luma_address[MCIF_BUF_COUNT]; 820 unsigned long long chroma_address[MCIF_BUF_COUNT]; 821 unsigned int luma_pitch; 822 unsigned int chroma_pitch; 823 unsigned int warmup_pitch; 824 unsigned int swlock; 825 }; 826 827 828 #define MAX_TG_COLOR_VALUE 0x3FF 829 struct tg_color { 830 /* Maximum 10 bits color value */ 831 uint16_t color_r_cr; 832 uint16_t color_g_y; 833 uint16_t color_b_cb; 834 }; 835 836 #endif /* DC_HW_TYPES_H */ 837 838
Indexes created Sun Sep 21 15:09:59 GMT 2025