1 /* $NetBSD: becc_intr.h,v 1.7 2018/01/24 09:04:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _BECC_INTR_H_ 39 #define _BECC_INTR_H_ 40 41 #include <arm/armreg.h> 42 #include <arm/cpufunc.h> 43 #include <arm/cpu.h> 44 45 #include <arm/xscale/beccreg.h> 46 #include <arm/xscale/becc_csrvar.h> 47 48 static inline void __attribute__((__unused__)) 49 becc_set_intrmask(void) 50 { 51 extern volatile uint32_t intr_enabled; 52 53 /* 54 * The bits in the ICMR indicate which interrupts are masked 55 * (disabled), so we must invert our intr_enabled mask. 56 */ 57 58 BECC_CSR_WRITE(BECC_ICMR, ~intr_enabled & ICU_VALID_MASK); 59 (void) BECC_CSR_READ(BECC_ICMR); 60 } 61 62 static inline int __attribute__((__unused__)) 63 becc_splraise(int ipl) 64 { 65 extern uint32_t becc_imask[]; 66 uint32_t old = curcpl(); 67 68 set_curcpl(old | becc_imask[ipl]); 69 70 return (old); 71 } 72 73 static inline void __attribute__((__unused__)) 74 becc_splx(int new) 75 { 76 extern volatile uint32_t intr_enabled, becc_ipending; 77 uint32_t oldirqstate, hwpend; 78 79 set_curcpl(new); 80 81 /* 82 * If there are pending HW interrupts which are being 83 * unmasked, then enable them in the ICMR register. 84 * This will cause them to come flooding in. This 85 * includes soft interrupts. 86 */ 87 hwpend = becc_ipending & ~new; 88 if (hwpend != 0) { 89 oldirqstate = disable_interrupts(I32_bit); 90 intr_enabled |= hwpend; 91 becc_set_intrmask(); 92 restore_interrupts(oldirqstate); 93 } 94 } 95 96 static inline int __attribute__((__unused__)) 97 becc_spllower(int ipl) 98 { 99 extern uint32_t becc_imask[]; 100 uint32_t old = curcpl(); 101 102 becc_splx(becc_imask[ipl]); 103 return (old); 104 } 105 106 #if !defined(EVBARM_SPL_NOINLINE) 107 108 #define _splraise(ipl) becc_splraise(ipl) 109 #define splx(new) becc_splx(new) 110 #define _spllower(ipl) becc_spllower(ipl) 111 #ifdef __HAVE_FAST_SOFTINTS 112 #define _setsoftintr(si) becc_setsoftintr(si) 113 #endif 114 115 #else 116 117 int _splraise(int); 118 void splx(int); 119 int _spllower(int); 120 #ifdef __HAVE_FAST_SOFTINTS 121 void _setsoftintr(int); 122 #endif 123 124 #endif /* ! EVBARM_SPL_NOINLINE */ 125 126 #endif /* _BECC_INTR_H_ */ 127