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    Searched defs:bo_size (Results 1 - 25 of 42) sorted by relevancy

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  /xsrc/external/mit/MesaLib/dist/src/panfrost/vulkan/
panvk_vX_image.c 139 unsigned bo_size = local
145 view->bo = panfrost_bo_create(pdev, bo_size, 0, "Texture descriptor");
panvk_vX_pipeline.c 196 unsigned bo_size = 0; local
206 bo_size = ALIGN_POT(bo_size, pan_alignment(RENDERER_STATE));
207 builder->stages[i].rsd_offset = bo_size;
208 bo_size += pan_size(RENDERER_STATE);
210 bo_size += pan_size(BLEND) * MAX2(pipeline->blend.state.rt_count, 1);
215 bo_size = ALIGN_POT(bo_size, pan_alignment(VIEWPORT));
216 builder->vpd_offset = bo_size;
217 bo_size += pan_size(VIEWPORT)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/asahi/
agx_blit.c 57 unsigned bo_size = 4096; local
59 struct agx_bo *bo = agx_bo_create(dev, bo_size, AGX_MEMORY_TYPE_SHADER);
75 assert(offset + binary.size < bo_size);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/v3d/
v3d_screen.h 77 uint32_t bo_size; member in struct:v3d_screen
  /xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
v3dv_query.c 63 const uint32_t bo_size = query_groups * 1024; local
64 pool->bo = v3dv_bo_alloc(device, bo_size, "query", true);
69 if (!v3dv_bo_map(device, pool->bo, bo_size)) {
v3dv_descriptor_set.c 389 /* bo_size is for the descriptor related info that we need to have on a GPU
393 uint32_t bo_size = 0; local
419 bo_size += v3dv_X(device, descriptor_bo_size)(pCreateInfo->pPoolSizes[i].type) *
446 if (bo_size > 0) {
447 pool->bo = v3dv_bo_alloc(device, bo_size, "descriptor pool bo", true);
607 set_layout->bo_size = 0;
662 set_layout->binding[binding_number].descriptor_offset = set_layout->bo_size;
663 set_layout->bo_size +=
744 if (layout->bo_size) {
760 if (pool->current_offset + layout->bo_size <= pool->bo->size)
1105 uint32_t bo_size = 0; local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/
nouveau_context.h 50 unsigned bo_size; member in struct:nouveau_context::__anon1393
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/v3d/
v3d_screen.h 77 uint32_t bo_size; member in struct:v3d_screen
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/
nouveau_context.h 50 unsigned bo_size; member in struct:nouveau_context::__anon3830
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a2xx/
fd2_gmem.c 599 uint32_t bo_size = align(batch->num_vertices, 0x10000); variable
601 fd_bo_size(ctx->vsc_pipe_bo[i]) < bo_size) {
605 fd_bo_new(ctx->dev, bo_size, 0, "vsc_pipe[%u]", i);
618 OUT_RING(ring, 0x4B000000 | bo_size);
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
vc4_screen.h 86 uint32_t bo_size; member in struct:vc4_screen::vc4_bo_cache
93 uint32_t bo_size; member in struct:vc4_screen
  /xsrc/external/mit/MesaLib/dist/src/intel/tools/
intel_sanitize_gpu.c 93 bo_size(int fd, uint32_t handle) function
168 .offset = align64(bo_size(fd, handle), 4096),
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
vc4_screen.h 86 uint32_t bo_size; member in struct:vc4_screen::vc4_bo_cache
93 uint32_t bo_size; member in struct:vc4_screen
  /xsrc/external/mit/MesaLib.old/dist/src/intel/tools/
intel_sanitize_gpu.c 93 bo_size(int fd, uint32_t handle) function
168 .offset = align64(bo_size(fd, handle), 4096),
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
nv84_video.c 613 unsigned bo_size; local
675 bo_size = mt0->total_size + mt1->total_size;
677 bo_size, &cfg, &buffer->interlaced))
682 bo_size, &cfg, &buffer->full))
  /xsrc/external/mit/MesaLib.old/dist/src/freedreno/drm/
freedreno_priv.h 100 int bo_size; member in struct:fd_device
234 VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size);
235 VALGRIND_MAKE_MEM_NOACCESS(bo, bo->dev->bo_size);
242 VALGRIND_MAKE_MEM_DEFINED(bo, bo->dev->bo_size);
243 VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
nv84_video.c 613 unsigned bo_size; local
676 bo_size = mt0->total_size + mt1->total_size;
678 bo_size, &cfg, &buffer->interlaced))
683 bo_size, &cfg, &buffer->full))
  /xsrc/external/mit/libdrm/dist/freedreno/
freedreno_priv.h 106 int bo_size; member in struct:fd_device
237 VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size);
238 VALGRIND_MAKE_MEM_NOACCESS(bo, bo->dev->bo_size);
245 VALGRIND_MAKE_MEM_DEFINED(bo, bo->dev->bo_size);
246 VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size);
  /xsrc/external/mit/libdrm/dist/radeon/
radeon_surface.h 127 uint64_t bo_size; member in struct:radeon_surface
  /xsrc/external/mit/MesaLib/dist/src/freedreno/drm/
freedreno_priv.h 138 int bo_size; member in struct:fd_device
398 VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size);
399 VALGRIND_MAKE_MEM_NOACCESS(bo, bo->dev->bo_size);
407 VALGRIND_MAKE_MEM_DEFINED(bo, bo->dev->bo_size);
408 VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(bo, bo->dev->bo_size);
  /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
tu_descriptor_set.c 587 uint64_t bo_size = 0, bo_count = 0, dynamic_count = 0; local
606 bo_size +=
614 bo_size += A6XX_TEX_CONST_DWORDS * 4 *
622 bo_size += descriptor_size(pCreateInfo->pPoolSizes[i].type) *
646 if (bo_size) {
648 ret = tu_bo_init_new(device, &pool->bo, bo_size, TU_BO_ALLOC_ALLOW_DUMP);
656 pool->host_bo = vk_alloc2(&device->vk.alloc, pAllocator, bo_size, 8,
664 pool->size = bo_size;
tu_device.c 1766 unsigned bo_size = 1ull << size_log2; local
1767 VkResult result = tu_bo_init_new(dev, &dev->scratch_bos[index].bo, bo_size,
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
radv_descriptor_set.c 628 uint64_t bo_size = 0, bo_count = 0, range_count = 0; local
638 bo_size += 28llu * info->maxInlineUniformBlockBindings;
661 bo_size += 32 * pCreateInfo->pPoolSizes[i].descriptorCount;
666 bo_size += 64 * pCreateInfo->pPoolSizes[i].descriptorCount;
669 bo_size += 96 * pCreateInfo->pPoolSizes[i].descriptorCount;
672 bo_size += pCreateInfo->pPoolSizes[i].descriptorCount;
702 if (bo_size) {
703 pool->bo = device->ws->buffer_create(device->ws, bo_size, 32,
711 pool->size = bo_size;
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_descriptor_set.c 720 uint64_t bo_size = 0, bo_count = 0, range_count = 0; local
734 bo_size += 28llu * info->maxInlineUniformBlockBindings;
759 bo_size += 32 * pCreateInfo->pPoolSizes[i].descriptorCount;
763 bo_size += 64 * pCreateInfo->pPoolSizes[i].descriptorCount;
777 bo_size += mutable_size * pCreateInfo->pPoolSizes[i].descriptorCount;
780 bo_size += 64 * pCreateInfo->pPoolSizes[i].descriptorCount;
784 bo_size += 96 * pCreateInfo->pPoolSizes[i].descriptorCount;
787 bo_size += pCreateInfo->pPoolSizes[i].descriptorCount;
817 if (bo_size) {
820 device->ws, bo_size, 32, RADEON_DOMAIN_VRAM
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
crocus_bufmgr.c 347 alloc_fresh_bo(struct crocus_bufmgr *bufmgr, uint64_t bo_size)
353 struct drm_i915_gem_create create = { .size = bo_size };
365 bo->size = bo_size;
405 uint64_t bo_size = local
418 bo = alloc_fresh_bo(bufmgr, bo_size);

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