1 /************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 /** 30 * @file 31 * 32 * Abstract graphics pipe state objects. 33 * 34 * Basic notes: 35 * 1. Want compact representations, so we use bitfields. 36 * 2. Put bitfields before other (GLfloat) fields. 37 * 3. enum bitfields need to be at least one bit extra in size so the most 38 * significant bit is zero. MSVC treats enums as signed so if the high 39 * bit is set, the value will be interpreted as a negative number. 40 * That causes trouble in various places. 41 */ 42 43 44 #ifndef PIPE_STATE_H 45 #define PIPE_STATE_H 46 47 #include "p_compiler.h" 48 #include "p_defines.h" 49 #include "p_format.h" 50 51 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 56 57 /** 58 * Implementation limits 59 */ 60 #define PIPE_MAX_ATTRIBS 32 61 #define PIPE_MAX_CLIP_PLANES 8 62 #define PIPE_MAX_COLOR_BUFS 8 63 #define PIPE_MAX_CONSTANT_BUFFERS 32 64 #define PIPE_MAX_SAMPLERS 32 65 #define PIPE_MAX_SHADER_INPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */ 66 #define PIPE_MAX_SHADER_OUTPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */ 67 #define PIPE_MAX_SHADER_SAMPLER_VIEWS 128 68 #define PIPE_MAX_SHADER_BUFFERS 32 69 #define PIPE_MAX_SHADER_IMAGES 32 70 #define PIPE_MAX_TEXTURE_LEVELS 16 71 #define PIPE_MAX_SO_BUFFERS 4 72 #define PIPE_MAX_SO_OUTPUTS 64 73 #define PIPE_MAX_VIEWPORTS 16 74 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8 75 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2 76 #define PIPE_MAX_WINDOW_RECTANGLES 8 77 #define PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE 4 78 79 #define PIPE_MAX_HW_ATOMIC_BUFFERS 32 80 #define PIPE_MAX_VERTEX_STREAMS 4 81 82 struct pipe_reference 83 { 84 int32_t count; /* atomic */ 85 }; 86 87 88 89 /** 90 * Primitive (point/line/tri) rasterization info 91 */ 92 struct pipe_rasterizer_state 93 { 94 unsigned flatshade:1; 95 unsigned light_twoside:1; 96 unsigned clamp_vertex_color:1; 97 unsigned clamp_fragment_color:1; 98 unsigned front_ccw:1; 99 unsigned cull_face:2; /**< PIPE_FACE_x */ 100 unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */ 101 unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */ 102 unsigned offset_point:1; 103 unsigned offset_line:1; 104 unsigned offset_tri:1; 105 unsigned scissor:1; 106 unsigned poly_smooth:1; 107 unsigned poly_stipple_enable:1; 108 unsigned point_smooth:1; 109 unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */ 110 unsigned point_quad_rasterization:1; /** points rasterized as quads or points */ 111 unsigned point_tri_clip:1; /** large points clipped as tris or points */ 112 unsigned point_size_per_vertex:1; /**< size computed in vertex shader */ 113 unsigned multisample:1; /* XXX maybe more ms state in future */ 114 unsigned force_persample_interp:1; 115 unsigned line_smooth:1; 116 unsigned line_stipple_enable:1; 117 unsigned line_last_pixel:1; 118 unsigned conservative_raster_mode:2; /**< PIPE_CONSERVATIVE_RASTER_x */ 119 120 /** 121 * Use the first vertex of a primitive as the provoking vertex for 122 * flat shading. 123 */ 124 unsigned flatshade_first:1; 125 126 unsigned half_pixel_center:1; 127 unsigned bottom_edge_rule:1; 128 129 /* 130 * Conservative rasterization subpixel precision bias in bits 131 */ 132 unsigned subpixel_precision_x:4; 133 unsigned subpixel_precision_y:4; 134 135 /** 136 * When true, rasterization is disabled and no pixels are written. 137 * This only makes sense with the Stream Out functionality. 138 */ 139 unsigned rasterizer_discard:1; 140 141 /** 142 * Exposed by PIPE_CAP_TILE_RASTER_ORDER. When true, 143 * tile_raster_order_increasing_* indicate the order that the rasterizer 144 * should render tiles, to meet the requirements of 145 * GL_MESA_tile_raster_order. 146 */ 147 unsigned tile_raster_order_fixed:1; 148 unsigned tile_raster_order_increasing_x:1; 149 unsigned tile_raster_order_increasing_y:1; 150 151 /** 152 * When false, depth clipping is disabled and the depth value will be 153 * clamped later at the per-pixel level before depth testing. 154 * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE. 155 * 156 * If PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE is unsupported, depth_clip_near 157 * is equal to depth_clip_far. 158 */ 159 unsigned depth_clip_near:1; 160 unsigned depth_clip_far:1; 161 162 /** 163 * When true clip space in the z axis goes from [0..1] (D3D). When false 164 * [-1, 1] (GL). 165 * 166 * NOTE: D3D will always use depth clamping. 167 */ 168 unsigned clip_halfz:1; 169 170 /** 171 * When true do not scale offset_units and use same rules for unorm and 172 * float depth buffers (D3D9). When false use GL/D3D1X behaviour. 173 * This depends on PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. 174 */ 175 unsigned offset_units_unscaled:1; 176 177 /** 178 * Enable bits for clipping half-spaces. 179 * This applies to both user clip planes and shader clip distances. 180 * Note that if the bound shader exports any clip distances, these 181 * replace all user clip planes, and clip half-spaces enabled here 182 * but not written by the shader count as disabled. 183 */ 184 unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES; 185 186 unsigned line_stipple_factor:8; /**< [1..256] actually */ 187 unsigned line_stipple_pattern:16; 188 189 /** 190 * Replace the given TEXCOORD inputs with point coordinates, max. 8 inputs. 191 * If TEXCOORD (including PCOORD) are unsupported, replace GENERIC inputs 192 * instead. Max. 9 inputs: 8x GENERIC to emulate TEXCOORD, and 1x GENERIC 193 * to emulate PCOORD. 194 */ 195 uint16_t sprite_coord_enable; /* 0-7: TEXCOORD/GENERIC, 8: PCOORD */ 196 197 float line_width; 198 float point_size; /**< used when no per-vertex size */ 199 float offset_units; 200 float offset_scale; 201 float offset_clamp; 202 float conservative_raster_dilate; 203 }; 204 205 206 struct pipe_poly_stipple 207 { 208 unsigned stipple[32]; 209 }; 210 211 212 struct pipe_viewport_state 213 { 214 float scale[3]; 215 float translate[3]; 216 }; 217 218 219 struct pipe_scissor_state 220 { 221 unsigned minx:16; 222 unsigned miny:16; 223 unsigned maxx:16; 224 unsigned maxy:16; 225 }; 226 227 228 struct pipe_clip_state 229 { 230 float ucp[PIPE_MAX_CLIP_PLANES][4]; 231 }; 232 233 /** 234 * A single output for vertex transform feedback. 235 */ 236 struct pipe_stream_output 237 { 238 unsigned register_index:6; /**< 0 to 63 (OUT index) */ 239 unsigned start_component:2; /** 0 to 3 */ 240 unsigned num_components:3; /** 1 to 4 */ 241 unsigned output_buffer:3; /**< 0 to PIPE_MAX_SO_BUFFERS */ 242 unsigned dst_offset:16; /**< offset into the buffer in dwords */ 243 unsigned stream:2; /**< 0 to 3 */ 244 }; 245 246 /** 247 * Stream output for vertex transform feedback. 248 */ 249 struct pipe_stream_output_info 250 { 251 unsigned num_outputs; 252 /** stride for an entire vertex for each buffer in dwords */ 253 uint16_t stride[PIPE_MAX_SO_BUFFERS]; 254 255 /** 256 * Array of stream outputs, in the order they are to be written in. 257 * Selected components are tightly packed into the output buffer. 258 */ 259 struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS]; 260 }; 261 262 /** 263 * The 'type' parameter identifies whether the shader state contains TGSI 264 * tokens, etc. If the driver returns 'PIPE_SHADER_IR_TGSI' for the 265 * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be 266 * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid. If the driver 267 * requests a different 'pipe_shader_ir' type, then it must check the 'type' 268 * enum to see if it is getting TGSI tokens or its preferred IR. 269 * 270 * TODO pipe_compute_state should probably get similar treatment to handle 271 * multiple IR's in a cleaner way.. 272 * 273 * NOTE: since it is expected that the consumer will want to perform 274 * additional passes on the nir_shader, the driver takes ownership of 275 * the nir_shader. If state trackers need to hang on to the IR (for 276 * example, variant management), it should use nir_shader_clone(). 277 */ 278 struct pipe_shader_state 279 { 280 enum pipe_shader_ir type; 281 /* TODO move tokens into union. */ 282 const struct tgsi_token *tokens; 283 union { 284 void *native; 285 void *nir; 286 } ir; 287 struct pipe_stream_output_info stream_output; 288 }; 289 290 static inline void 291 pipe_shader_state_from_tgsi(struct pipe_shader_state *state, 292 const struct tgsi_token *tokens) 293 { 294 state->type = PIPE_SHADER_IR_TGSI; 295 state->tokens = tokens; 296 memset(&state->stream_output, 0, sizeof(state->stream_output)); 297 } 298 299 struct pipe_depth_state 300 { 301 unsigned enabled:1; /**< depth test enabled? */ 302 unsigned writemask:1; /**< allow depth buffer writes? */ 303 unsigned func:3; /**< depth test func (PIPE_FUNC_x) */ 304 unsigned bounds_test:1; /**< depth bounds test enabled? */ 305 float bounds_min; /**< minimum depth bound */ 306 float bounds_max; /**< maximum depth bound */ 307 }; 308 309 310 struct pipe_stencil_state 311 { 312 unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */ 313 unsigned func:3; /**< PIPE_FUNC_x */ 314 unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */ 315 unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */ 316 unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */ 317 unsigned valuemask:8; 318 unsigned writemask:8; 319 }; 320 321 322 struct pipe_alpha_state 323 { 324 unsigned enabled:1; 325 unsigned func:3; /**< PIPE_FUNC_x */ 326 float ref_value; /**< reference value */ 327 }; 328 329 330 struct pipe_depth_stencil_alpha_state 331 { 332 struct pipe_depth_state depth; 333 struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */ 334 struct pipe_alpha_state alpha; 335 }; 336 337 338 struct pipe_rt_blend_state 339 { 340 unsigned blend_enable:1; 341 342 unsigned rgb_func:3; /**< PIPE_BLEND_x */ 343 unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */ 344 unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */ 345 346 unsigned alpha_func:3; /**< PIPE_BLEND_x */ 347 unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */ 348 unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */ 349 350 unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */ 351 }; 352 353 354 struct pipe_blend_state 355 { 356 unsigned independent_blend_enable:1; 357 unsigned logicop_enable:1; 358 unsigned logicop_func:4; /**< PIPE_LOGICOP_x */ 359 unsigned dither:1; 360 unsigned alpha_to_coverage:1; 361 unsigned alpha_to_one:1; 362 struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS]; 363 }; 364 365 366 struct pipe_blend_color 367 { 368 float color[4]; 369 }; 370 371 372 struct pipe_stencil_ref 373 { 374 ubyte ref_value[2]; 375 }; 376 377 378 /** 379 * Note that pipe_surfaces are "texture views for rendering" 380 * and so in the case of ARB_framebuffer_no_attachment there 381 * is no pipe_surface state available such that we may 382 * extract the number of samples and layers. 383 */ 384 struct pipe_framebuffer_state 385 { 386 uint16_t width, height; 387 uint16_t layers; /**< Number of layers in a no-attachment framebuffer */ 388 ubyte samples; /**< Number of samples in a no-attachment framebuffer */ 389 390 /** multiple color buffers for multiple render targets */ 391 ubyte nr_cbufs; 392 struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS]; 393 394 struct pipe_surface *zsbuf; /**< Z/stencil buffer */ 395 }; 396 397 398 /** 399 * Texture sampler state. 400 */ 401 struct pipe_sampler_state 402 { 403 unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */ 404 unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */ 405 unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */ 406 unsigned min_img_filter:1; /**< PIPE_TEX_FILTER_x */ 407 unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */ 408 unsigned mag_img_filter:1; /**< PIPE_TEX_FILTER_x */ 409 unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */ 410 unsigned compare_func:3; /**< PIPE_FUNC_x */ 411 unsigned normalized_coords:1; /**< Are coords normalized to [0,1]? */ 412 unsigned max_anisotropy:5; 413 unsigned seamless_cube_map:1; 414 float lod_bias; /**< LOD/lambda bias */ 415 float min_lod, max_lod; /**< LOD clamp range, after bias */ 416 union pipe_color_union border_color; 417 }; 418 419 union pipe_surface_desc { 420 struct { 421 unsigned level; 422 unsigned first_layer:16; 423 unsigned last_layer:16; 424 } tex; 425 struct { 426 unsigned first_element; 427 unsigned last_element; 428 } buf; 429 }; 430 431 /** 432 * A view into a texture that can be bound to a color render target / 433 * depth stencil attachment point. 434 */ 435 struct pipe_surface 436 { 437 struct pipe_reference reference; 438 enum pipe_format format:16; 439 unsigned writable:1; /**< writable shader resource */ 440 struct pipe_resource *texture; /**< resource into which this is a view */ 441 struct pipe_context *context; /**< context this surface belongs to */ 442 443 /* XXX width/height should be removed */ 444 uint16_t width; /**< logical width in pixels */ 445 uint16_t height; /**< logical height in pixels */ 446 447 /** 448 * Number of samples for the surface. This will be 0 if rendering 449 * should use the resource's nr_samples, or another value if the resource 450 * is bound using FramebufferTexture2DMultisampleEXT. 451 */ 452 unsigned nr_samples:8; 453 454 union pipe_surface_desc u; 455 }; 456 457 458 /** 459 * A view into a texture that can be bound to a shader stage. 460 */ 461 struct pipe_sampler_view 462 { 463 struct pipe_reference reference; 464 enum pipe_format format:15; /**< typed PIPE_FORMAT_x */ 465 enum pipe_texture_target target:5; /**< PIPE_TEXTURE_x */ 466 unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */ 467 unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */ 468 unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */ 469 unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */ 470 struct pipe_resource *texture; /**< texture into which this is a view */ 471 struct pipe_context *context; /**< context this view belongs to */ 472 union { 473 struct { 474 unsigned first_layer:16; /**< first layer to use for array textures */ 475 unsigned last_layer:16; /**< last layer to use for array textures */ 476 unsigned first_level:8; /**< first mipmap level to use */ 477 unsigned last_level:8; /**< last mipmap level to use */ 478 } tex; 479 struct { 480 unsigned offset; /**< offset in bytes */ 481 unsigned size; /**< size of the readable sub-range in bytes */ 482 } buf; 483 } u; 484 }; 485 486 487 /** 488 * A description of a buffer or texture image that can be bound to a shader 489 * stage. 490 */ 491 struct pipe_image_view 492 { 493 struct pipe_resource *resource; /**< resource into which this is a view */ 494 enum pipe_format format; /**< typed PIPE_FORMAT_x */ 495 uint16_t access; /**< PIPE_IMAGE_ACCESS_x */ 496 uint16_t shader_access; /**< PIPE_IMAGE_ACCESS_x */ 497 498 union { 499 struct { 500 unsigned first_layer:16; /**< first layer to use for array textures */ 501 unsigned last_layer:16; /**< last layer to use for array textures */ 502 unsigned level:8; /**< mipmap level to use */ 503 } tex; 504 struct { 505 unsigned offset; /**< offset in bytes */ 506 unsigned size; /**< size of the accessible sub-range in bytes */ 507 } buf; 508 } u; 509 }; 510 511 512 /** 513 * Subregion of 1D/2D/3D image resource. 514 */ 515 struct pipe_box 516 { 517 /* Fields only used by textures use int16_t instead of int. 518 * x and width are used by buffers, so they need the full 32-bit range. 519 */ 520 int x; 521 int16_t y; 522 int16_t z; 523 int width; 524 int16_t height; 525 int16_t depth; 526 }; 527 528 529 /** 530 * A memory object/resource such as a vertex buffer or texture. 531 */ 532 struct pipe_resource 533 { 534 struct pipe_reference reference; 535 536 unsigned width0; /**< Used by both buffers and textures. */ 537 uint16_t height0; /* Textures: The maximum height/depth/array_size is 16k. */ 538 uint16_t depth0; 539 uint16_t array_size; 540 541 enum pipe_format format:16; /**< PIPE_FORMAT_x */ 542 enum pipe_texture_target target:8; /**< PIPE_TEXTURE_x */ 543 unsigned last_level:8; /**< Index of last mipmap level present/defined */ 544 545 /** Number of samples determining quality, driving rasterizer, shading, 546 * and framebuffer. 547 */ 548 unsigned nr_samples:8; 549 550 /** Multiple samples within a pixel can have the same value. 551 * nr_storage_samples determines how many slots for different values 552 * there are per pixel. Only color buffers can set this lower than 553 * nr_samples. 554 */ 555 unsigned nr_storage_samples:8; 556 557 unsigned usage:8; /**< PIPE_USAGE_x (not a bitmask) */ 558 unsigned bind; /**< bitmask of PIPE_BIND_x */ 559 unsigned flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */ 560 561 /** 562 * For planar images, ie. YUV EGLImage external, etc, pointer to the 563 * next plane. 564 */ 565 struct pipe_resource *next; 566 /* The screen pointer should be last for optimal structure packing. */ 567 struct pipe_screen *screen; /**< screen that this texture belongs to */ 568 }; 569 570 571 /** 572 * Transfer object. For data transfer to/from a resource. 573 */ 574 struct pipe_transfer 575 { 576 struct pipe_resource *resource; /**< resource to transfer to/from */ 577 unsigned level; /**< texture mipmap level */ 578 enum pipe_transfer_usage usage; 579 struct pipe_box box; /**< region of the resource to access */ 580 unsigned stride; /**< row stride in bytes */ 581 unsigned layer_stride; /**< image/layer stride in bytes */ 582 }; 583 584 585 /** 586 * A vertex buffer. Typically, all the vertex data/attributes for 587 * drawing something will be in one buffer. But it's also possible, for 588 * example, to put colors in one buffer and texcoords in another. 589 */ 590 struct pipe_vertex_buffer 591 { 592 uint16_t stride; /**< stride to same attrib in next vertex, in bytes */ 593 bool is_user_buffer; 594 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 595 596 union { 597 struct pipe_resource *resource; /**< the actual buffer */ 598 const void *user; /**< pointer to a user buffer */ 599 } buffer; 600 }; 601 602 603 /** 604 * A constant buffer. A subrange of an existing buffer can be set 605 * as a constant buffer. 606 */ 607 struct pipe_constant_buffer 608 { 609 struct pipe_resource *buffer; /**< the actual buffer */ 610 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 611 unsigned buffer_size; /**< how much data can be read in shader */ 612 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */ 613 }; 614 615 616 /** 617 * An untyped shader buffer supporting loads, stores, and atomics. 618 */ 619 struct pipe_shader_buffer { 620 struct pipe_resource *buffer; /**< the actual buffer */ 621 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 622 unsigned buffer_size; /**< how much data can be read in shader */ 623 }; 624 625 626 /** 627 * A stream output target. The structure specifies the range vertices can 628 * be written to. 629 * 630 * In addition to that, the structure should internally maintain the offset 631 * into the buffer, which should be incremented everytime something is written 632 * (appended) to it. The internal offset is buffer_offset + how many bytes 633 * have been written. The internal offset can be stored on the device 634 * and the CPU actually doesn't have to query it. 635 * 636 * Note that the buffer_size variable is actually specifying the available 637 * space in the buffer, not the size of the attached buffer. 638 * In other words in majority of cases buffer_size would simply be 639 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size 640 * of the buffer left, after accounting for buffer offset, for stream output 641 * to write to. 642 * 643 * Use PIPE_QUERY_SO_STATISTICS to know how many primitives have 644 * actually been written. 645 */ 646 struct pipe_stream_output_target 647 { 648 struct pipe_reference reference; 649 struct pipe_resource *buffer; /**< the output buffer */ 650 struct pipe_context *context; /**< context this SO target belongs to */ 651 652 unsigned buffer_offset; /**< offset where data should be written, in bytes */ 653 unsigned buffer_size; /**< how much data is allowed to be written */ 654 }; 655 656 657 /** 658 * Information to describe a vertex attribute (position, color, etc) 659 */ 660 struct pipe_vertex_element 661 { 662 /** Offset of this attribute, in bytes, from the start of the vertex */ 663 unsigned src_offset:16; 664 665 /** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does 666 * this attribute live in? 667 */ 668 unsigned vertex_buffer_index:5; 669 670 enum pipe_format src_format:11; 671 672 /** Instance data rate divisor. 0 means this is per-vertex data, 673 * n means per-instance data used for n consecutive instances (n > 0). 674 */ 675 unsigned instance_divisor; 676 }; 677 678 679 struct pipe_draw_indirect_info 680 { 681 unsigned offset; /**< must be 4 byte aligned */ 682 unsigned stride; /**< must be 4 byte aligned */ 683 unsigned draw_count; /**< number of indirect draws */ 684 unsigned indirect_draw_count_offset; /**< must be 4 byte aligned */ 685 686 /* Indirect draw parameters resource is laid out as follows: 687 * 688 * if using indexed drawing: 689 * struct { 690 * uint32_t count; 691 * uint32_t instance_count; 692 * uint32_t start; 693 * int32_t index_bias; 694 * uint32_t start_instance; 695 * }; 696 * otherwise: 697 * struct { 698 * uint32_t count; 699 * uint32_t instance_count; 700 * uint32_t start; 701 * uint32_t start_instance; 702 * }; 703 */ 704 struct pipe_resource *buffer; 705 706 /* Indirect draw count resource: If not NULL, contains a 32-bit value which 707 * is to be used as the real draw_count. 708 */ 709 struct pipe_resource *indirect_draw_count; 710 }; 711 712 713 /** 714 * Information to describe a draw_vbo call. 715 */ 716 struct pipe_draw_info 717 { 718 ubyte index_size; /**< if 0, the draw is not indexed. */ 719 enum pipe_prim_type mode:8; /**< the mode of the primitive */ 720 unsigned primitive_restart:1; 721 unsigned has_user_indices:1; /**< if true, use index.user_buffer */ 722 ubyte vertices_per_patch; /**< the number of vertices per patch */ 723 724 /** 725 * Direct draws: start is the index of the first vertex 726 * Non-indexed indirect draws: not used 727 * Indexed indirect draws: start is added to the indirect start. 728 */ 729 unsigned start; 730 unsigned count; /**< number of vertices */ 731 732 unsigned start_instance; /**< first instance id */ 733 unsigned instance_count; /**< number of instances */ 734 735 unsigned drawid; /**< id of this draw in a multidraw */ 736 737 /** 738 * For indexed drawing, these fields apply after index lookup. 739 */ 740 int index_bias; /**< a bias to be added to each index */ 741 unsigned min_index; /**< the min index */ 742 unsigned max_index; /**< the max index */ 743 744 /** 745 * Primitive restart enable/index (only applies to indexed drawing) 746 */ 747 unsigned restart_index; 748 749 /* Pointers must be at the end for an optimal structure layout on 64-bit. */ 750 751 /** 752 * An index buffer. When an index buffer is bound, all indices to vertices 753 * will be looked up from the buffer. 754 * 755 * If has_user_indices, use index.user, else use index.resource. 756 */ 757 union { 758 struct pipe_resource *resource; /**< real buffer */ 759 const void *user; /**< pointer to a user buffer */ 760 } index; 761 762 struct pipe_draw_indirect_info *indirect; /**< Indirect draw. */ 763 764 /** 765 * Stream output target. If not NULL, it's used to provide the 'count' 766 * parameter based on the number vertices captured by the stream output 767 * stage. (or generally, based on the number of bytes captured) 768 * 769 * Only 'mode', 'start_instance', and 'instance_count' are taken into 770 * account, all the other variables from pipe_draw_info are ignored. 771 * 772 * 'start' is implicitly 0 and 'count' is set as discussed above. 773 * The draw command is non-indexed. 774 * 775 * Note that this only provides the count. The vertex buffers must 776 * be set via set_vertex_buffers manually. 777 */ 778 struct pipe_stream_output_target *count_from_stream_output; 779 }; 780 781 782 /** 783 * Information to describe a blit call. 784 */ 785 struct pipe_blit_info 786 { 787 struct { 788 struct pipe_resource *resource; 789 unsigned level; 790 struct pipe_box box; /**< negative width, height only legal for src */ 791 /* For pipe_surface-like format casting: */ 792 enum pipe_format format; /**< must be supported for sampling (src) 793 or rendering (dst), ZS is always supported */ 794 } dst, src; 795 796 unsigned mask; /**< bitmask of PIPE_MASK_R/G/B/A/Z/S */ 797 unsigned filter; /**< PIPE_TEX_FILTER_* */ 798 799 boolean scissor_enable; 800 struct pipe_scissor_state scissor; 801 802 /* Window rectangles can either be inclusive or exclusive. */ 803 boolean window_rectangle_include; 804 unsigned num_window_rectangles; 805 struct pipe_scissor_state window_rectangles[PIPE_MAX_WINDOW_RECTANGLES]; 806 807 boolean render_condition_enable; /**< whether the blit should honor the 808 current render condition */ 809 boolean alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */ 810 }; 811 812 /** 813 * Information to describe a launch_grid call. 814 */ 815 struct pipe_grid_info 816 { 817 /** 818 * For drivers that use PIPE_SHADER_IR_NATIVE as their prefered IR, this 819 * value will be the index of the kernel in the opencl.kernels metadata 820 * list. 821 */ 822 uint32_t pc; 823 824 /** 825 * Will be used to initialize the INPUT resource, and it should point to a 826 * buffer of at least pipe_compute_state::req_input_mem bytes. 827 */ 828 void *input; 829 830 /** 831 * Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to 832 * clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with 833 * 1 for non-used dimensions. 834 */ 835 uint work_dim; 836 837 /** 838 * Determine the layout of the working block (in thread units) to be used. 839 */ 840 uint block[3]; 841 842 /** 843 * last_block allows disabling threads at the farthermost grid boundary. 844 * Full blocks as specified by "block" are launched, but the threads 845 * outside of "last_block" dimensions are disabled. 846 * 847 * If a block touches the grid boundary in the i-th axis, threads with 848 * THREAD_ID[i] >= last_block[i] are disabled. 849 * 850 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i], 851 * meaning no effect. 852 * 853 * It's equivalent to doing this at the beginning of the compute shader: 854 * 855 * for (i = 0; i < 3; i++) { 856 * if (block_id[i] == grid[i] - 1 && 857 * last_block[i] && thread_id[i] >= last_block[i]) 858 * return; 859 * } 860 */ 861 uint last_block[3]; 862 863 /** 864 * Determine the layout of the grid (in block units) to be used. 865 */ 866 uint grid[3]; 867 868 /* Indirect compute parameters resource: If not NULL, block sizes are taken 869 * from this buffer instead, which is laid out as follows: 870 * 871 * struct { 872 * uint32_t num_blocks_x; 873 * uint32_t num_blocks_y; 874 * uint32_t num_blocks_z; 875 * }; 876 */ 877 struct pipe_resource *indirect; 878 unsigned indirect_offset; /**< must be 4 byte aligned */ 879 }; 880 881 /** 882 * Structure used as a header for serialized LLVM programs. 883 */ 884 struct pipe_llvm_program_header 885 { 886 uint32_t num_bytes; /**< Number of bytes in the LLVM bytecode program. */ 887 }; 888 889 struct pipe_compute_state 890 { 891 enum pipe_shader_ir ir_type; /**< IR type contained in prog. */ 892 const void *prog; /**< Compute program to be executed. */ 893 unsigned req_local_mem; /**< Required size of the LOCAL resource. */ 894 unsigned req_private_mem; /**< Required size of the PRIVATE resource. */ 895 unsigned req_input_mem; /**< Required size of the INPUT resource. */ 896 }; 897 898 /** 899 * Structure that contains a callback for debug messages from the driver back 900 * to the state tracker. 901 */ 902 struct pipe_debug_callback 903 { 904 /** 905 * When set to \c true, the callback may be called asynchronously from a 906 * driver-created thread. 907 */ 908 bool async; 909 910 /** 911 * Callback for the driver to report debug/performance/etc information back 912 * to the state tracker. 913 * 914 * \param data user-supplied data pointer 915 * \param id message type identifier, if pointed value is 0, then a 916 * new id is assigned 917 * \param type PIPE_DEBUG_TYPE_* 918 * \param format printf-style format string 919 * \param args args for format string 920 */ 921 void (*debug_message)(void *data, 922 unsigned *id, 923 enum pipe_debug_type type, 924 const char *fmt, 925 va_list args); 926 void *data; 927 }; 928 929 /** 930 * Structure that contains a callback for device reset messages from the driver 931 * back to the state tracker. 932 * 933 * The callback must not be called from driver-created threads. 934 */ 935 struct pipe_device_reset_callback 936 { 937 /** 938 * Callback for the driver to report when a device reset is detected. 939 * 940 * \param data user-supplied data pointer 941 * \param status PIPE_*_RESET 942 */ 943 void (*reset)(void *data, enum pipe_reset_status status); 944 945 void *data; 946 }; 947 948 /** 949 * Information about memory usage. All sizes are in kilobytes. 950 */ 951 struct pipe_memory_info 952 { 953 unsigned total_device_memory; /**< size of device memory, e.g. VRAM */ 954 unsigned avail_device_memory; /**< free device memory at the moment */ 955 unsigned total_staging_memory; /**< size of staging memory, e.g. GART */ 956 unsigned avail_staging_memory; /**< free staging memory at the moment */ 957 unsigned device_memory_evicted; /**< size of memory evicted (monotonic counter) */ 958 unsigned nr_device_memory_evictions; /**< # of evictions (monotonic counter) */ 959 }; 960 961 /** 962 * Structure that contains information about external memory 963 */ 964 struct pipe_memory_object 965 { 966 bool dedicated; 967 }; 968 969 #ifdef __cplusplus 970 } 971 #endif 972 973 #endif 974
Indexes created Thu Aug 06 00:25:04 UTC 2026