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      1 /*	$NetBSD: amdgpu_sdma.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2018 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef __AMDGPU_SDMA_H__
     27 #define __AMDGPU_SDMA_H__
     28 
     29 /* max number of IP instances */
     30 #define AMDGPU_MAX_SDMA_INSTANCES		8
     31 
     32 enum amdgpu_sdma_irq {
     33 	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
     34 	AMDGPU_SDMA_IRQ_INSTANCE1,
     35 	AMDGPU_SDMA_IRQ_INSTANCE2,
     36 	AMDGPU_SDMA_IRQ_INSTANCE3,
     37 	AMDGPU_SDMA_IRQ_INSTANCE4,
     38 	AMDGPU_SDMA_IRQ_INSTANCE5,
     39 	AMDGPU_SDMA_IRQ_INSTANCE6,
     40 	AMDGPU_SDMA_IRQ_INSTANCE7,
     41 	AMDGPU_SDMA_IRQ_LAST
     42 };
     43 
     44 struct amdgpu_sdma_instance {
     45 	/* SDMA firmware */
     46 	const struct firmware	*fw;
     47 	uint32_t		fw_version;
     48 	uint32_t		feature_version;
     49 
     50 	struct amdgpu_ring	ring;
     51 	struct amdgpu_ring	page;
     52 	bool			burst_nop;
     53 };
     54 
     55 struct amdgpu_sdma_ras_funcs {
     56 	int (*ras_late_init)(struct amdgpu_device *adev,
     57 			void *ras_ih_info);
     58 	void (*ras_fini)(struct amdgpu_device *adev);
     59 	int (*query_ras_error_count)(struct amdgpu_device *adev,
     60 			uint32_t instance, void *ras_error_status);
     61 };
     62 
     63 struct amdgpu_sdma {
     64 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
     65 	struct drm_gpu_scheduler    *sdma_sched[AMDGPU_MAX_SDMA_INSTANCES];
     66 	uint32_t		    num_sdma_sched;
     67 	struct amdgpu_irq_src	trap_irq;
     68 	struct amdgpu_irq_src	illegal_inst_irq;
     69 	struct amdgpu_irq_src	ecc_irq;
     70 	int			num_instances;
     71 	uint32_t                    srbm_soft_reset;
     72 	bool			has_page_queue;
     73 	struct ras_common_if	*ras_if;
     74 	const struct amdgpu_sdma_ras_funcs	*funcs;
     75 };
     76 
     77 /*
     78  * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
     79  * But currently, we use sdma to move data.
     80  */
     81 struct amdgpu_buffer_funcs {
     82 	/* maximum bytes in a single operation */
     83 	uint32_t	copy_max_bytes;
     84 
     85 	/* number of dw to reserve per operation */
     86 	unsigned	copy_num_dw;
     87 
     88 	/* used for buffer migration */
     89 	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
     90 				 /* src addr in bytes */
     91 				 uint64_t src_offset,
     92 				 /* dst addr in bytes */
     93 				 uint64_t dst_offset,
     94 				 /* number of byte to transfer */
     95 				 uint32_t byte_count);
     96 
     97 	/* maximum bytes in a single operation */
     98 	uint32_t	fill_max_bytes;
     99 
    100 	/* number of dw to reserve per operation */
    101 	unsigned	fill_num_dw;
    102 
    103 	/* used for buffer clearing */
    104 	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
    105 				 /* value to write to memory */
    106 				 uint32_t src_data,
    107 				 /* dst addr in bytes */
    108 				 uint64_t dst_offset,
    109 				 /* number of byte to fill */
    110 				 uint32_t byte_count);
    111 };
    112 
    113 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
    114 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
    115 
    116 struct amdgpu_sdma_instance *
    117 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
    118 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
    119 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
    120 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
    121 			      void *ras_ih_info);
    122 void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
    123 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
    124 		void *err_data,
    125 		struct amdgpu_iv_entry *entry);
    126 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
    127 				      struct amdgpu_irq_src *source,
    128 				      struct amdgpu_iv_entry *entry);
    129 #endif
    130