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      1 /*	$NetBSD: c_nec_pci.c,v 1.21 2021/09/19 10:34:07 andvar Exp $	*/
      2 
      3 /*-
      4  * Copyright (C) 2000 Shuichiro URATA.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 /*
     30  * for NEC PCI generation machines.
     31  */
     32 
     33 #include <sys/cdefs.h>
     34 __KERNEL_RCSID(0, "$NetBSD: c_nec_pci.c,v 1.21 2021/09/19 10:34:07 andvar Exp $");
     35 
     36 #define __INTR_PRIVATE
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/kcore.h>
     40 #include <sys/device.h>
     41 #include <sys/intr.h>
     42 
     43 #include <uvm/uvm_extern.h>
     44 
     45 #include <machine/autoconf.h>
     46 #include <sys/bus.h>
     47 #include <machine/pio.h>
     48 #include <machine/platform.h>
     49 #include <machine/wired_map.h>
     50 #include <mips/pte.h>
     51 
     52 #include <dev/clock_subr.h>
     53 #include <dev/ic/mc146818var.h>
     54 
     55 #include <dev/pci/pcivar.h>
     56 
     57 #include <arc/arc/arcbios.h>
     58 #include <arc/jazz/pica.h>
     59 #include <arc/jazz/rd94.h>
     60 #include <arc/jazz/jazziovar.h>
     61 #include <arc/jazz/mcclock_jazziovar.h>
     62 #include <arc/pci/necpbvar.h>
     63 
     64 #include "tga.h"
     65 #if NTGA > 0
     66 #include <dev/pci/tgavar.h>
     67 #endif
     68 
     69 #include "vga_pci.h"
     70 #if NVGA_PCI > 0
     71 #include <dev/pci/vga_pcivar.h>
     72 #endif
     73 
     74 #include "rasdisplay_jazzio.h"
     75 #if NRASDISPLAY_JAZZIO > 0
     76 #include <arc/jazz/rasdisplay_jazziovar.h>
     77 #endif
     78 
     79 #include "pckbc_jazzio.h"
     80 #if NPCKBC_JAZZIO > 0
     81 #include <dev/ic/pckbcvar.h>
     82 #include <arc/jazz/pckbc_jazzioreg.h>
     83 #endif
     84 
     85 #include "com.h"
     86 #if NCOM > 0
     87 #include <sys/termios.h>
     88 #include <dev/ic/comreg.h>
     89 #include <dev/ic/comvar.h>
     90 #endif
     91 
     92 const char *c_nec_pci_mainbusdevs[] = {
     93 	"jazzio",
     94 	"necpb",
     95 	NULL,
     96 };
     97 
     98 /*
     99  * chipset-dependent mcclock routines.
    100  */
    101 
    102 static u_int	mc_nec_pci_read(struct mc146818_softc *, u_int);
    103 static void	mc_nec_pci_write(struct mc146818_softc *, u_int, u_int);
    104 
    105 struct mcclock_jazzio_config mcclock_nec_pci_conf = {
    106 	0x80004000,		/* I/O base */
    107 	2,			/* I/O size */
    108 	mc_nec_pci_read,	/* read function */
    109 	mc_nec_pci_write	/* write function */
    110 };
    111 
    112 /*
    113  * This is a mask of bits to clear in the SR when we go to a
    114  * given interrupt priority level.
    115  */
    116 static const struct ipl_sr_map nec_pci_ipl_sr_map = {
    117     .sr_bits = {
    118 	[IPL_NONE] =		0,
    119 	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
    120 	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK,
    121 	[IPL_VM] =		MIPS_SOFT_INT_MASK
    122 				| MIPS_INT_MASK_0
    123 				| MIPS_INT_MASK_1
    124 				| MIPS_INT_MASK_2,
    125 	[IPL_SCHED] =		MIPS_INT_MASK,
    126 	[IPL_DDB] =		MIPS_INT_MASK,
    127 	[IPL_HIGH] =		MIPS_INT_MASK,
    128     },
    129 };
    130 
    131 static u_int
    132 mc_nec_pci_read(struct mc146818_softc *sc, u_int reg)
    133 {
    134 	u_int i, as;
    135 
    136 	as = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1) & 0x80;
    137 	bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1, as | reg);
    138 	i = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 0);
    139 	return i;
    140 }
    141 
    142 static void
    143 mc_nec_pci_write(struct mc146818_softc *sc, u_int reg, u_int datum)
    144 {
    145 	u_int as;
    146 
    147 	as = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1) & 0x80;
    148 	bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1, as | reg);
    149 	bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, datum);
    150 }
    151 
    152 /*
    153  * chipset-dependent jazzio bus configuration
    154  */
    155 
    156 void jazzio_nec_pci_set_iointr_mask(int);
    157 
    158 struct jazzio_config jazzio_nec_pci_conf = {
    159 	RD94_SYS_INTSTAT1,
    160 	jazzio_nec_pci_set_iointr_mask,
    161 	RD94_SYS_TL_BASE,
    162 	RD94_SYS_DMA0_REGS,
    163 };
    164 
    165 void
    166 jazzio_nec_pci_set_iointr_mask(int mask)
    167 {
    168 
    169 	/* XXX: I don't know why, but firmware does. */
    170 	if (in32(RD94_V_LOCAL_IO_BASE + 0x560) != 0)
    171 		out16(RD94_SYS_LB_IE2, mask);
    172 	else
    173 		out16(RD94_SYS_LB_IE1, mask);
    174 }
    175 
    176 /*
    177  * critial i/o space, interrupt, and other chipset related initialization.
    178  */
    179 void
    180 c_nec_pci_init(void)
    181 {
    182 
    183 	/*
    184 	 * Initialize interrupt priority
    185 	 */
    186 	ipl_sr_map = nec_pci_ipl_sr_map;
    187 
    188 	/*
    189 	 * Initialize I/O address offset
    190 	 */
    191 	arc_bus_space_init(&jazzio_bus, "jazzio",
    192 	    RD94_P_LOCAL_IO_BASE, RD94_V_LOCAL_IO_BASE,
    193 	    RD94_V_LOCAL_IO_BASE, RD94_S_LOCAL_IO_BASE);
    194 
    195 	arc_bus_space_init(&arc_bus_io, "rd94pciio",
    196 	    RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO);
    197 	arc_bus_space_init(&arc_bus_mem, "rd94pcimem",
    198 	    RD94_P_PCI_MEM, RD94_V_PCI_MEM, 0, RD94_S_PCI_MEM);
    199 
    200 	/*
    201 	 * Initialize wired TLB for I/O space which is used on early stage
    202 	 */
    203 	arc_init_wired_map();
    204 	arc_wired_enter_page(RD94_V_LOCAL_IO_BASE, RD94_P_LOCAL_IO_BASE,
    205 	    RD94_S_LOCAL_IO_BASE);
    206 	/*
    207 	 * allocate only 16M for PCM MEM space for now to save wired TLB entry;
    208 	 * Other regions will be allocalted by bus_space_large.c later.
    209 	 */
    210 	arc_wired_enter_page(RD94_V_PCI_IO, RD94_P_PCI_IO, RD94_S_PCI_IO);
    211 	arc_wired_enter_page(RD94_V_PCI_MEM, RD94_P_PCI_MEM, RD94_S_PCI_IO);
    212 
    213 	/*
    214 	 * By default, reserve 32MB in KSEG2 for PCI memory space.
    215 	 * Since kseg2iobufsize/NBPG*4 bytes are used for Sysmap,
    216 	 * this consumes 32KB physical memory.
    217 	 *
    218 	 * If a kernel with "options DIAGNOSTIC" panics with
    219 	 * the message "pmap_enter: kva too big", you have to
    220 	 * increase this value by a option like below:
    221 	 *     options KSEG2IOBUFSIZE=0x1b000000 # 432MB consumes 432KB
    222 	 * If you met this symptom, please report it to
    223 	 * port-arc-maintainer (at) NetBSD.org.
    224 	 *
    225 	 * kseg2iobufsize will be referred from pmap_bootstrap().
    226 	 */
    227 	kseg2iobufsize = 0x02000000; /* 32MB: consumes 32KB for PTEs */
    228 
    229 	/*
    230 	 * Disable all interrupts. New masks will be set up
    231 	 * during system configuration
    232 	 */
    233 	out16(RD94_SYS_LB_IE1, 0);
    234 	out16(RD94_SYS_LB_IE2, 0);
    235 	out32(RD94_SYS_EXT_IMASK, 0);
    236 
    237 	/*
    238 	 * common configuration between NEC EISA and PCI platforms
    239 	 */
    240 	c_nec_jazz_init();
    241 
    242 	/* chipset-dependent mcclock configuration */
    243 	mcclock_jazzio_conf = &mcclock_nec_pci_conf;
    244 
    245 	/* chipset-dependent jazzio bus configuration */
    246 	jazzio_conf = &jazzio_nec_pci_conf;
    247 }
    248 
    249 /*
    250  * console initialization
    251  */
    252 void
    253 c_nec_pci_cons_init(void)
    254 {
    255 
    256 	if (!com_console) {
    257 		if (strcmp(arc_displayc_id, "10110004") == 0) {
    258 			/* NEC RISCstation 2200 PCI TGA [NEC-RA94] */
    259 			/* NEC RISCstation 2250 PCI TGA [NEC-RD94] */
    260 			/* NEC Express 5800/230 R4400 PCI TGA [NEC-JC94] */
    261 			/* NEC Express 5800/230 R10000 PCI TGA [NEC-J95] */
    262 #if NTGA > 0
    263 			necpb_init(&necpb_main_context);
    264 			/* XXX device number is hardcoded */
    265 			if (tga_cnattach(&necpb_main_context.nc_iot,
    266 			    &necpb_main_context.nc_memt,
    267 			    &necpb_main_context.nc_pc, 0, 3, 0) == 0) {
    268 #if NPCKBC_JAZZIO > 0
    269 				pckbc_cnattach(&jazzio_bus, PICA_SYS_KBD,
    270 				    JAZZIO_KBCMDP, PCKBC_KBD_SLOT, 0);
    271 #endif
    272 				return;
    273 			}
    274 #endif
    275 		} else if (strcmp(arc_displayc_id, "53335631") == 0
    276 			/* NEC RISCstation 2200 PCI VGA S3 ViRGE [NEC-RA'94] */
    277 		    || strcmp(arc_displayc_id, "3D3D0001") == 0
    278 			/* NEC RISCstation 2200 PCI VGA 3Dlab GLINT 300SX */
    279 		    ) {
    280 			/* XXX - the followings are not really tested */
    281 #if NVGA_PCI > 0
    282 			necpb_init(&necpb_main_context);
    283 			/* XXX device number is hardcoded */
    284 			if (vga_pci_cnattach(&necpb_main_context.nc_iot,
    285 			    &necpb_main_context.nc_memt,
    286 			    &necpb_main_context.nc_pc, 0, 3, 0) == 0) {
    287 #if NPCKBC_JAZZIO > 0
    288 				pckbc_cnattach(&jazzio_bus, PICA_SYS_KBD,
    289 				    JAZZIO_KBCMDP, PCKBC_KBD_SLOT, 0);
    290 #endif
    291 				return;
    292 			}
    293 #endif
    294 		} else {
    295 			printf("nec_pci: unknown display controller [%s]\n",
    296 			    arc_displayc_id);
    297 		}
    298 	}
    299 
    300 #if NCOM > 0
    301 	if (com_console_address == 0)
    302 		com_console_address = RD94_SYS_COM1;
    303 	comcnattach(&jazzio_bus, com_console_address,
    304 	    com_console_speed, com_freq, COM_TYPE_NORMAL, com_console_mode);
    305 #endif
    306 }
    307