| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_ring.h | 101 * same cacheline, the Head Pointer must not be greater than the Tail
107 * into the same cacheline as ring->head.
109 #define cacheline(a) round_down(a, CACHELINE_BYTES) macro
110 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
112 #undef cacheline
134 * same cacheline, the Head Pointer must not be greater than the Tail
|
| intel_timeline.c | 56 hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
94 *cacheline = __ffs64(hwsp->free_bitmap);
95 hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
105 static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
112 /* As a cacheline becomes available, publish the HWSP on the freelist */
116 GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap));
117 hwsp->free_bitmap |= BIT_ULL(cacheline);
162 cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
167 GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
181 cl->vaddr = page_pack_bits(vaddr, cacheline);
225 unsigned int cacheline; local in function:intel_timeline_init
413 unsigned int cacheline; local in function:__intel_timeline_get_seqno
[all...] |
| selftest_timeline.c | 74 unsigned long cacheline; local in function:__mock_hwsp_timeline
81 cacheline = hwsp_cacheline(tl);
82 err = radix_tree_insert(&state->cachelines, cacheline, tl);
85 pr_err("HWSP cacheline %lu already used; duplicate allocation!\n",
86 cacheline);
660 * Across a seqno wrap, we need to keep the old cacheline alive for
|
| /src/sys/arch/sparc64/dev/ |
| pci_machdep.c | 256 int bus_frequency, lt, cl, cacheline; local in function:sparc64_pci_enumerate_bus1
274 cacheline = uimax(ecache_min_line_size, 64);
275 KASSERT((cacheline/64)*64 == cacheline &&
276 (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline &&
277 (cacheline/4)*4 == cacheline);
359 cl = cacheline;
|
| /src/sys/dev/acpi/ |
| qcomsmem.c | 65 uint32_t cacheline; member in struct:qcsmem_ptable_entry
91 size_t cacheline; member in struct:qcsmem_partition
256 part->cacheline = pte->cacheline;
418 roundup(sizeof(*entry), part->cacheline));
443 roundup(sizeof(*entry), part->cacheline));
|
| /src/sys/dev/pci/ |
| if_ti.c | 1250 uint32_t cacheline; local in function:ti_chipinit
1309 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG));
1319 switch (cacheline) {
1332 device_xname(sc->sc_dev), cacheline);
|
