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/src/sys/external/bsd/drm2/dist/drm/i915/display/ | |
intel_dpll_mgr.h | 190 u32 cfgcr1, cfgcr2; member in struct:intel_dpll_hw_state 194 /* CNL also uses cfgcr1 */ 201 * u32 cfgcr0, cfgcr1; |
intel_dpll_mgr.c | 963 i915_reg_t ctl, cfgcr1, cfgcr2; member in struct:skl_dpll_regs 976 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 982 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 988 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 1018 I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); 1020 POSTING_READ(regs[id].cfgcr1); 1080 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); 1372 u32 ctrl1, cfgcr1, cfgcr2 local in function:skl_ddi_hdmi_pll_dividers 2329 u32 cfgcr0, cfgcr1; local in function:cnl_ddi_hdmi_pll_dividers 2623 u32 cfgcr0, cfgcr1; local in function:icl_calc_dpll_state [all...] |