1 /* $NetBSD: cgfourteenreg.h,v 1.9 2025/05/14 06:32:16 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Harvard University and 18 * its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 /* 37 * Register/dac/clut/cursor definitions for cgfourteen frame buffer 38 */ 39 40 /* Locations of control registers in cg14 register set */ 41 #define CG14_OFFSET_CURS 0x1000 42 #define CG14_OFFSET_DAC 0x2000 43 #define CG14_OFFSET_XLUT 0x3000 44 #define CG14_OFFSET_CLUT1 0x4000 45 #define CG14_OFFSET_CLUT2 0x5000 46 #define CG14_OFFSET_CLUT3 0x6000 47 #define CG14_OFFSET_CLUTINCR 0xf000 48 49 /* cursor registers */ 50 #define CG14_CURSOR_PLANE0 0x1000 51 #define CG14_CURSOR_PLANE1 0x1080 52 #define CG14_CURSOR_CONTROL 0x1100 53 #define CG14_CRSR_ENABLE 0x04 54 #define CG14_CRSR_DBLBUFFER 0x02 55 #define CG14_CURSOR_X 0x1104 56 #define CG14_CURSOR_Y 0x1106 57 #define CG14_CURSOR_COLOR1 0x1108 58 #define CG14_CURSOR_COLOR2 0x110c 59 60 /* ranges in framebuffer space */ 61 #define CG14_FB_VRAM 0x00000000 62 #define CG14_FB_CBGR 0x01000000 63 #define CG14_FB_PX32 0x03000000 64 #define CG14_FB_PB32 0x03400000 65 #define CG14_FB_PG32 0x03800000 66 #define CG14_FB_PR32 0x03c00000 67 68 /* Main control register set */ 69 struct cg14ctl { 70 volatile uint8_t ctl_mctl; /* main control register */ 71 #define CG14_MCTL 0x00000000 72 #define CG14_MCTL_ENABLEINTR 0x80 /* interrupts */ 73 #define CG14_MCTL_ENABLEVID 0x40 /* enable video */ 74 #define CG14_MCTL_PIXMODE_MASK 0x30 75 #define CG14_MCTL_PIXMODE_8 0x00 /* data is 16 8-bit pixels */ 76 #define CG14_MCTL_PIXMODE_16 0x20 /* data is 8 16-bit pixels */ 77 #define CG14_MCTL_PIXMODE_32 0x30 /* data is 4 32-bit pixels */ 78 #define CG14_MCTL_PIXMODE_SHIFT 4 79 #define CG14_MCTL_TMR 0x0c 80 #define CG14_MCTL_ENABLETMR 0x02 81 #define CG14_MCTL_rev0RESET 0x01 82 #define CG14_MCTL_POWERCTL 0x01 83 84 volatile uint8_t ctl_ppr; /* packed pixel register */ 85 volatile uint8_t ctl_tmsr0; /* test status reg. 0 */ 86 volatile uint8_t ctl_tmsr1; /* test status reg. 1 */ 87 volatile uint8_t ctl_msr; /* master status register */ 88 volatile uint8_t ctl_fsr; /* fault status register */ 89 volatile uint8_t ctl_rsr; /* revision status register */ 90 #define CG14_RSR_REVMASK 0xf0 /* mask to get revision */ 91 #define CG14_RSR_IMPLMASK 0x0f /* mask to get impl. code */ 92 volatile uint8_t ctl_ccr; /* clock control register */ 93 #define CCR_SCL 0x01 94 #define CCR_SDA 0x02 95 #define CCR_SDA_DIR 0x04 96 #define CCR_ASXSEL 0x08 /* the ICS1562 has 4 data/address lines and a */ 97 #define CCR_DATA 0xf0 /* toggle input - I suspect this is it */ 98 volatile uint32_t ctl_tmr; /* test mode readback */ 99 volatile uint8_t ctl_mod; /* monitor data register */ 100 /* reads 0x4 on mine, other bits in the lower half can be written with 101 no obvious effect ( I suspect monitor ID ), upper half is hard zero 102 */ 103 volatile uint8_t ctl_acr; /* aux control register */ 104 #define ACR_BYTE_PIXEL 0x01 /* if unset pixels are 32bit */ 105 /* other bits are hard zero */ 106 uint8_t m_pad0[6]; /* Reserved */ 107 uint16_t m_hct; /* Horizontal Counter */ 108 uint16_t m_vct; /* Vertical Counter */ 109 uint16_t m_hbs; /* Horizontal Blank Start */ 110 uint16_t m_hbc; /* Horizontal Blank Clear */ 111 uint16_t m_hss; /* Horizontal Sync Set */ 112 uint16_t m_hsc; /* Horizontal Sync Set */ 113 uint16_t m_csc; /* Composite sync clear */ 114 uint16_t m_vbs; /* Vertical blank start */ 115 uint16_t m_vbc; /* Vertical Blank Clear */ 116 uint16_t m_vss; /* Verical Sync Set */ 117 uint16_t m_vsc; /* Verical Sync Clear */ 118 uint16_t m_xcs; /* XXX Gone in VSIMM 2 */ 119 uint16_t m_xcc; /* XXX Gone in VSIMM 2 */ 120 uint16_t m_fsa; /* Fault status address */ 121 uint16_t m_adr; /* Address register (autoincrements) */ 122 uint8_t m_pad2[0xce]; /* Reserved */ 123 124 /* PCG registers */ 125 uint8_t m_pcg[0x100]; /* Pixel Clock generator regs */ 126 /* XXX etc. */ 127 }; 128 129 /* Hardware cursor map */ 130 #define CG14_CURS_SIZE 32 131 struct cg14curs { 132 volatile uint32_t curs_plane0[CG14_CURS_SIZE]; /* plane 0 */ 133 volatile uint32_t curs_plane1[CG14_CURS_SIZE]; 134 volatile uint8_t curs_ctl; /* control register */ 135 #define CG14_CURS_ENABLE 0x4 136 #define CG14_CURS_DOUBLEBUFFER 0x2 /* use X-channel for curs */ 137 volatile uint8_t pad0[3]; 138 volatile uint16_t curs_x; /* x position */ 139 volatile uint16_t curs_y; /* y position */ 140 volatile uint32_t curs_color1; /* color register 1 */ 141 volatile uint32_t curs_color2; /* color register 2 */ 142 volatile uint32_t pad[444]; /* pad to 2KB boundary */ 143 volatile uint32_t curs_plane0incr[CG14_CURS_SIZE]; /* autoincr */ 144 volatile uint32_t curs_plane1incr[CG14_CURS_SIZE]; /* autoincr */ 145 }; 146 147 /* DAC */ 148 struct cg14dac { 149 volatile uint8_t dac_addr; /* address register */ 150 volatile uint8_t pad0[255]; 151 volatile uint8_t dac_gammalut; /* gamma LUT */ 152 volatile uint8_t pad1[255]; 153 volatile uint8_t dac_regsel; /* register select */ 154 volatile uint8_t pad2[255]; 155 volatile uint8_t dac_mode; /* mode register */ 156 }; 157 158 #define CG14_CLUT_SIZE 256 159 160 /* XLUT registers */ 161 struct cg14xlut { 162 volatile uint8_t xlut_lut[CG14_CLUT_SIZE]; /* the LUT */ 163 volatile uint8_t xlut_lutd[CG14_CLUT_SIZE]; /* ??? */ 164 volatile uint8_t pad0[0x600]; 165 volatile uint8_t xlut_lutinc[CG14_CLUT_SIZE]; /* autoincrLUT*/ 166 volatile uint8_t xlut_lutincd[CG14_CLUT_SIZE]; 167 }; 168 169 /* 170 * The XLUT and ctl_ppr bits are the same - in 8bit ppr is used, in 16bit and 171 * 24bit XLUT 172 * here we select two colours, either RGB or a component passed through a 173 * CLUT, and blend them together. The alpha value is taken from the right 174 * source's CLUT's upper byte, with 0x80 being 1.0 and 0x00 being 0.0 175 */ 176 177 #define CG14_LEFT_PASSTHROUGH 0x00 178 #define CG14_LEFT_CLUT1 0x40 179 #define CG14_LEFT_CLUT2 0x80 180 #define CG14_LEFT_CLUT3 0xc0 181 182 #define CG14_RIGHT_PASSTHROUGH 0x00 183 #define CG14_RIGHT_CLUT1 0x10 184 #define CG14_RIGHT_CLUT2 0x20 185 #define CG14_RIGHT_CLUT3 0x30 186 187 /* 0 is passthrough again */ 188 #define CG14_LEFT_B 0x04 189 #define CG14_LEFT_G 0x08 190 #define CG14_LEFT_R 0x0c 191 192 /* except here 0 selects the X channel */ 193 #define CG14_RIGHT_X 0x00 194 #define CG14_RIGHT_B 0x01 195 #define CG14_RIGHT_G 0x02 196 #define CG14_RIGHT_R 0x03 197 198 /* Color Look-Up Table (CLUT) */ 199 struct cg14clut { 200 volatile uint32_t clut_lut[CG14_CLUT_SIZE]; /* the LUT */ 201 volatile uint32_t clut_lutd[CG14_CLUT_SIZE]; /* ??? */ 202 volatile uint32_t clut_lutinc[CG14_CLUT_SIZE]; /* autoincr */ 203 volatile uint32_t clut_lutincd[CG14_CLUT_SIZE]; 204 }; 205
Indexes created Mon Sep 22 21:09:42 GMT 2025