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      1 /*	$NetBSD: ci_smumgr.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2017 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef _CI_SMUMANAGER_H_
     26 #define _CI_SMUMANAGER_H_
     27 
     28 #define SMU__NUM_SCLK_DPM_STATE  8
     29 #define SMU__NUM_MCLK_DPM_LEVELS 6
     30 #define SMU__NUM_LCLK_DPM_LEVELS 8
     31 #define SMU__NUM_PCIE_DPM_LEVELS 8
     32 
     33 #include "smu7_discrete.h"
     34 #include <pp_endian.h>
     35 #include "ppatomctrl.h"
     36 
     37 struct ci_pt_defaults {
     38 	u8 svi_load_line_en;
     39 	u8 svi_load_line_vddc;
     40 	u8 tdc_vddc_throttle_release_limit_perc;
     41 	u8 tdc_mawt;
     42 	u8 tdc_waterfall_ctl;
     43 	u8 dte_ambient_temp_base;
     44 	u32 display_cac;
     45 	u32 bapm_temp_gradient;
     46 	u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
     47 	u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
     48 };
     49 
     50 struct ci_mc_reg_entry {
     51 	uint32_t mclk_max;
     52 	uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
     53 };
     54 
     55 struct ci_mc_reg_table {
     56 	uint8_t   last;
     57 	uint8_t   num_entries;
     58 	uint16_t  validflag;
     59 	struct ci_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
     60 	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
     61 };
     62 
     63 struct ci_smumgr {
     64 	uint32_t                             soft_regs_start;
     65 	uint32_t                             dpm_table_start;
     66 	uint32_t                             mc_reg_table_start;
     67 	uint32_t                             fan_table_start;
     68 	uint32_t                             arb_table_start;
     69 	uint32_t                             ulv_setting_starts;
     70 	struct SMU7_Discrete_DpmTable       smc_state_table;
     71 	struct SMU7_Discrete_PmFuses  power_tune_table;
     72 	const struct ci_pt_defaults  *power_tune_defaults;
     73 	SMU7_Discrete_MCRegisters      mc_regs;
     74 	struct ci_mc_reg_table mc_reg_table;
     75 };
     76 
     77 #endif
     78 
     79