| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| rv1_clk_mgr_clk.c | 57 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base)
59 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rv1_dump_clk_registers
|
| amdgpu_rv1_clk_mgr.c | 42 void rv1_init_clocks(struct clk_mgr *clk_mgr)
44 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
47 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
50 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
52 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
82 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
93 static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc *dc, struct dc_clocks *new_clocks)
96 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks)
134 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rv1_update_clocks
236 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rv1_enable_pme_wa
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/ |
| amdgpu_clk_mgr.c | 71 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
79 clk_mgr->psr_allow_active_cache = edp_link->psr_allow_active;
85 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
90 dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false);
97 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
101 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); local in function:dc_clk_mgr_create
103 if (clk_mgr == NULL)
179 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dc_destroy_clk_mgr
[all...] |
| Makefile | 23 # Makefile for the 'clk_mgr' sub-component of DAL.
24 # It provides the control and status of HW CLK_MGR pins.
26 CLK_MGR = clk_mgr.o
28 AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
38 AMD_DAL_CLK_MGR_DCE100 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce100/,$(CLK_MGR_DCE100))
47 AMD_DAL_CLK_MGR_DCE110 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce110/,$(CLK_MGR_DCE110))
55 AMD_DAL_CLK_MGR_DCE112 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce112/,$(CLK_MGR_DCE112))
63 AMD_DAL_CLK_MGR_DCE120 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce120/,$(CLK_MGR_DCE120)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 52 (clk_mgr->regs->reg)
56 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
134 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
136 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dce_get_dp_ref_freq_khz
155 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
157 return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
160 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
200 struct clk_mgr *clk_mgr_base,
235 struct clk_mgr *clk_mgr_base
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 48 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
51 (clk_mgr->regs->reg)
108 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
114 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
126 clk_mgr->dccg->funcs->update_dpp_dto(
127 clk_mgr->dccg, dpp_inst, dppclk_khz)
155 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dcn2_update_clocks
344 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dcn2_enable_pme_wa
358 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:dcn2_read_clocks_from_hw_dentist
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 101 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
105 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_update_clocks
129 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
137 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
145 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
156 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
165 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
166 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
174 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz)
234 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_dump_clk_registers_internal
399 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_enable_pme_wa
474 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); local in function:rn_notify_wm_ranges
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr.h | 1 /* $NetBSD: clk_mgr.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
170 void (*update_clocks)(struct clk_mgr *clk_mgr,
174 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
176 void (*init_clocks)(struct clk_mgr *clk_mgr);
178 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
179 void (*get_clock)(struct clk_mgr *clk_mgr
189 struct clk_mgr { struct
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 57 #include "clk_mgr.h"
953 struct clk_mgr *clk_mgr; local in function:dce110_enable_audio_stream
960 clk_mgr = dc->clk_mgr;
974 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
976 clk_mgr->funcs->enable_pme_wa(clk_mgr);
989 struct clk_mgr *clk_mgr; local in function:dce110_disable_audio_stream
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 378 struct clk_mgr *clk_mgr; member in struct:dc_state
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 503 struct clk_mgr *clk_mgr; member in struct:dc
|
