| /src/sys/arch/hpcmips/dev/ |
| plumpower.c | 129 plumreg_t pwrreg, clkreg; local
132 clkreg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG);
157 clkreg |= PLUM_POWER_CLKCONT_IO5CLK;
172 clkreg |= PLUM_POWER_CLKCONT_USBCLK1;
177 clkreg &= ~PLUM_POWER_CLKCONT_USBCLK2;
180 clkreg |= PLUM_POWER_CLKCONT_SMCLK;
183 clkreg |= PLUM_POWER_CLKCONT_PCCCLK1;
186 clkreg |= PLUM_POWER_CLKCONT_PCCCLK2;
191 plum_conf_write(regt, regh, PLUM_POWER_CLKCONT_REG, clkreg);
205 plumreg_t pwrreg, clkreg; local
[all...] |
| /src/sys/arch/hp300/hp300/ |
| clockreg.h | 45 struct clkreg { struct
|
| /src/sys/arch/mips/ingenic/ |
| apbus.c | 71 uint32_t clkreg; /* CGU register */ member in struct:apbus_dev
253 aa.aa_clockreg = adv->clkreg;
291 ingenic_cdr_set(uint32_t clkreg, uint32_t val)
295 writereg(clkreg, val | CDR_CE);
297 if ((readreg(clkreg) & CDR_BUSY) == 0)
|
| /src/sys/arch/arm/samsung/ |
| exynos_soc.c | 711 uint32_t phypwr, rstcon, clkreg; local
714 clkreg = FSEL_CLKSEL_24M;
716 USB_PHYCLK, clkreg);
|
| /src/sys/dev/pci/ |
| if_bnx.c | 734 uint32_t clkreg; local
738 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS);
740 clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
741 switch (clkreg) {
|
