1 /* $NetBSD: com.c,v 1.390 2025/11/25 13:23:28 brad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 * 67 * Lock order (when sc_softirq is false): 68 * ttylock (IPL_VM) 69 * -> sc->sc_lock (IPL_HIGH) 70 * -> timecounter_lock (IPL_HIGH) 71 * 72 * When sc_softirq is true, the ttylock is dropped or avoided and 73 * sc->sc_lock is run at IPL_SOFTSERIAL 74 * 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.390 2025/11/25 13:23:28 brad Exp $"); 79 80 #include "opt_com.h" 81 #include "opt_ddb.h" 82 #include "opt_kgdb.h" 83 #include "opt_lockdebug.h" 84 #include "opt_multiprocessor.h" 85 #include "opt_ntp.h" 86 87 /* The COM16650 option was renamed to COM_16650. */ 88 #ifdef COM16650 89 #error Obsolete COM16650 option; use COM_16650 instead. 90 #endif 91 92 /* 93 * Override cnmagic(9) macro before including <sys/systm.h>. 94 * We need to know if cn_check_magic triggered debugger, so set a flag. 95 * Callers of cn_check_magic must declare int cn_trapped = 0; 96 * XXX: this is *ugly*! 97 */ 98 #define cn_trap() \ 99 do { \ 100 console_debugger(); \ 101 cn_trapped = 1; \ 102 (void)cn_trapped; \ 103 } while (/* CONSTCOND */ 0) 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/ioctl.h> 108 #include <sys/select.h> 109 #include <sys/poll.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/uio.h> 115 #include <sys/kernel.h> 116 #include <sys/syslog.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 #include <sys/timepps.h> 120 #include <sys/vnode.h> 121 #include <sys/kauth.h> 122 #include <sys/intr.h> 123 #include <sys/workqueue.h> 124 #ifdef RND_COM 125 #include <sys/rndsource.h> 126 #endif 127 128 #include <sys/bus.h> 129 130 #include <ddb/db_active.h> 131 132 #include <dev/ic/comreg.h> 133 #include <dev/ic/comvar.h> 134 #include <dev/ic/ns16550reg.h> 135 #include <dev/ic/st16650reg.h> 136 #include <dev/ic/hayespreg.h> 137 #define com_lcr com_cfcr 138 #include <dev/cons.h> 139 140 #include "ioconf.h" 141 142 #define CSR_READ_1(r, o) \ 143 (r)->cr_read((r), (r)->cr_map[o]) 144 #define CSR_WRITE_1(r, o, v) \ 145 (r)->cr_write((r), (r)->cr_map[o], (v)) 146 #define CSR_WRITE_MULTI(r, o, p, n) \ 147 (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n)) 148 149 /* 150 * XXX COM_TYPE_AU1x00 specific 151 */ 152 #define CSR_WRITE_2(r, o, v) \ 153 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 154 #define CSR_READ_2(r, o) \ 155 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 156 157 /* Out of band error */ 158 #define CSR_HAS_ERROR(r) \ 159 (r)->cr_has_errored 160 161 static void com_enable_debugport(struct com_softc *); 162 163 void com_config(struct com_softc *); 164 void com_shutdown(struct com_softc *); 165 int comspeed(long, long, int); 166 static u_char cflag2lcr(tcflag_t); 167 int comparam(struct tty *, struct termios *); 168 void comstart(struct tty *); 169 void comstartsoft(struct tty *); 170 int comhwiflow(struct tty *, int); 171 int comhwiflowsoft(struct tty *, int); 172 173 void com_loadchannelregs(struct com_softc *); 174 void com_hwiflow(struct com_softc *); 175 void com_break(struct com_softc *, int); 176 void com_modem(struct com_softc *, int); 177 void tiocm_to_com(struct com_softc *, u_long, int); 178 int com_to_tiocm(struct com_softc *); 179 void com_iflush(struct com_softc *); 180 181 int com_common_getc(dev_t, struct com_regs *); 182 static void com_common_putc(dev_t, struct com_regs *, int, int); 183 184 int cominit(struct com_regs *, int, int, int, tcflag_t); 185 186 static int comcnreattach(void); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 void comsoft(void *); 193 static void comsoftwq(struct work *, void *); 194 static inline void com_rxsoft(struct com_softc *, struct tty *); 195 static inline void com_txsoft(struct com_softc *, struct tty *); 196 static inline void com_stsoft(struct com_softc *, struct tty *); 197 static inline void com_schedrx(struct com_softc *); 198 void comdiag(void *); 199 200 dev_type_open(comopen); 201 dev_type_close(comclose); 202 dev_type_read(comread); 203 dev_type_write(comwrite); 204 dev_type_ioctl(comioctl); 205 dev_type_stop(comstop); 206 dev_type_tty(comtty); 207 dev_type_poll(compoll); 208 209 static struct comcons_info comcons_info; 210 211 /* 212 * Following are all routines needed for COM to act as console 213 */ 214 static struct consdev comcons = { 215 .cn_getc = comcngetc, 216 .cn_putc = comcnputc, 217 .cn_pollc = comcnpollc, 218 .cn_dev = NODEV, 219 .cn_pri = CN_NORMAL 220 }; 221 222 223 const struct cdevsw com_cdevsw = { 224 .d_open = comopen, 225 .d_close = comclose, 226 .d_read = comread, 227 .d_write = comwrite, 228 .d_ioctl = comioctl, 229 .d_stop = comstop, 230 .d_tty = comtty, 231 .d_poll = compoll, 232 .d_mmap = nommap, 233 .d_kqfilter = ttykqfilter, 234 .d_discard = nodiscard, 235 .d_flag = D_TTY 236 }; 237 238 /* 239 * Make this an option variable one can patch. 240 * But be warned: this must be a power of 2! 241 */ 242 u_int com_rbuf_size = COM_RING_SIZE; 243 244 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 245 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 246 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 247 248 static int comconsattached; 249 static struct cnm_state com_cnm_state; 250 251 #ifdef KGDB 252 #include <sys/kgdb.h> 253 254 static struct com_regs comkgdbregs; 255 static int com_kgdb_attached; 256 257 int com_kgdb_getc(void *); 258 void com_kgdb_putc(void *, int); 259 #endif /* KGDB */ 260 261 /* initializer for typical 16550-ish hardware */ 262 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 263 [COM_REG_RXDATA] = com_data, 264 [COM_REG_TXDATA] = com_data, 265 [COM_REG_DLBL] = com_dlbl, 266 [COM_REG_DLBH] = com_dlbh, 267 [COM_REG_IER] = com_ier, 268 [COM_REG_IIR] = com_iir, 269 [COM_REG_FIFO] = com_fifo, 270 [COM_REG_TCR] = com_fifo, 271 [COM_REG_EFR] = com_efr, 272 [COM_REG_TLR] = com_efr, 273 [COM_REG_LCR] = com_lcr, 274 [COM_REG_MCR] = com_mcr, 275 [COM_REG_LSR] = com_lsr, 276 [COM_REG_MSR] = com_msr, 277 [COM_REG_USR] = com_usr, 278 [COM_REG_TFL] = com_tfl, 279 [COM_REG_RFL] = com_rfl, 280 [COM_REG_HALT] = com_halt, 281 [COM_REG_MDR1] = com_mdr1, 282 }; 283 284 #define COMDIALOUT_MASK TTDIALOUT_MASK 285 286 #define COMUNIT(x) TTUNIT(x) 287 #define COMDIALOUT(x) TTDIALOUT(x) 288 289 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 290 device_is_active((sc)->sc_dev)) 291 292 #define BR BUS_SPACE_BARRIER_READ 293 #define BW BUS_SPACE_BARRIER_WRITE 294 #define COM_BARRIER(r, f) \ 295 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 296 297 /* Wrap the mutex calls to pick which varient we need to be using */ 298 299 static void 300 com_mutex_enter(struct com_softc *sc) 301 { 302 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 303 mutex_enter(&sc->sc_lock); 304 else 305 mutex_spin_enter(&sc->sc_lock); 306 } 307 308 static void 309 com_mutex_exit(struct com_softc *sc) 310 { 311 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 312 mutex_exit(&sc->sc_lock); 313 else 314 mutex_spin_exit(&sc->sc_lock); 315 } 316 317 /* 318 * com_read_1 -- 319 * Default register read callback using single byte accesses. 320 */ 321 static uint8_t 322 com_read_1(struct com_regs *regs, u_int reg) 323 { 324 return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg); 325 } 326 327 /* 328 * com_write_1 -- 329 * Default register write callback using single byte accesses. 330 */ 331 static void 332 com_write_1(struct com_regs *regs, u_int reg, uint8_t val) 333 { 334 bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val); 335 } 336 337 /* 338 * com_write_multi_1 -- 339 * Default register multi write callback using single byte accesses. 340 */ 341 static void 342 com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap, 343 bus_size_t count) 344 { 345 bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count); 346 } 347 348 /* 349 * com_read_4 -- 350 * Default register read callback using dword accesses. 351 */ 352 static uint8_t 353 com_read_4(struct com_regs *regs, u_int reg) 354 { 355 return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff; 356 } 357 358 /* 359 * com_write_4 -- 360 * Default register write callback using dword accesses. 361 */ 362 static void 363 com_write_4(struct com_regs *regs, u_int reg, uint8_t val) 364 { 365 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val); 366 } 367 368 /* 369 * com_write_multi_4 -- 370 * Default register multi write callback using dword accesses. 371 */ 372 static void 373 com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap, 374 bus_size_t count) 375 { 376 while (count-- > 0) { 377 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++); 378 } 379 } 380 381 /* 382 * com_init_regs -- 383 * Driver front-ends use this to initialize our register map 384 * in the standard fashion. They may then tailor the map to 385 * their own particular requirements. 386 */ 387 void 388 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 389 bus_addr_t addr) 390 { 391 392 memset(regs, 0, sizeof(*regs)); 393 regs->cr_has_errored = false; 394 regs->cr_iot = st; 395 regs->cr_ioh = sh; 396 regs->cr_iobase = addr; 397 regs->cr_nports = COM_NPORTS; 398 regs->cr_read = com_read_1; 399 regs->cr_write = com_write_1; 400 regs->cr_write_multi = com_write_multi_1; 401 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 402 } 403 404 /* 405 * com_init_regs_stride -- 406 * Convenience function for front-ends that have a stride between 407 * registers. 408 */ 409 void 410 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 411 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 412 { 413 414 com_init_regs(regs, st, sh, addr); 415 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 416 regs->cr_map[i] <<= regshift; 417 } 418 regs->cr_nports <<= regshift; 419 } 420 421 /* 422 * com_init_regs_stride_width -- 423 * Convenience function for front-ends that have a stride between 424 * registers and specific I/O width requirements. 425 */ 426 void 427 com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st, 428 bus_space_handle_t sh, bus_addr_t addr, 429 u_int regshift, u_int width) 430 { 431 432 com_init_regs(regs, st, sh, addr); 433 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 434 regs->cr_map[i] <<= regshift; 435 } 436 regs->cr_nports <<= regshift; 437 438 switch (width) { 439 case 1: 440 /* Already set by com_init_regs */ 441 break; 442 case 4: 443 regs->cr_read = com_read_4; 444 regs->cr_write = com_write_4; 445 regs->cr_write_multi = com_write_multi_4; 446 break; 447 default: 448 panic("com: unsupported I/O width %d", width); 449 } 450 } 451 452 /*ARGSUSED*/ 453 int 454 comspeed(long speed, long frequency, int type) 455 { 456 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 457 458 int x, err; 459 int divisor = 16; 460 461 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 462 divisor = 13; 463 } 464 465 if (speed == 0) 466 return (0); 467 if (speed < 0) 468 return (-1); 469 x = divrnd(frequency / divisor, speed); 470 if (x <= 0) 471 return (-1); 472 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 473 if (err < 0) 474 err = -err; 475 if (err > COM_TOLERANCE) 476 return (-1); 477 if (x > 65535) /* There are only 16 bits for the divider. */ 478 return (-1); 479 return (x); 480 481 #undef divrnd 482 } 483 484 #ifdef COM_DEBUG 485 int com_debug = 0; 486 487 void comstatus(struct com_softc *, const char *); 488 void 489 comstatus(struct com_softc *sc, const char *str) 490 { 491 struct tty *tp = sc->sc_tty; 492 493 aprint_normal_dev(sc->sc_dev, 494 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 495 str, 496 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 497 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 498 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 499 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 500 sc->sc_tx_stopped ? '+' : '-'); 501 502 aprint_normal_dev(sc->sc_dev, 503 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 504 str, 505 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 506 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 507 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 508 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 509 sc->sc_rx_flags); 510 } 511 #endif 512 513 int 514 com_probe_subr(struct com_regs *regs) 515 { 516 517 /* force access to id reg */ 518 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 519 CSR_WRITE_1(regs, COM_REG_IIR, 0); 520 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 521 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 522 return (0); 523 524 return (1); 525 } 526 527 int 528 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 529 { 530 struct com_regs regs; 531 532 com_init_regs(®s, iot, ioh, 0/*XXX*/); 533 534 return com_probe_subr(®s); 535 } 536 537 /* 538 * No locking in this routine; it is only called during attach, 539 * or with the port already locked. 540 */ 541 static void 542 com_enable_debugport(struct com_softc *sc) 543 { 544 545 /* Turn on line break interrupt, set carrier. */ 546 sc->sc_ier = IER_ERLS; 547 if (sc->sc_type == COM_TYPE_PXA2x0) 548 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 549 if (sc->sc_type == COM_TYPE_INGENIC || 550 sc->sc_type == COM_TYPE_TEGRA) 551 sc->sc_ier |= IER_ERXTOUT; 552 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 553 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 554 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 555 } 556 557 static void 558 com_intr_poll(void *arg) 559 { 560 struct com_softc * const sc = arg; 561 562 comintr(sc); 563 564 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 565 } 566 567 void 568 com_attach_subr(struct com_softc *sc) 569 { 570 struct com_regs *regsp = &sc->sc_regs; 571 struct tty *tp; 572 uint32_t cpr; 573 uint8_t lcr; 574 const char *fifo_msg = NULL; 575 prop_dictionary_t dict; 576 bool is_console = true; 577 bool force_console = false; 578 bool skip_attach_delay = false; 579 int error; 580 aprint_naive("\n"); 581 582 dict = device_properties(sc->sc_dev); 583 prop_dictionary_get_bool(dict, "is_console", &is_console); 584 prop_dictionary_get_bool(dict, "force_console", &force_console); 585 prop_dictionary_get_bool(dict, "skip_attach_delay", &skip_attach_delay); 586 callout_init(&sc->sc_diag_callout, 0); 587 588 /* The softirq case must run everything here at IPL_SOFTfoo and 589 * not have any spin locks involved 590 */ 591 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 592 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTSERIAL); 593 } else { 594 callout_init(&sc->sc_poll_callout, 0); 595 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 596 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 597 } 598 599 #if defined(COM_16650) 600 sc->sc_type = COM_TYPE_16650; 601 #elif defined(COM_16750) 602 sc->sc_type = COM_TYPE_16750; 603 #elif defined(COM_HAYESP) 604 sc->sc_type = COM_TYPE_HAYESP; 605 #elif defined(COM_PXA2X0) 606 sc->sc_type = COM_TYPE_PXA2x0; 607 #endif 608 609 /* Disable interrupts before configuring the device. */ 610 if (sc->sc_type == COM_TYPE_PXA2x0) 611 sc->sc_ier = IER_EUART; 612 else 613 sc->sc_ier = 0; 614 615 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 616 617 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 618 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 619 comconsattached = 1; 620 621 if (force_console) 622 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 623 624 if (cn_tab == NULL && comcnreattach() != 0) { 625 printf("can't re-init serial console @%lx\n", 626 (u_long)comcons_info.regs.cr_iobase); 627 } 628 629 switch (sc->sc_type) { 630 case COM_TYPE_16750: 631 case COM_TYPE_DW_APB: 632 /* Use in comintr(). */ 633 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 634 break; 635 } 636 637 /* No need for a delay on virtual machines. */ 638 if (!skip_attach_delay) 639 delay(10000); /* wait for output to finish */ 640 641 /* Make sure the console is always "hardwired". */ 642 if (is_console) { 643 SET(sc->sc_hwflags, COM_HW_CONSOLE); 644 } 645 646 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 647 } 648 649 /* Probe for FIFO */ 650 switch (sc->sc_type) { 651 case COM_TYPE_HAYESP: 652 goto fifodone; 653 654 case COM_TYPE_AU1x00: 655 sc->sc_fifolen = 16; 656 fifo_msg = "Au1X00 UART"; 657 SET(sc->sc_hwflags, COM_HW_FIFO); 658 goto fifodelay; 659 660 case COM_TYPE_16550_NOERS: 661 sc->sc_fifolen = 16; 662 fifo_msg = "ns16650, no ERS"; 663 SET(sc->sc_hwflags, COM_HW_FIFO); 664 goto fifodelay; 665 666 case COM_TYPE_OMAP: 667 sc->sc_fifolen = 64; 668 fifo_msg = "OMAP UART"; 669 SET(sc->sc_hwflags, COM_HW_FIFO); 670 goto fifodelay; 671 672 case COM_TYPE_INGENIC: 673 sc->sc_fifolen = 16; 674 fifo_msg = "Ingenic UART"; 675 SET(sc->sc_hwflags, COM_HW_FIFO); 676 SET(sc->sc_hwflags, COM_HW_NOIEN); 677 goto fifodelay; 678 679 case COM_TYPE_TEGRA: 680 sc->sc_fifolen = 8; 681 fifo_msg = "Tegra UART"; 682 SET(sc->sc_hwflags, COM_HW_FIFO); 683 CSR_WRITE_1(regsp, COM_REG_FIFO, 684 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 685 goto fifodelay; 686 687 case COM_TYPE_BCMAUXUART: 688 sc->sc_fifolen = 1; 689 fifo_msg = "BCM AUX UART"; 690 SET(sc->sc_hwflags, COM_HW_FIFO); 691 CSR_WRITE_1(regsp, COM_REG_FIFO, 692 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 693 goto fifodelay; 694 695 case COM_TYPE_DW_APB: 696 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 697 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 698 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 699 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 700 } 701 if (sc->sc_fifolen == 0) { 702 sc->sc_fifolen = 1; 703 fifo_msg = "DesignWare APB UART, no fifo"; 704 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 705 } else { 706 fifo_msg = "DesignWare APB UART"; 707 SET(sc->sc_hwflags, COM_HW_FIFO); 708 CSR_WRITE_1(regsp, COM_REG_FIFO, 709 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 710 } 711 goto fifodelay; 712 713 case COM_TYPE_SC16IS7XX: 714 sc->sc_fifolen = 64; 715 fifo_msg = "NXP UART"; 716 SET(sc->sc_hwflags, COM_HW_FLOW); 717 SET(sc->sc_hwflags, COM_HW_FIFO); 718 SET(sc->sc_hwflags, COM_HW_MCRPRESCALE); 719 CSR_WRITE_1(regsp, COM_REG_FIFO, 720 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 721 goto fifodelay; 722 } 723 724 sc->sc_fifolen = 1; 725 /* look for a NS 16550AF UART with FIFOs */ 726 if (sc->sc_type == COM_TYPE_INGENIC) { 727 CSR_WRITE_1(regsp, COM_REG_FIFO, 728 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 729 FIFO_TRIGGER_14 | FIFO_UART_ON); 730 } else 731 CSR_WRITE_1(regsp, COM_REG_FIFO, 732 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 733 delay(100); 734 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 735 == IIR_FIFO_MASK) 736 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 737 == FIFO_TRIGGER_14) { 738 SET(sc->sc_hwflags, COM_HW_FIFO); 739 740 fifo_msg = "ns16550a"; 741 sc->sc_fifolen = 16; 742 743 /* 744 * IIR changes into the EFR if LCR is set to LCR_EERS 745 * on 16650s. We also know IIR != 0 at this point. 746 * Write 0 into the EFR, and read it. If the result 747 * is 0, we have a 16650. 748 * 749 * Older 16650s were broken; the test to detect them 750 * is taken from the Linux driver. Apparently 751 * setting DLAB enable gives access to the EFR on 752 * these chips. 753 */ 754 if (sc->sc_type == COM_TYPE_16650) { 755 lcr = CSR_READ_1(regsp, COM_REG_LCR); 756 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 757 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 758 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 759 CSR_WRITE_1(regsp, COM_REG_LCR, 760 lcr | LCR_DLAB); 761 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 762 CLR(sc->sc_hwflags, COM_HW_FIFO); 763 sc->sc_fifolen = 0; 764 } else { 765 SET(sc->sc_hwflags, COM_HW_FLOW); 766 sc->sc_fifolen = 32; 767 } 768 } else 769 sc->sc_fifolen = 16; 770 771 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 772 if (sc->sc_fifolen == 0) 773 fifo_msg = "st16650, broken fifo"; 774 else if (sc->sc_fifolen == 32) 775 fifo_msg = "st16650a"; 776 else 777 fifo_msg = "ns16550a"; 778 } 779 780 /* 781 * TL16C750 can enable 64byte FIFO, only when DLAB 782 * is 1. However, some 16750 may always enable. For 783 * example, restrictions according to DLAB in a data 784 * sheet for SC16C750 were not described. 785 * Please enable 'options COM_16650', supposing you 786 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 787 * should become effective. 788 */ 789 if (sc->sc_type == COM_TYPE_16750) { 790 uint8_t iir1, iir2; 791 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 792 793 lcr = CSR_READ_1(regsp, COM_REG_LCR); 794 CSR_WRITE_1(regsp, COM_REG_LCR, 795 lcr & ~LCR_DLAB); 796 CSR_WRITE_1(regsp, COM_REG_FIFO, 797 fcr | FIFO_64B_ENABLE); 798 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 799 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 800 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 801 CSR_WRITE_1(regsp, COM_REG_FIFO, 802 fcr | FIFO_64B_ENABLE); 803 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 804 805 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 806 807 if (!ISSET(iir1, IIR_64B_FIFO) && 808 ISSET(iir2, IIR_64B_FIFO)) { 809 /* It is TL16C750. */ 810 sc->sc_fifolen = 64; 811 SET(sc->sc_hwflags, COM_HW_AFE); 812 } else 813 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 814 815 if (sc->sc_fifolen == 64) 816 fifo_msg = "tl16c750"; 817 else 818 fifo_msg = "ns16750"; 819 } 820 } else 821 fifo_msg = "ns16550, broken fifo"; 822 else 823 fifo_msg = "ns8250 or ns16450, no fifo"; 824 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 825 826 fifodelay: 827 /* 828 * Some chips will clear down both Tx and Rx FIFOs when zero is 829 * written to com_fifo. If this chip is the console, writing zero 830 * results in some of the chip/FIFO description being lost, so delay 831 * printing it until now. 832 */ 833 delay(10); 834 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 835 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 836 } else { 837 aprint_normal(": %s\n", fifo_msg); 838 } 839 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 840 sc->sc_fifolen = 1; 841 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 842 } 843 844 fifodone: 845 846 tp = tty_alloc(); 847 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 848 tp->t_oproc = comstartsoft; 849 tp->t_hwiflow = comhwiflowsoft; 850 } else { 851 tp->t_oproc = comstart; 852 tp->t_hwiflow = comhwiflow; 853 } 854 tp->t_param = comparam; 855 tp->t_softc = sc; 856 857 sc->sc_tty = tp; 858 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 859 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 860 sc->sc_rbavail = com_rbuf_size; 861 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 862 863 tty_attach(tp); 864 865 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 866 SET(sc->sc_mcr, MCR_IENABLE); 867 868 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 869 int maj; 870 871 /* locate the major number */ 872 maj = cdevsw_lookup_major(&com_cdevsw); 873 874 tp->t_dev = cn_tab->cn_dev = makedev(maj, 875 device_unit(sc->sc_dev)); 876 877 aprint_normal_dev(sc->sc_dev, "console\n"); 878 } 879 880 #ifdef KGDB 881 /* 882 * Allow kgdb to "take over" this port. If this is 883 * not the console and is the kgdb device, it has 884 * exclusive use. If it's the console _and_ the 885 * kgdb device, it doesn't. 886 */ 887 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 888 regsp->cr_iobase == comkgdbregs.cr_iobase) { 889 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 890 com_kgdb_attached = 1; 891 892 SET(sc->sc_hwflags, COM_HW_KGDB); 893 } 894 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 895 } 896 #endif 897 898 /* Use a workqueue in the softirq case and not a softint, which 899 * tripped panics 900 */ 901 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 902 error = workqueue_create(&sc->sc_wq, device_xname(sc->sc_dev), 903 comsoftwq, sc, PRI_SOFTSERIAL, IPL_SOFTSERIAL, WQ_MPSAFE); 904 if (error) { 905 aprint_error_dev(sc->sc_dev, 906 "Could not create workqueue: %d\n", 907 error); 908 } 909 sc->sc_si = NULL; 910 } else { 911 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 912 sc->sc_wq = NULL; 913 } 914 915 #ifdef RND_COM 916 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 917 RND_TYPE_TTY, RND_FLAG_DEFAULT); 918 #endif 919 920 /* if there are no enable/disable functions, assume the device 921 is always enabled */ 922 if (!sc->enable) 923 sc->enabled = 1; 924 925 com_config(sc); 926 927 SET(sc->sc_hwflags, COM_HW_DEV_OK); 928 929 /* A choice was made here... in the softirq case, have the code that 930 * this is glued to start the interrupt poller. The SC16IS7XX needs this 931 * because there are two ports on one chip with a single interrupt and you 932 * wouldn't want two kernel threads running to do that artifical interrupt. 933 */ 934 if (sc->sc_poll_ticks != 0) { 935 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) { 936 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 937 } 938 } 939 } 940 941 void 942 com_config(struct com_softc *sc) 943 { 944 struct com_regs *regsp = &sc->sc_regs; 945 946 /* Disable interrupts before configuring the device. */ 947 if (sc->sc_type == COM_TYPE_PXA2x0) 948 sc->sc_ier = IER_EUART; 949 else 950 sc->sc_ier = 0; 951 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 952 (void) CSR_READ_1(regsp, COM_REG_IIR); 953 954 /* Look for a Hayes ESP board. */ 955 if (sc->sc_type == COM_TYPE_HAYESP) { 956 957 /* Set 16550 compatibility mode */ 958 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 959 HAYESP_SETMODE); 960 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 961 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 962 HAYESP_MODE_SCALE); 963 964 /* Set RTS/CTS flow control */ 965 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 966 HAYESP_SETFLOWTYPE); 967 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 968 HAYESP_FLOW_RTS); 969 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 970 HAYESP_FLOW_CTS); 971 972 /* Set flow control levels */ 973 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 974 HAYESP_SETRXFLOW); 975 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 976 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 977 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 978 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 979 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 980 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 981 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 982 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 983 } 984 985 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 986 com_enable_debugport(sc); 987 } 988 989 int 990 com_detach(device_t self, int flags) 991 { 992 struct com_softc *sc = device_private(self); 993 int maj, mn; 994 995 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 996 return EBUSY; 997 998 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 999 (flags & DETACH_SHUTDOWN) != 0) 1000 return EBUSY; 1001 1002 if (sc->disable != NULL && sc->enabled != 0) { 1003 (*sc->disable)(sc); 1004 sc->enabled = 0; 1005 } 1006 1007 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1008 comconsattached = 0; 1009 cn_tab = NULL; 1010 } 1011 1012 /* locate the major number */ 1013 maj = cdevsw_lookup_major(&com_cdevsw); 1014 1015 /* Nuke the vnodes for any open instances. */ 1016 mn = device_unit(self); 1017 vdevgone(maj, mn, mn, VCHR); 1018 1019 mn |= COMDIALOUT_MASK; 1020 vdevgone(maj, mn, mn, VCHR); 1021 1022 if (sc->sc_rbuf == NULL) { 1023 /* 1024 * Ring buffer allocation failed in the com_attach_subr, 1025 * only the tty is allocated, and nothing else. 1026 */ 1027 tty_free(sc->sc_tty); 1028 return 0; 1029 } 1030 1031 /* Free the receive buffer. */ 1032 free(sc->sc_rbuf, M_DEVBUF); 1033 1034 /* Detach and free the tty. */ 1035 tty_detach(sc->sc_tty); 1036 tty_free(sc->sc_tty); 1037 1038 /* Unhook the soft interrupt handler. */ 1039 if (sc->sc_si != NULL) 1040 softint_disestablish(sc->sc_si); 1041 1042 if (sc->sc_wq != NULL) 1043 workqueue_destroy(sc->sc_wq); 1044 1045 #ifdef RND_COM 1046 /* Unhook the entropy source. */ 1047 rnd_detach_source(&sc->rnd_source); 1048 #endif 1049 callout_destroy(&sc->sc_diag_callout); 1050 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 1051 callout_destroy(&sc->sc_poll_callout); 1052 1053 com_mutex_enter(sc); 1054 com_mutex_exit(sc); 1055 1056 /* Destroy the lock. */ 1057 mutex_destroy(&sc->sc_lock); 1058 1059 return (0); 1060 } 1061 1062 void 1063 com_shutdown(struct com_softc *sc) 1064 { 1065 struct tty *tp = sc->sc_tty; 1066 1067 com_mutex_enter(sc); 1068 1069 /* If we were asserting flow control, then deassert it. */ 1070 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1071 com_hwiflow(sc); 1072 1073 /* Clear any break condition set with TIOCSBRK. */ 1074 com_break(sc, 0); 1075 1076 /* 1077 * Hang up if necessary. Record when we hung up, so if we 1078 * immediately open the port again, we will wait a bit until 1079 * the other side has had time to notice that we hung up. 1080 */ 1081 if (ISSET(tp->t_cflag, HUPCL)) { 1082 com_modem(sc, 0); 1083 microuptime(&sc->sc_hup_pending); 1084 sc->sc_hup_pending.tv_sec++; 1085 } 1086 1087 /* Turn off interrupts. */ 1088 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1089 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 1090 if ((sc->sc_type == COM_TYPE_PXA2x0) || 1091 (sc->sc_type == COM_TYPE_INGENIC) || 1092 (sc->sc_type == COM_TYPE_TEGRA)) 1093 sc->sc_ier |= IER_ERXTOUT; 1094 } else 1095 sc->sc_ier = 0; 1096 1097 if (sc->sc_type == COM_TYPE_PXA2x0) 1098 sc->sc_ier |= IER_EUART; 1099 1100 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1101 1102 com_mutex_exit(sc); 1103 1104 if (sc->disable) { 1105 #ifdef DIAGNOSTIC 1106 if (!sc->enabled) 1107 panic("com_shutdown: not enabled?"); 1108 #endif 1109 (*sc->disable)(sc); 1110 sc->enabled = 0; 1111 } 1112 } 1113 1114 int 1115 comopen(dev_t dev, int flag, int mode, struct lwp *l) 1116 { 1117 struct com_softc *sc; 1118 struct tty *tp; 1119 int s; 1120 int error; 1121 1122 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1123 1124 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 1125 sc->sc_rbuf == NULL) 1126 return (ENXIO); 1127 1128 if (!device_is_active(sc->sc_dev)) 1129 return (ENXIO); 1130 1131 #ifdef KGDB 1132 /* 1133 * If this is the kgdb port, no other use is permitted. 1134 */ 1135 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1136 return (EBUSY); 1137 #endif 1138 1139 tp = sc->sc_tty; 1140 1141 /* 1142 * If the device is exclusively for kernel use, deny userland 1143 * open. 1144 */ 1145 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1146 return (EBUSY); 1147 1148 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1149 return (EBUSY); 1150 1151 /* Run at the IPL_SOFTfoo level */ 1152 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 1153 s = splsoftserial(); 1154 else 1155 s = spltty(); 1156 1157 /* 1158 * Do the following iff this is a first open. 1159 */ 1160 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1161 struct termios t; 1162 struct timeval now, diff; 1163 1164 tp->t_dev = dev; 1165 1166 if (sc->enable) { 1167 if ((*sc->enable)(sc)) { 1168 splx(s); 1169 aprint_error_dev(sc->sc_dev, 1170 "device enable failed\n"); 1171 return (EIO); 1172 } 1173 com_mutex_enter(sc); 1174 sc->enabled = 1; 1175 com_config(sc); 1176 } else { 1177 com_mutex_enter(sc); 1178 } 1179 1180 if (timerisset(&sc->sc_hup_pending)) { 1181 microuptime(&now); 1182 while (timercmp(&now, &sc->sc_hup_pending, <)) { 1183 timersub(&sc->sc_hup_pending, &now, &diff); 1184 const int ms = diff.tv_sec * 1000 + 1185 diff.tv_usec / 1000; 1186 kpause(ttclos, false, uimax(mstohz(ms), 1), 1187 &sc->sc_lock); 1188 microuptime(&now); 1189 } 1190 timerclear(&sc->sc_hup_pending); 1191 } 1192 1193 /* Turn on interrupts. */ 1194 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1195 if (!ISSET(tp->t_cflag, CLOCAL)) 1196 sc->sc_ier |= IER_EMSC; 1197 1198 if (sc->sc_type == COM_TYPE_PXA2x0) 1199 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1200 else if (sc->sc_type == COM_TYPE_INGENIC || 1201 sc->sc_type == COM_TYPE_TEGRA) 1202 sc->sc_ier |= IER_ERXTOUT; 1203 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1204 1205 /* Fetch the current modem control status, needed later. */ 1206 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1207 1208 /* Clear PPS capture state on first open. */ 1209 mutex_spin_enter(&timecounter_lock); 1210 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1211 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1212 pps_init(&sc->sc_pps_state); 1213 mutex_spin_exit(&timecounter_lock); 1214 1215 com_mutex_exit(sc); 1216 1217 /* 1218 * Initialize the termios status to the defaults. Add in the 1219 * sticky bits from TIOCSFLAGS. 1220 */ 1221 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1222 t.c_ospeed = comcons_info.rate; 1223 t.c_cflag = comcons_info.cflag; 1224 } else { 1225 t.c_ospeed = TTYDEF_SPEED; 1226 t.c_cflag = TTYDEF_CFLAG; 1227 } 1228 t.c_ispeed = t.c_ospeed; 1229 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1230 SET(t.c_cflag, CLOCAL); 1231 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1232 SET(t.c_cflag, CRTSCTS); 1233 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1234 SET(t.c_cflag, MDMBUF); 1235 /* Make sure comparam() will do something. */ 1236 tp->t_ospeed = 0; 1237 (void) comparam(tp, &t); 1238 tp->t_iflag = TTYDEF_IFLAG; 1239 tp->t_oflag = TTYDEF_OFLAG; 1240 tp->t_lflag = TTYDEF_LFLAG; 1241 ttychars(tp); 1242 ttsetwater(tp); 1243 1244 com_mutex_enter(sc); 1245 1246 /* 1247 * Turn on DTR. We must always do this, even if carrier is not 1248 * present, because otherwise we'd have to use TIOCSDTR 1249 * immediately after setting CLOCAL, which applications do not 1250 * expect. We always assert DTR while the device is open 1251 * unless explicitly requested to deassert it. 1252 */ 1253 com_modem(sc, 1); 1254 1255 /* Clear the input ring, and unblock. */ 1256 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1257 sc->sc_rbavail = com_rbuf_size; 1258 com_iflush(sc); 1259 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1260 com_hwiflow(sc); 1261 1262 #ifdef COM_DEBUG 1263 if (com_debug) 1264 comstatus(sc, "comopen "); 1265 #endif 1266 1267 com_mutex_exit(sc); 1268 } 1269 1270 splx(s); 1271 1272 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1273 if (error) 1274 goto bad; 1275 1276 error = (*tp->t_linesw->l_open)(dev, tp); 1277 if (error) 1278 goto bad; 1279 1280 return (0); 1281 1282 bad: 1283 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1284 /* 1285 * We failed to open the device, and nobody else had it opened. 1286 * Clean up the state as appropriate. 1287 */ 1288 com_shutdown(sc); 1289 } 1290 1291 return (error); 1292 } 1293 1294 int 1295 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1296 { 1297 struct com_softc *sc = 1298 device_lookup_private(&com_cd, COMUNIT(dev)); 1299 struct tty *tp = sc->sc_tty; 1300 1301 /* XXX This is for cons.c. */ 1302 if (!ISSET(tp->t_state, TS_ISOPEN)) 1303 return (0); 1304 /* 1305 * If the device is exclusively for kernel use, deny userland 1306 * close. 1307 */ 1308 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1309 return (0); 1310 1311 (*tp->t_linesw->l_close)(tp, flag); 1312 ttyclose(tp); 1313 1314 if (COM_ISALIVE(sc) == 0) 1315 return (0); 1316 1317 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1318 /* 1319 * Although we got a last close, the device may still be in 1320 * use; e.g. if this was the dialout node, and there are still 1321 * processes waiting for carrier on the non-dialout node. 1322 */ 1323 com_shutdown(sc); 1324 } 1325 1326 return (0); 1327 } 1328 1329 int 1330 comread(dev_t dev, struct uio *uio, int flag) 1331 { 1332 struct com_softc *sc = 1333 device_lookup_private(&com_cd, COMUNIT(dev)); 1334 struct tty *tp = sc->sc_tty; 1335 1336 if (COM_ISALIVE(sc) == 0) 1337 return (EIO); 1338 1339 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1340 } 1341 1342 int 1343 comwrite(dev_t dev, struct uio *uio, int flag) 1344 { 1345 struct com_softc *sc = 1346 device_lookup_private(&com_cd, COMUNIT(dev)); 1347 struct tty *tp = sc->sc_tty; 1348 1349 if (COM_ISALIVE(sc) == 0) 1350 return (EIO); 1351 1352 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1353 } 1354 1355 int 1356 compoll(dev_t dev, int events, struct lwp *l) 1357 { 1358 struct com_softc *sc = 1359 device_lookup_private(&com_cd, COMUNIT(dev)); 1360 struct tty *tp = sc->sc_tty; 1361 1362 if (COM_ISALIVE(sc) == 0) 1363 return (POLLHUP); 1364 1365 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1366 } 1367 1368 struct tty * 1369 comtty(dev_t dev) 1370 { 1371 struct com_softc *sc = 1372 device_lookup_private(&com_cd, COMUNIT(dev)); 1373 struct tty *tp = sc->sc_tty; 1374 1375 return (tp); 1376 } 1377 1378 int 1379 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1380 { 1381 struct com_softc *sc; 1382 struct tty *tp; 1383 int error; 1384 1385 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1386 if (sc == NULL) 1387 return ENXIO; 1388 if (COM_ISALIVE(sc) == 0) 1389 return (EIO); 1390 1391 tp = sc->sc_tty; 1392 1393 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1394 if (error != EPASSTHROUGH) 1395 return (error); 1396 1397 error = ttioctl(tp, cmd, data, flag, l); 1398 if (error != EPASSTHROUGH) 1399 return (error); 1400 1401 error = 0; 1402 switch (cmd) { 1403 case TIOCSFLAGS: 1404 error = kauth_authorize_device_tty(l->l_cred, 1405 KAUTH_DEVICE_TTY_PRIVSET, tp); 1406 break; 1407 default: 1408 /* nothing */ 1409 break; 1410 } 1411 if (error) { 1412 return error; 1413 } 1414 1415 com_mutex_enter(sc); 1416 1417 switch (cmd) { 1418 case TIOCSBRK: 1419 com_break(sc, 1); 1420 break; 1421 1422 case TIOCCBRK: 1423 com_break(sc, 0); 1424 break; 1425 1426 case TIOCSDTR: 1427 com_modem(sc, 1); 1428 break; 1429 1430 case TIOCCDTR: 1431 com_modem(sc, 0); 1432 break; 1433 1434 case TIOCGFLAGS: 1435 *(int *)data = sc->sc_swflags; 1436 break; 1437 1438 case TIOCSFLAGS: 1439 sc->sc_swflags = *(int *)data; 1440 break; 1441 1442 case TIOCMSET: 1443 case TIOCMBIS: 1444 case TIOCMBIC: 1445 tiocm_to_com(sc, cmd, *(int *)data); 1446 break; 1447 1448 case TIOCMGET: 1449 *(int *)data = com_to_tiocm(sc); 1450 break; 1451 1452 case PPS_IOC_CREATE: 1453 case PPS_IOC_DESTROY: 1454 case PPS_IOC_GETPARAMS: 1455 case PPS_IOC_SETPARAMS: 1456 case PPS_IOC_GETCAP: 1457 case PPS_IOC_FETCH: 1458 #ifdef PPS_SYNC 1459 case PPS_IOC_KCBIND: 1460 #endif 1461 mutex_spin_enter(&timecounter_lock); 1462 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1463 mutex_spin_exit(&timecounter_lock); 1464 break; 1465 1466 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1467 mutex_spin_enter(&timecounter_lock); 1468 #ifndef PPS_TRAILING_EDGE 1469 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1470 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1471 #else 1472 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1473 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1474 #endif 1475 mutex_spin_exit(&timecounter_lock); 1476 break; 1477 1478 default: 1479 error = EPASSTHROUGH; 1480 break; 1481 } 1482 1483 com_mutex_exit(sc); 1484 1485 #ifdef COM_DEBUG 1486 if (com_debug) 1487 comstatus(sc, "comioctl "); 1488 #endif 1489 1490 return (error); 1491 } 1492 1493 static inline void 1494 com_schedrx(struct com_softc *sc) 1495 { 1496 sc->sc_rx_ready = 1; 1497 1498 /* Wake up the poller. */ 1499 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 1500 workqueue_enqueue(sc->sc_wq,(struct work *)&sc->sc_wk,NULL); 1501 else 1502 softint_schedule(sc->sc_si); 1503 } 1504 1505 void 1506 com_break(struct com_softc *sc, int onoff) 1507 { 1508 1509 if (onoff) 1510 SET(sc->sc_lcr, LCR_SBREAK); 1511 else 1512 CLR(sc->sc_lcr, LCR_SBREAK); 1513 1514 if (!sc->sc_heldchange) { 1515 if (sc->sc_tx_busy) { 1516 sc->sc_heldtbc = sc->sc_tbc; 1517 sc->sc_tbc = 0; 1518 sc->sc_heldchange = 1; 1519 } else 1520 com_loadchannelregs(sc); 1521 } 1522 } 1523 1524 void 1525 com_modem(struct com_softc *sc, int onoff) 1526 { 1527 1528 if (sc->sc_mcr_dtr == 0) 1529 return; 1530 1531 if (onoff) 1532 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1533 else 1534 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1535 1536 if (!sc->sc_heldchange) { 1537 if (sc->sc_tx_busy) { 1538 sc->sc_heldtbc = sc->sc_tbc; 1539 sc->sc_tbc = 0; 1540 sc->sc_heldchange = 1; 1541 } else 1542 com_loadchannelregs(sc); 1543 } 1544 } 1545 1546 void 1547 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1548 { 1549 u_char combits; 1550 1551 combits = 0; 1552 if (ISSET(ttybits, TIOCM_DTR)) 1553 SET(combits, MCR_DTR); 1554 if (ISSET(ttybits, TIOCM_RTS)) 1555 SET(combits, MCR_RTS); 1556 1557 switch (how) { 1558 case TIOCMBIC: 1559 CLR(sc->sc_mcr, combits); 1560 break; 1561 1562 case TIOCMBIS: 1563 SET(sc->sc_mcr, combits); 1564 break; 1565 1566 case TIOCMSET: 1567 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1568 SET(sc->sc_mcr, combits); 1569 break; 1570 } 1571 1572 if (!sc->sc_heldchange) { 1573 if (sc->sc_tx_busy) { 1574 sc->sc_heldtbc = sc->sc_tbc; 1575 sc->sc_tbc = 0; 1576 sc->sc_heldchange = 1; 1577 } else 1578 com_loadchannelregs(sc); 1579 } 1580 } 1581 1582 int 1583 com_to_tiocm(struct com_softc *sc) 1584 { 1585 u_char combits; 1586 int ttybits = 0; 1587 1588 combits = sc->sc_mcr; 1589 if (ISSET(combits, MCR_DTR)) 1590 SET(ttybits, TIOCM_DTR); 1591 if (ISSET(combits, MCR_RTS)) 1592 SET(ttybits, TIOCM_RTS); 1593 1594 combits = sc->sc_msr; 1595 if (sc->sc_type == COM_TYPE_INGENIC) { 1596 SET(ttybits, TIOCM_CD); 1597 } else { 1598 if (ISSET(combits, MSR_DCD)) 1599 SET(ttybits, TIOCM_CD); 1600 } 1601 if (ISSET(combits, MSR_CTS)) 1602 SET(ttybits, TIOCM_CTS); 1603 if (ISSET(combits, MSR_DSR)) 1604 SET(ttybits, TIOCM_DSR); 1605 if (ISSET(combits, MSR_RI | MSR_TERI)) 1606 SET(ttybits, TIOCM_RI); 1607 1608 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1609 SET(ttybits, TIOCM_LE); 1610 1611 return (ttybits); 1612 } 1613 1614 static u_char 1615 cflag2lcr(tcflag_t cflag) 1616 { 1617 u_char lcr = 0; 1618 1619 switch (ISSET(cflag, CSIZE)) { 1620 case CS5: 1621 SET(lcr, LCR_5BITS); 1622 break; 1623 case CS6: 1624 SET(lcr, LCR_6BITS); 1625 break; 1626 case CS7: 1627 SET(lcr, LCR_7BITS); 1628 break; 1629 case CS8: 1630 SET(lcr, LCR_8BITS); 1631 break; 1632 } 1633 if (ISSET(cflag, PARENB)) { 1634 SET(lcr, LCR_PENAB); 1635 if (!ISSET(cflag, PARODD)) 1636 SET(lcr, LCR_PEVEN); 1637 } 1638 if (ISSET(cflag, CSTOPB)) 1639 SET(lcr, LCR_STOPB); 1640 1641 return (lcr); 1642 } 1643 1644 int 1645 comparam(struct tty *tp, struct termios *t) 1646 { 1647 struct com_softc *sc = 1648 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1649 int ospeed; 1650 u_char lcr; 1651 1652 if (COM_ISALIVE(sc) == 0) 1653 return (EIO); 1654 1655 if (sc->sc_type == COM_TYPE_HAYESP) { 1656 int prescaler, speed; 1657 1658 /* 1659 * Calculate UART clock prescaler. It should be in 1660 * range of 0 .. 3. 1661 */ 1662 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1663 prescaler++, speed /= 2) 1664 if ((ospeed = comspeed(speed, sc->sc_frequency, 1665 sc->sc_type)) > 0) 1666 break; 1667 1668 if (prescaler == 4) 1669 return (EINVAL); 1670 sc->sc_prescaler = prescaler; 1671 } else { 1672 if (ISSET(sc->sc_hwflags, COM_HW_MCRPRESCALE)) { 1673 /* Try it without the prescaler, if that fails, enable 1674 * the prescaler and try again. 1675 */ 1676 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1677 CLR(sc->sc_mcr, MCR_PRESCALE); 1678 if (ospeed < 0) { 1679 ospeed = comspeed(t->c_ospeed, sc->sc_frequency / 4, sc->sc_type); 1680 if (ospeed >= 0) 1681 SET(sc->sc_mcr, MCR_PRESCALE); 1682 } 1683 } else { 1684 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1685 } 1686 } 1687 1688 /* Check requested parameters. */ 1689 if (ospeed < 0) 1690 return (EINVAL); 1691 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1692 return (EINVAL); 1693 1694 /* 1695 * For the console, always force CLOCAL and !HUPCL, so that the port 1696 * is always active. 1697 */ 1698 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1699 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1700 SET(t->c_cflag, CLOCAL); 1701 CLR(t->c_cflag, HUPCL); 1702 } 1703 1704 /* 1705 * If there were no changes, don't do anything. This avoids dropping 1706 * input and improves performance when all we did was frob things like 1707 * VMIN and VTIME. 1708 */ 1709 if (tp->t_ospeed == t->c_ospeed && 1710 tp->t_cflag == t->c_cflag) 1711 return (0); 1712 1713 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1714 1715 com_mutex_enter(sc); 1716 1717 sc->sc_lcr = lcr; 1718 1719 /* 1720 * If we're not in a mode that assumes a connection is present, then 1721 * ignore carrier changes. 1722 */ 1723 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1724 sc->sc_msr_dcd = 0; 1725 else 1726 sc->sc_msr_dcd = MSR_DCD; 1727 /* 1728 * Set the flow control pins depending on the current flow control 1729 * mode. 1730 */ 1731 if (ISSET(t->c_cflag, CRTSCTS)) { 1732 sc->sc_mcr_dtr = MCR_DTR; 1733 sc->sc_mcr_rts = MCR_RTS; 1734 sc->sc_msr_cts = MSR_CTS; 1735 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1736 SET(sc->sc_mcr, MCR_AFE); 1737 } else { 1738 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1739 } 1740 } else if (ISSET(t->c_cflag, MDMBUF)) { 1741 /* 1742 * For DTR/DCD flow control, make sure we don't toggle DTR for 1743 * carrier detection. 1744 */ 1745 sc->sc_mcr_dtr = 0; 1746 sc->sc_mcr_rts = MCR_DTR; 1747 sc->sc_msr_cts = MSR_DCD; 1748 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1749 CLR(sc->sc_mcr, MCR_AFE); 1750 } else { 1751 sc->sc_efr = 0; 1752 } 1753 } else { 1754 /* 1755 * If no flow control, then always set RTS. This will make 1756 * the other side happy if it mistakenly thinks we're doing 1757 * RTS/CTS flow control. 1758 */ 1759 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1760 sc->sc_mcr_rts = 0; 1761 sc->sc_msr_cts = 0; 1762 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1763 CLR(sc->sc_mcr, MCR_AFE); 1764 } else { 1765 sc->sc_efr = 0; 1766 } 1767 if (ISSET(sc->sc_mcr, MCR_DTR)) 1768 SET(sc->sc_mcr, MCR_RTS); 1769 else 1770 CLR(sc->sc_mcr, MCR_RTS); 1771 } 1772 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1773 1774 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1775 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1776 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1777 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1778 1779 sc->sc_dlbl = ospeed; 1780 sc->sc_dlbh = ospeed >> 8; 1781 1782 /* 1783 * Set the FIFO threshold based on the receive speed. 1784 * 1785 * * If it's a low speed, it's probably a mouse or some other 1786 * interactive device, so set the threshold low. 1787 * * If it's a high speed, trim the trigger level down to prevent 1788 * overflows. 1789 * * Otherwise set it a bit higher. 1790 */ 1791 if (sc->sc_type == COM_TYPE_HAYESP) { 1792 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1793 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1794 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1795 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1796 if (t->c_ospeed <= 1200) 1797 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1798 else if (t->c_ospeed <= 38400) 1799 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1800 else 1801 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1802 } else { 1803 sc->sc_fifo = 0; 1804 } 1805 1806 if (sc->sc_type == COM_TYPE_INGENIC) 1807 sc->sc_fifo |= FIFO_UART_ON; 1808 1809 /* And copy to tty. */ 1810 tp->t_ispeed = t->c_ospeed; 1811 tp->t_ospeed = t->c_ospeed; 1812 tp->t_cflag = t->c_cflag; 1813 1814 if (!sc->sc_heldchange) { 1815 if (sc->sc_tx_busy) { 1816 sc->sc_heldtbc = sc->sc_tbc; 1817 sc->sc_tbc = 0; 1818 sc->sc_heldchange = 1; 1819 } else 1820 com_loadchannelregs(sc); 1821 } 1822 1823 if (!ISSET(t->c_cflag, CHWFLOW)) { 1824 /* Disable the high water mark. */ 1825 sc->sc_r_hiwat = 0; 1826 sc->sc_r_lowat = 0; 1827 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1828 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1829 com_schedrx(sc); 1830 } 1831 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1832 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1833 com_hwiflow(sc); 1834 } 1835 } else { 1836 sc->sc_r_hiwat = com_rbuf_hiwat; 1837 sc->sc_r_lowat = com_rbuf_lowat; 1838 } 1839 1840 com_mutex_exit(sc); 1841 1842 /* 1843 * Update the tty layer's idea of the carrier bit, in case we changed 1844 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1845 * explicit request. 1846 */ 1847 if (sc->sc_type == COM_TYPE_INGENIC) { 1848 /* no DCD here */ 1849 (void) (*tp->t_linesw->l_modem)(tp, 1); 1850 } else 1851 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1852 1853 #ifdef COM_DEBUG 1854 if (com_debug) 1855 comstatus(sc, "comparam "); 1856 #endif 1857 1858 if (!ISSET(t->c_cflag, CHWFLOW)) { 1859 if (sc->sc_tx_stopped) { 1860 sc->sc_tx_stopped = 0; 1861 comstart(tp); 1862 } 1863 } 1864 1865 return (0); 1866 } 1867 1868 void 1869 com_iflush(struct com_softc *sc) 1870 { 1871 struct com_regs *regsp = &sc->sc_regs; 1872 uint8_t fifo; 1873 #ifdef DIAGNOSTIC 1874 int reg; 1875 #endif 1876 int timo; 1877 1878 #ifdef DIAGNOSTIC 1879 reg = 0xffff; 1880 #endif 1881 timo = 50000; 1882 /* flush any pending I/O */ 1883 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1884 && --timo) 1885 #ifdef DIAGNOSTIC 1886 reg = 1887 #else 1888 (void) 1889 #endif 1890 CSR_READ_1(regsp, COM_REG_RXDATA); 1891 #ifdef DIAGNOSTIC 1892 if (!timo) 1893 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1894 #endif 1895 1896 switch (sc->sc_type) { 1897 case COM_TYPE_16750: 1898 case COM_TYPE_DW_APB: 1899 /* 1900 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1901 * This should prevent triggering busy interrupt while 1902 * manipulating divisors. 1903 */ 1904 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1905 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1906 CSR_WRITE_1(regsp, COM_REG_FIFO, 1907 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1908 delay(100); 1909 break; 1910 } 1911 } 1912 1913 void 1914 com_loadchannelregs(struct com_softc *sc) 1915 { 1916 struct com_regs *regsp = &sc->sc_regs; 1917 1918 /* XXXXX necessary? */ 1919 com_iflush(sc); 1920 1921 if (sc->sc_type == COM_TYPE_PXA2x0) 1922 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1923 else 1924 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1925 1926 if (sc->sc_type == COM_TYPE_OMAP) { 1927 /* disable before changing settings */ 1928 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1929 } 1930 1931 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1932 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1933 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1934 /* no EFR on alchemy */ 1935 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1936 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1937 } 1938 if (ISSET(sc->sc_hwflags, COM_HW_MCRPRESCALE)) { 1939 /* Unlock the prescale bit */ 1940 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1941 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr | EFR_EFCR); 1942 } 1943 if (sc->sc_type == COM_TYPE_AU1x00) { 1944 /* alchemy has single separate 16-bit clock divisor register */ 1945 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1946 (sc->sc_dlbh << 8)); 1947 } else { 1948 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1949 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1950 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1951 } 1952 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1953 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1954 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1955 if (ISSET(sc->sc_hwflags, COM_HW_MCRPRESCALE)) { 1956 /* Lock the prescale bit back up again */ 1957 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1958 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1959 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1960 } 1961 if (sc->sc_type == COM_TYPE_HAYESP) { 1962 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1963 HAYESP_SETPRESCALER); 1964 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1965 sc->sc_prescaler); 1966 } 1967 if (sc->sc_type == COM_TYPE_OMAP) { 1968 /* setup the fifos. the FCR value is not used as long 1969 as SCR[6] and SCR[7] are 0, which they are at reset 1970 and we never touch the SCR register */ 1971 uint8_t rx_fifo_trig = 40; 1972 uint8_t tx_fifo_trig = 60; 1973 uint8_t rx_start = 8; 1974 uint8_t rx_halt = 60; 1975 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1976 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1977 1978 /* enable access to TCR & TLR */ 1979 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1980 1981 /* write tcr and tlr values */ 1982 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1983 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1984 1985 /* disable access to TCR & TLR */ 1986 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1987 1988 /* enable again, but mode is based on speed */ 1989 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1990 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1991 } else { 1992 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1993 } 1994 } 1995 1996 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1997 } 1998 1999 int 2000 comhwiflow(struct tty *tp, int block) 2001 { 2002 struct com_softc *sc = 2003 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2004 2005 if (COM_ISALIVE(sc) == 0) 2006 return (0); 2007 2008 if (sc->sc_mcr_rts == 0) 2009 return (0); 2010 2011 com_mutex_enter(sc); 2012 2013 if (block) { 2014 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2015 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 2016 com_hwiflow(sc); 2017 } 2018 } else { 2019 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 2020 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2021 com_schedrx(sc); 2022 } 2023 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2024 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 2025 com_hwiflow(sc); 2026 } 2027 } 2028 2029 com_mutex_exit(sc); 2030 return (1); 2031 } 2032 2033 int 2034 comhwiflowsoft(struct tty *tp, int block) 2035 { 2036 int r; 2037 2038 mutex_spin_exit(&tty_lock); 2039 r = comhwiflow(tp, block); 2040 mutex_spin_enter(&tty_lock); 2041 2042 return r; 2043 } 2044 2045 /* 2046 * (un)block input via hw flowcontrol 2047 */ 2048 void 2049 com_hwiflow(struct com_softc *sc) 2050 { 2051 struct com_regs *regsp= &sc->sc_regs; 2052 2053 if (sc->sc_mcr_rts == 0) 2054 return; 2055 2056 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 2057 CLR(sc->sc_mcr, sc->sc_mcr_rts); 2058 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 2059 } else { 2060 SET(sc->sc_mcr, sc->sc_mcr_rts); 2061 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 2062 } 2063 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 2064 } 2065 2066 2067 void 2068 comstart(struct tty *tp) 2069 { 2070 struct com_softc *sc = 2071 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2072 struct com_regs *regsp = &sc->sc_regs; 2073 2074 if (COM_ISALIVE(sc) == 0) 2075 return; 2076 2077 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 2078 return; 2079 if (sc->sc_tx_stopped) 2080 return; 2081 if (!ttypull(tp)) 2082 return; 2083 2084 /* Grab the first contiguous region of buffer space. */ 2085 { 2086 u_char *tba; 2087 int tbc; 2088 2089 tba = tp->t_outq.c_cf; 2090 tbc = ndqb(&tp->t_outq, 0); 2091 2092 com_mutex_enter(sc); 2093 2094 sc->sc_tba = tba; 2095 sc->sc_tbc = tbc; 2096 } 2097 2098 SET(tp->t_state, TS_BUSY); 2099 sc->sc_tx_busy = 1; 2100 2101 /* Enable transmit completion interrupts if necessary. */ 2102 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 2103 SET(sc->sc_ier, IER_ETXRDY); 2104 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2105 } 2106 2107 /* Output the first chunk of the contiguous buffer. */ 2108 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 2109 u_int n; 2110 2111 n = sc->sc_tbc; 2112 if (n > sc->sc_fifolen) 2113 n = sc->sc_fifolen; 2114 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2115 sc->sc_tbc -= n; 2116 sc->sc_tba += n; 2117 } 2118 2119 com_mutex_exit(sc); 2120 } 2121 2122 /* Do an ugly thing in the softirq case. We can't have a spin lock held right now, 2123 * so drop it. 2124 */ 2125 2126 void 2127 comstartsoft(struct tty *tp) 2128 { 2129 mutex_spin_exit(&tty_lock); 2130 comstart(tp); 2131 mutex_spin_enter(&tty_lock); 2132 } 2133 2134 /* 2135 * Stop output on a line. 2136 * 2137 * For reasons that are not obvious dropping the tty_lock spin lock was not 2138 * enough for the stop call and if you try to acquire a adaptive lock while 2139 * holding a spin lock you will panic, so just don't acquire it. 2140 */ 2141 void 2142 comstop(struct tty *tp, int flag) 2143 { 2144 struct com_softc *sc = 2145 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2146 2147 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 2148 com_mutex_enter(sc); 2149 if (ISSET(tp->t_state, TS_BUSY)) { 2150 /* Stop transmitting at the next chunk. */ 2151 sc->sc_tbc = 0; 2152 sc->sc_heldtbc = 0; 2153 if (!ISSET(tp->t_state, TS_TTSTOP)) 2154 SET(tp->t_state, TS_FLUSH); 2155 } 2156 if (!ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 2157 com_mutex_exit(sc); 2158 } 2159 2160 2161 void 2162 comdiag(void *arg) 2163 { 2164 struct com_softc *sc = arg; 2165 int overflows, floods; 2166 2167 com_mutex_enter(sc); 2168 overflows = sc->sc_overflows; 2169 sc->sc_overflows = 0; 2170 floods = sc->sc_floods; 2171 sc->sc_floods = 0; 2172 sc->sc_errors = 0; 2173 com_mutex_exit(sc); 2174 2175 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 2176 device_xname(sc->sc_dev), 2177 overflows, overflows == 1 ? "" : "s", 2178 floods, floods == 1 ? "" : "s"); 2179 } 2180 2181 static inline void 2182 com_rxsoft(struct com_softc *sc, struct tty *tp) 2183 { 2184 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 2185 u_char *get, *end; 2186 u_int cc, scc; 2187 u_char lsr; 2188 int code; 2189 2190 end = sc->sc_ebuf; 2191 get = sc->sc_rbget; 2192 scc = cc = com_rbuf_size - sc->sc_rbavail; 2193 2194 if (cc == com_rbuf_size) { 2195 sc->sc_floods++; 2196 if (sc->sc_errors++ == 0) 2197 callout_reset(&sc->sc_diag_callout, 60 * hz, 2198 comdiag, sc); 2199 } 2200 2201 /* If not yet open, drop the entire buffer content here */ 2202 if (!ISSET(tp->t_state, TS_ISOPEN)) { 2203 get += cc << 1; 2204 if (get >= end) 2205 get -= com_rbuf_size << 1; 2206 cc = 0; 2207 } 2208 while (cc) { 2209 code = get[0]; 2210 lsr = get[1]; 2211 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 2212 if (ISSET(lsr, LSR_OE)) { 2213 sc->sc_overflows++; 2214 if (sc->sc_errors++ == 0) 2215 callout_reset(&sc->sc_diag_callout, 2216 60 * hz, comdiag, sc); 2217 } 2218 if (ISSET(lsr, LSR_BI | LSR_FE)) 2219 SET(code, TTY_FE); 2220 if (ISSET(lsr, LSR_PE)) 2221 SET(code, TTY_PE); 2222 } 2223 if ((*rint)(code, tp) == -1) { 2224 /* 2225 * The line discipline's buffer is out of space. 2226 */ 2227 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2228 /* 2229 * We're either not using flow control, or the 2230 * line discipline didn't tell us to block for 2231 * some reason. Either way, we have no way to 2232 * know when there's more space available, so 2233 * just drop the rest of the data. 2234 */ 2235 get += cc << 1; 2236 if (get >= end) 2237 get -= com_rbuf_size << 1; 2238 cc = 0; 2239 } else { 2240 /* 2241 * Don't schedule any more receive processing 2242 * until the line discipline tells us there's 2243 * space available (through comhwiflow()). 2244 * Leave the rest of the data in the input 2245 * buffer. 2246 */ 2247 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2248 } 2249 break; 2250 } 2251 get += 2; 2252 if (get >= end) 2253 get = sc->sc_rbuf; 2254 cc--; 2255 } 2256 2257 if (cc != scc) { 2258 sc->sc_rbget = get; 2259 com_mutex_enter(sc); 2260 2261 cc = sc->sc_rbavail += scc - cc; 2262 /* Buffers should be ok again, release possible block. */ 2263 if (cc >= sc->sc_r_lowat) { 2264 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2265 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2266 SET(sc->sc_ier, IER_ERXRDY); 2267 if (sc->sc_type == COM_TYPE_PXA2x0) 2268 SET(sc->sc_ier, IER_ERXTOUT); 2269 if (sc->sc_type == COM_TYPE_INGENIC || 2270 sc->sc_type == COM_TYPE_TEGRA) 2271 SET(sc->sc_ier, IER_ERXTOUT); 2272 2273 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2274 sc->sc_ier); 2275 } 2276 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2277 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2278 com_hwiflow(sc); 2279 } 2280 } 2281 com_mutex_exit(sc); 2282 } 2283 } 2284 2285 static inline void 2286 com_txsoft(struct com_softc *sc, struct tty *tp) 2287 { 2288 2289 CLR(tp->t_state, TS_BUSY); 2290 if (ISSET(tp->t_state, TS_FLUSH)) 2291 CLR(tp->t_state, TS_FLUSH); 2292 else 2293 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2294 2295 /* This used to be (*tp->t_linesw->l_start)(tp) which is probably more 2296 * correct, however... in the softirq case, it won't work as comstartsoft 2297 * will try and drop the spin lock and there isn't one of those when called 2298 * from here. In any case, l_start is just comstartsoft or comstart anyway 2299 * and there are other places in this code that just calls comstart, so 2300 * do likewise. 2301 */ 2302 comstart(tp); 2303 } 2304 2305 static inline void 2306 com_stsoft(struct com_softc *sc, struct tty *tp) 2307 { 2308 u_char msr, delta; 2309 2310 com_mutex_enter(sc); 2311 msr = sc->sc_msr; 2312 delta = sc->sc_msr_delta; 2313 sc->sc_msr_delta = 0; 2314 com_mutex_exit(sc); 2315 2316 if (ISSET(delta, sc->sc_msr_dcd)) { 2317 /* 2318 * Inform the tty layer that carrier detect changed. 2319 */ 2320 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2321 } 2322 2323 if (ISSET(delta, sc->sc_msr_cts)) { 2324 /* Block or unblock output according to flow control. */ 2325 if (ISSET(msr, sc->sc_msr_cts)) { 2326 sc->sc_tx_stopped = 0; 2327 /* See note above about (*tp->t_linesw->l_start)(tp); */ 2328 comstart(tp); 2329 } else { 2330 sc->sc_tx_stopped = 1; 2331 } 2332 } 2333 2334 #ifdef COM_DEBUG 2335 if (com_debug) 2336 comstatus(sc, "com_stsoft"); 2337 #endif 2338 } 2339 2340 void 2341 comsoft(void *arg) 2342 { 2343 struct com_softc *sc = arg; 2344 struct tty *tp; 2345 2346 if (COM_ISALIVE(sc) == 0) 2347 return; 2348 2349 tp = sc->sc_tty; 2350 2351 if (sc->sc_rx_ready) { 2352 sc->sc_rx_ready = 0; 2353 com_rxsoft(sc, tp); 2354 } 2355 2356 if (sc->sc_st_check) { 2357 sc->sc_st_check = 0; 2358 com_stsoft(sc, tp); 2359 } 2360 2361 if (sc->sc_tx_done) { 2362 sc->sc_tx_done = 0; 2363 com_txsoft(sc, tp); 2364 } 2365 } 2366 2367 static void 2368 comsoftwq(struct work *wk, void *arg) 2369 { 2370 struct com_softc *sc = arg; 2371 struct com_regs *regsp = &sc->sc_regs; 2372 2373 if (CSR_HAS_ERROR(regsp)) { 2374 return; 2375 } 2376 2377 comsoft(sc); 2378 } 2379 2380 int 2381 comintr(void *arg) 2382 { 2383 struct com_softc *sc = arg; 2384 struct com_regs *regsp = &sc->sc_regs; 2385 2386 u_char *put, *end; 2387 u_int cc; 2388 u_char lsr, iir; 2389 2390 if (COM_ISALIVE(sc) == 0) 2391 return (0); 2392 2393 KASSERT(regsp != NULL); 2394 2395 com_mutex_enter(sc); 2396 iir = CSR_READ_1(regsp, COM_REG_IIR); 2397 2398 if (CSR_HAS_ERROR(regsp)) { 2399 com_mutex_exit(sc); 2400 return (0); 2401 } 2402 2403 /* Handle ns16750-specific busy interrupt. */ 2404 if (sc->sc_type == COM_TYPE_16750 && 2405 (iir & IIR_BUSY) == IIR_BUSY) { 2406 for (int timeout = 10000; 2407 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) { 2408 if (CSR_HAS_ERROR(regsp)) { 2409 com_mutex_exit(sc); 2410 return (0); 2411 } 2412 if (timeout <= 0) { 2413 aprint_error_dev(sc->sc_dev, 2414 "timeout while waiting for BUSY interrupt " 2415 "acknowledge\n"); 2416 com_mutex_exit(sc); 2417 return (0); 2418 } 2419 } 2420 2421 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2422 iir = CSR_READ_1(regsp, COM_REG_IIR); 2423 } 2424 2425 /* DesignWare APB UART BUSY interrupt */ 2426 if (sc->sc_type == COM_TYPE_DW_APB && 2427 (iir & IIR_BUSY) == IIR_BUSY) { 2428 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 2429 (void)CSR_READ_1(regsp, COM_REG_USR); 2430 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2431 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2432 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2433 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2434 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2435 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2436 CSR_WRITE_1(regsp, COM_REG_HALT, 2437 HALT_CHCFG_EN | HALT_CHCFG_UD); 2438 for (int timeout = 10000000; 2439 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2440 timeout--) { 2441 if (CSR_HAS_ERROR(regsp)) { 2442 com_mutex_exit(sc); 2443 return (0); 2444 } 2445 if (timeout <= 0) { 2446 aprint_error_dev(sc->sc_dev, 2447 "timeout while waiting for HALT " 2448 "update acknowledge 0x%x 0x%x\n", 2449 CSR_READ_1(regsp, COM_REG_HALT), 2450 CSR_READ_1(regsp, COM_REG_USR)); 2451 break; 2452 } 2453 } 2454 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2455 (void)CSR_READ_1(regsp, COM_REG_USR); 2456 } else { 2457 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2458 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2459 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2460 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2461 } 2462 } 2463 2464 end = sc->sc_ebuf; 2465 put = sc->sc_rbput; 2466 cc = sc->sc_rbavail; 2467 2468 if (ISSET(iir, IIR_NOPEND)) { 2469 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2470 goto do_tx; 2471 com_mutex_exit(sc); 2472 return (0); 2473 } 2474 2475 again: do { 2476 u_char msr, delta; 2477 2478 if (CSR_HAS_ERROR(regsp)) { 2479 com_mutex_exit(sc); 2480 return (0); 2481 } 2482 2483 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2484 if (ISSET(lsr, LSR_BI)) { 2485 int cn_trapped = 0; /* see above: cn_trap() */ 2486 2487 cn_check_magic(sc->sc_tty->t_dev, 2488 CNC_BREAK, com_cnm_state); 2489 if (cn_trapped) 2490 continue; 2491 #if defined(KGDB) && !defined(DDB) 2492 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2493 kgdb_connect(1); 2494 continue; 2495 } 2496 #endif 2497 } 2498 2499 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2500 lsr |= LSR_RXRDY; 2501 2502 if (ISSET(lsr, LSR_RCV_MASK) && 2503 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2504 while (cc > 0) { 2505 int cn_trapped = 0; 2506 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2507 put[1] = lsr; 2508 cn_check_magic(sc->sc_tty->t_dev, 2509 put[0], com_cnm_state); 2510 if (cn_trapped) 2511 goto next; 2512 put += 2; 2513 if (put >= end) 2514 put = sc->sc_rbuf; 2515 cc--; 2516 next: 2517 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2518 if (!ISSET(lsr, LSR_RCV_MASK)) 2519 break; 2520 2521 if (CSR_HAS_ERROR(regsp)) { 2522 com_mutex_exit(sc); 2523 return (0); 2524 } 2525 } 2526 2527 /* 2528 * Current string of incoming characters ended because 2529 * no more data was available or we ran out of space. 2530 * Schedule a receive event if any data was received. 2531 * If we're out of space, turn off receive interrupts. 2532 */ 2533 sc->sc_rbput = put; 2534 sc->sc_rbavail = cc; 2535 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2536 sc->sc_rx_ready = 1; 2537 2538 /* 2539 * See if we are in danger of overflowing a buffer. If 2540 * so, use hardware flow control to ease the pressure. 2541 */ 2542 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2543 cc < sc->sc_r_hiwat) { 2544 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2545 com_hwiflow(sc); 2546 } 2547 2548 /* 2549 * If we're out of space, disable receive interrupts 2550 * until the queue has drained a bit. 2551 */ 2552 if (!cc) { 2553 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2554 switch (sc->sc_type) { 2555 case COM_TYPE_PXA2x0: 2556 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2557 break; 2558 case COM_TYPE_INGENIC: 2559 case COM_TYPE_TEGRA: 2560 CLR(sc->sc_ier, 2561 IER_ERXRDY | IER_ERXTOUT); 2562 break; 2563 default: 2564 CLR(sc->sc_ier, IER_ERXRDY); 2565 break; 2566 } 2567 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2568 } 2569 } else { 2570 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2571 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2572 continue; 2573 } 2574 } 2575 2576 msr = CSR_READ_1(regsp, COM_REG_MSR); 2577 if (CSR_HAS_ERROR(regsp)) { 2578 com_mutex_exit(sc); 2579 return (0); 2580 } 2581 delta = msr ^ sc->sc_msr; 2582 sc->sc_msr = msr; 2583 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2584 (delta & MSR_DCD)) { 2585 mutex_spin_enter(&timecounter_lock); 2586 pps_capture(&sc->sc_pps_state); 2587 pps_event(&sc->sc_pps_state, 2588 (msr & MSR_DCD) ? 2589 PPS_CAPTUREASSERT : 2590 PPS_CAPTURECLEAR); 2591 mutex_spin_exit(&timecounter_lock); 2592 } 2593 2594 /* 2595 * Process normal status changes 2596 */ 2597 if (ISSET(delta, sc->sc_msr_mask)) { 2598 SET(sc->sc_msr_delta, delta); 2599 2600 /* 2601 * Stop output immediately if we lose the output 2602 * flow control signal or carrier detect. 2603 */ 2604 if (ISSET(~msr, sc->sc_msr_mask)) { 2605 sc->sc_tbc = 0; 2606 sc->sc_heldtbc = 0; 2607 #ifdef COM_DEBUG 2608 if (com_debug) 2609 comstatus(sc, "comintr "); 2610 #endif 2611 } 2612 2613 sc->sc_st_check = 1; 2614 } 2615 } while (!ISSET((iir = 2616 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2617 /* 2618 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2619 * by IIR read, so we can't do this way: `process all interrupts, 2620 * then do TX if possible'. 2621 */ 2622 (iir & IIR_IMASK) != IIR_TXRDY); 2623 2624 do_tx: 2625 /* 2626 * Read LSR again, since there may be an interrupt between 2627 * the last LSR read and IIR read above. 2628 */ 2629 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2630 2631 if (CSR_HAS_ERROR(regsp)) { 2632 com_mutex_exit(sc); 2633 return (0); 2634 } 2635 2636 /* 2637 * See if data can be transmitted as well. 2638 * Schedule tx done event if no data left 2639 * and tty was marked busy. 2640 */ 2641 if (ISSET(lsr, LSR_TXRDY)) { 2642 /* 2643 * If we've delayed a parameter change, do it now, and restart 2644 * output. 2645 */ 2646 if (sc->sc_heldchange) { 2647 com_loadchannelregs(sc); 2648 sc->sc_heldchange = 0; 2649 sc->sc_tbc = sc->sc_heldtbc; 2650 sc->sc_heldtbc = 0; 2651 } 2652 2653 /* Output the next chunk of the contiguous buffer, if any. */ 2654 if (sc->sc_tbc > 0) { 2655 u_int n; 2656 2657 n = sc->sc_tbc; 2658 if (n > sc->sc_fifolen) 2659 n = sc->sc_fifolen; 2660 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2661 sc->sc_tbc -= n; 2662 sc->sc_tba += n; 2663 } else { 2664 /* Disable transmit completion interrupts if necessary. */ 2665 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2666 CLR(sc->sc_ier, IER_ETXRDY); 2667 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2668 } 2669 if (sc->sc_tx_busy) { 2670 sc->sc_tx_busy = 0; 2671 sc->sc_tx_done = 1; 2672 } 2673 } 2674 } 2675 2676 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2677 goto again; 2678 2679 com_mutex_exit(sc); 2680 2681 if (CSR_HAS_ERROR(regsp)) { 2682 return (0); 2683 } 2684 2685 /* Wake up the poller. */ 2686 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) { 2687 if (ISSET(sc->sc_hwflags, COM_HW_SOFTIRQ)) 2688 workqueue_enqueue(sc->sc_wq,(struct work *)&sc->sc_wk,NULL); 2689 else 2690 softint_schedule(sc->sc_si); 2691 } 2692 2693 #ifdef RND_COM 2694 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2695 #endif 2696 2697 return (1); 2698 } 2699 2700 /* 2701 * The following functions are polled getc and putc routines, shared 2702 * by the console and kgdb glue. 2703 * 2704 * The read-ahead code is so that you can detect pending in-band 2705 * cn_magic in polled mode while doing output rather than having to 2706 * wait until the kernel decides it needs input. 2707 */ 2708 2709 #define MAX_READAHEAD 20 2710 static int com_readahead[MAX_READAHEAD]; 2711 static int com_readaheadcount = 0; 2712 2713 int 2714 com_common_getc(dev_t dev, struct com_regs *regsp) 2715 { 2716 int s = splserial(); 2717 u_char stat, c; 2718 2719 /* got a character from reading things earlier */ 2720 if (com_readaheadcount > 0) { 2721 int i; 2722 2723 c = com_readahead[0]; 2724 for (i = 1; i < com_readaheadcount; i++) { 2725 com_readahead[i-1] = com_readahead[i]; 2726 } 2727 com_readaheadcount--; 2728 splx(s); 2729 return (c); 2730 } 2731 2732 /* don't block until a character becomes available */ 2733 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2734 splx(s); 2735 return -1; 2736 } 2737 2738 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2739 stat = CSR_READ_1(regsp, COM_REG_IIR); 2740 { 2741 int cn_trapped = 0; /* required by cn_trap, see above */ 2742 if (!db_active) 2743 cn_check_magic(dev, c, com_cnm_state); 2744 } 2745 splx(s); 2746 return (c); 2747 } 2748 2749 static void 2750 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2751 { 2752 int s = splserial(); 2753 int cin, stat, timo; 2754 2755 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2756 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2757 int cn_trapped = 0; 2758 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2759 stat = CSR_READ_1(regsp, COM_REG_IIR); 2760 cn_check_magic(dev, cin, com_cnm_state); 2761 com_readahead[com_readaheadcount++] = cin; 2762 } 2763 2764 /* wait for any pending transmission to finish */ 2765 timo = 150000; 2766 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2767 continue; 2768 2769 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2770 COM_BARRIER(regsp, BR | BW); 2771 2772 splx(s); 2773 } 2774 2775 /* 2776 * Initialize UART for use as console or KGDB line. 2777 */ 2778 int 2779 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2780 tcflag_t cflag) 2781 { 2782 2783 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2784 ®sp->cr_ioh)) 2785 return (ENOMEM); /* ??? */ 2786 2787 if (type == COM_TYPE_OMAP) { 2788 /* disable before changing settings */ 2789 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2790 } 2791 2792 rate = comspeed(rate, frequency, type); 2793 if (rate != -1) { 2794 if (type == COM_TYPE_AU1x00) { 2795 /* no EFR on alchemy */ 2796 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2797 } else { 2798 if ((type != COM_TYPE_16550_NOERS) && 2799 (type != COM_TYPE_INGENIC)) { 2800 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2801 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2802 } 2803 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2804 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2805 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2806 } 2807 } 2808 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2809 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2810 2811 if (type == COM_TYPE_INGENIC) { 2812 CSR_WRITE_1(regsp, COM_REG_FIFO, 2813 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2814 FIFO_TRIGGER_1 | FIFO_UART_ON); 2815 } else { 2816 CSR_WRITE_1(regsp, COM_REG_FIFO, 2817 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2818 FIFO_TRIGGER_1); 2819 } 2820 2821 if (type == COM_TYPE_OMAP) { 2822 /* setup the fifos. the FCR value is not used as long 2823 as SCR[6] and SCR[7] are 0, which they are at reset 2824 and we never touch the SCR register */ 2825 uint8_t rx_fifo_trig = 40; 2826 uint8_t tx_fifo_trig = 60; 2827 uint8_t rx_start = 8; 2828 uint8_t rx_halt = 60; 2829 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2830 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2831 2832 /* enable access to TCR & TLR */ 2833 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2834 2835 /* write tcr and tlr values */ 2836 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2837 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2838 2839 /* disable access to TCR & TLR */ 2840 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2841 2842 /* enable again, but mode is based on speed */ 2843 if (rate > 230400) { 2844 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2845 } else { 2846 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2847 } 2848 } 2849 2850 if (type == COM_TYPE_PXA2x0) 2851 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2852 else 2853 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2854 2855 return (0); 2856 } 2857 2858 int 2859 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2860 tcflag_t cflag) 2861 { 2862 int res; 2863 2864 comcons_info.regs = *regsp; 2865 2866 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2867 if (res) 2868 return (res); 2869 2870 cn_tab = &comcons; 2871 cn_init_magic(&com_cnm_state); 2872 cn_set_magic("\047\001"); /* default magic is BREAK */ 2873 2874 comcons_info.frequency = frequency; 2875 comcons_info.type = type; 2876 comcons_info.rate = rate; 2877 comcons_info.cflag = cflag; 2878 2879 return (0); 2880 } 2881 2882 int 2883 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2884 int type, tcflag_t cflag) 2885 { 2886 struct com_regs regs; 2887 2888 /*XXX*/ 2889 bus_space_handle_t dummy_bsh; 2890 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2891 2892 /* 2893 * dummy_bsh required because com_init_regs() wants it. A 2894 * real bus_space_handle will be filled in by cominit() later. 2895 * XXXJRT Detangle this mess eventually, plz. 2896 */ 2897 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2898 2899 return comcnattach1(®s, rate, frequency, type, cflag); 2900 } 2901 2902 static int 2903 comcnreattach(void) 2904 { 2905 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2906 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2907 } 2908 2909 int 2910 comcngetc(dev_t dev) 2911 { 2912 2913 return (com_common_getc(dev, &comcons_info.regs)); 2914 } 2915 2916 /* 2917 * Console kernel output character routine. 2918 */ 2919 void 2920 comcnputc(dev_t dev, int c) 2921 { 2922 2923 com_common_putc(dev, &comcons_info.regs, c, cold); 2924 } 2925 2926 void 2927 comcnpollc(dev_t dev, int on) 2928 { 2929 2930 com_readaheadcount = 0; 2931 } 2932 2933 #ifdef KGDB 2934 int 2935 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2936 tcflag_t cflag) 2937 { 2938 int res; 2939 2940 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2941 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2942 #if !defined(DDB) 2943 return (EBUSY); /* cannot share with console */ 2944 #else 2945 comkgdbregs = *regsp; 2946 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2947 #endif 2948 } else { 2949 comkgdbregs = *regsp; 2950 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2951 if (res) 2952 return (res); 2953 2954 /* 2955 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2956 * expects this to be initialized 2957 */ 2958 cn_init_magic(&com_cnm_state); 2959 cn_set_magic("\047\001"); 2960 } 2961 2962 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2963 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2964 2965 return (0); 2966 } 2967 2968 int 2969 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2970 int frequency, int type, tcflag_t cflag) 2971 { 2972 struct com_regs regs; 2973 2974 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2975 2976 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2977 } 2978 2979 /* ARGSUSED */ 2980 int 2981 com_kgdb_getc(void *arg) 2982 { 2983 2984 return (com_common_getc(NODEV, &comkgdbregs)); 2985 } 2986 2987 /* ARGSUSED */ 2988 void 2989 com_kgdb_putc(void *arg, int c) 2990 { 2991 2992 com_common_putc(NODEV, &comkgdbregs, c, 0); 2993 } 2994 #endif /* KGDB */ 2995 2996 /* 2997 * helper function to identify the com ports used by 2998 * console or KGDB (and not yet autoconf attached) 2999 */ 3000 int 3001 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 3002 { 3003 bus_space_handle_t help; 3004 3005 if (!comconsattached && 3006 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 3007 iobase == comcons_info.regs.cr_iobase) 3008 help = comcons_info.regs.cr_ioh; 3009 #ifdef KGDB 3010 else if (!com_kgdb_attached && 3011 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 3012 iobase == comkgdbregs.cr_iobase) 3013 help = comkgdbregs.cr_ioh; 3014 #endif 3015 else 3016 return (0); 3017 3018 if (ioh) 3019 *ioh = help; 3020 return (1); 3021 } 3022 3023 /* 3024 * this routine exists to serve as a shutdown hook for systems that 3025 * have firmware which doesn't interact properly with a com device in 3026 * FIFO mode. 3027 */ 3028 bool 3029 com_cleanup(device_t self, int how) 3030 { 3031 struct com_softc *sc = device_private(self); 3032 3033 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 3034 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 3035 3036 return true; 3037 } 3038 3039 bool 3040 com_suspend(device_t self, const pmf_qual_t *qual) 3041 { 3042 struct com_softc *sc = device_private(self); 3043 3044 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 3045 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 3046 3047 return true; 3048 } 3049 3050 bool 3051 com_resume(device_t self, const pmf_qual_t *qual) 3052 { 3053 struct com_softc *sc = device_private(self); 3054 3055 com_mutex_enter(sc); 3056 com_loadchannelregs(sc); 3057 com_mutex_exit(sc); 3058 3059 return true; 3060 } 3061
Indexes created Sun Feb 22 16:20:20 UTC 2026