1 /************************************************************************** 2 3 Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 4 Copyright 2002 David Dawes 5 6 All Rights Reserved. 7 8 Permission is hereby granted, free of charge, to any person obtaining a 9 copy of this software and associated documentation files (the 10 "Software"), to deal in the Software without restriction, including 11 without limitation the rights to use, copy, modify, merge, publish, 12 distribute, sub license, and/or sell copies of the Software, and to 13 permit persons to whom the Software is furnished to do so, subject to 14 the following conditions: 15 16 The above copyright notice and this permission notice (including the 17 next paragraph) shall be included in all copies or substantial portions 18 of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 24 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28 **************************************************************************/ 29 30 /* 31 * Authors: 32 * Keith Whitwell <keith (at) tungstengraphics.com> 33 * David Dawes <dawes (at) xfree86.org> 34 * 35 */ 36 37 #if 0 38 #define I830DEBUG 39 #endif 40 41 #include <stdint.h> 42 43 #ifndef REMAP_RESERVED 44 #define REMAP_RESERVED 0 45 #endif 46 47 #ifndef _I830_H_ 48 #define _I830_H_ 49 50 #include "xorg-server.h" 51 #include "xf86_OSproc.h" 52 #include "compiler.h" 53 #include "xf86PciInfo.h" 54 #include "xf86Pci.h" 55 #include "i810_reg.h" 56 #include "xf86Cursor.h" 57 #include "xf86xv.h" 58 #include "vgaHW.h" 59 #include "xf86Crtc.h" 60 #include "xf86RandR12.h" 61 62 #include "xorg-server.h" 63 #include <pciaccess.h> 64 65 #include "xf86drm.h" 66 #include "sarea.h" 67 #define _XF86DRI_SERVER_ 68 #include "dri.h" 69 #include "GL/glxint.h" 70 #include "i830_dri.h" 71 #include "intel_bufmgr.h" 72 #include "i915_drm.h" 73 74 #include "uxa.h" 75 Bool i830_uxa_init(ScreenPtr pScreen); 76 void i830_uxa_create_screen_resources(ScreenPtr pScreen); 77 void i830_uxa_block_handler (ScreenPtr pScreen); 78 Bool i830_get_aperture_space(ScrnInfoPtr pScrn, drm_intel_bo **bo_table, 79 int num_bos); 80 81 dri_bo *i830_get_pixmap_bo (PixmapPtr pixmap); 82 void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo *bo); 83 84 typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr; 85 86 #include "common.h" 87 #include "i830_sdvo.h" 88 #include "i2c_vid.h" 89 90 #ifdef XvMCExtension 91 #ifdef ENABLE_XVMC 92 #define INTEL_XVMC 1 93 #endif 94 #endif 95 96 #define ALWAYS_SYNC 0 97 #define ALWAYS_FLUSH 0 98 99 typedef struct _I830Rec *I830Ptr; 100 101 typedef void (*I830WriteIndexedByteFunc)(I830Ptr pI830, IOADDRESS addr, 102 uint8_t index, uint8_t value); 103 typedef uint8_t(*I830ReadIndexedByteFunc)(I830Ptr pI830, IOADDRESS addr, 104 uint8_t index); 105 typedef void (*I830WriteByteFunc)(I830Ptr pI830, IOADDRESS addr, 106 uint8_t value); 107 typedef uint8_t(*I830ReadByteFunc)(I830Ptr pI830, IOADDRESS addr); 108 109 enum tile_format { 110 TILE_NONE, 111 TILE_XMAJOR, 112 TILE_YMAJOR 113 }; 114 115 #define PITCH_NONE 0 116 117 /** Record of a linear allocation in the aperture. */ 118 typedef struct _i830_memory i830_memory; 119 struct _i830_memory { 120 /** Offset of the allocation in card VM */ 121 unsigned long offset; 122 /** End of the allocation in card VM */ 123 unsigned long end; 124 /** 125 * Requested size of the allocation: doesn't count padding. 126 * 127 * Any bound memory will cover offset to (offset + size). 128 */ 129 unsigned long size; 130 /** 131 * Allocated aperture size, taking into account padding to allow for 132 * tiling. 133 */ 134 unsigned long allocated_size; 135 /** 136 * Physical (or more properly, bus) address of the allocation. 137 * Only set if requested during allocation. 138 */ 139 uint64_t bus_addr; 140 /** AGP memory handle */ 141 int key; 142 /** 143 * Whether or not the AGP memory (if any) is currently bound. 144 */ 145 Bool bound; 146 /** 147 * Offset that the AGP-allocated memory (if any) is to be bound to. 148 * 149 * This is either @offset or pI830->stolen_size 150 */ 151 unsigned long agp_offset; 152 153 enum tile_format tiling; 154 /** 155 * Index of the fence register representing the tiled surface, when 156 * bound. 157 */ 158 int fence_nr; 159 /** Pitch value in bytes for tiled surfaces */ 160 unsigned int pitch; 161 162 /** Description of the allocation, for logging */ 163 char *name; 164 165 /** @{ 166 * Memory allocator linked list pointers 167 */ 168 i830_memory *next; 169 i830_memory *prev; 170 /** @} */ 171 172 dri_bo *bo; 173 uint32_t alignment; 174 uint32_t gem_name; 175 Bool lifetime_fixed_offset; 176 }; 177 178 typedef struct { 179 int tail_mask; 180 i830_memory *mem; 181 unsigned char *virtual_start; 182 int head; 183 int tail; 184 int space; 185 } I830RingBuffer; 186 187 /* store information about an Ixxx DVO */ 188 /* The i830->i865 use multiple DVOs with multiple i2cs */ 189 /* the i915, i945 have a single sDVO i2c bus - which is different */ 190 #define MAX_OUTPUTS 6 191 192 #define I830_I2C_BUS_DVO 1 193 #define I830_I2C_BUS_SDVO 2 194 195 /* these are outputs from the chip - integrated only 196 external chips are via DVO or SDVO output */ 197 #define I830_OUTPUT_UNUSED 0 198 #define I830_OUTPUT_ANALOG 1 199 #define I830_OUTPUT_DVO_TMDS 2 200 #define I830_OUTPUT_DVO_LVDS 3 201 #define I830_OUTPUT_DVO_TVOUT 4 202 #define I830_OUTPUT_SDVO 5 203 #define I830_OUTPUT_LVDS 6 204 #define I830_OUTPUT_TVOUT 7 205 #define I830_OUTPUT_HDMI 8 206 207 struct _I830DVODriver { 208 int type; 209 char *modulename; 210 char *fntablename; 211 unsigned int dvo_reg; 212 uint32_t gpio; 213 int address; 214 I830I2CVidOutputRec *vid_rec; 215 void *dev_priv; 216 pointer modhandle; 217 }; 218 219 typedef struct _I830CrtcPrivateRec { 220 int pipe; 221 int plane; 222 223 Bool enabled; 224 225 int dpms_mode; 226 227 int x, y; 228 229 /* Lookup table values to be set when the CRTC is enabled */ 230 uint8_t lut_r[256], lut_g[256], lut_b[256]; 231 232 i830_memory *rotate_mem; 233 /* Card virtual address of the cursor */ 234 unsigned long cursor_offset; 235 unsigned long cursor_argb_offset; 236 /* Physical or virtual addresses of the cursor for setting in the cursor 237 * registers. 238 */ 239 uint64_t cursor_addr; 240 unsigned long cursor_argb_addr; 241 Bool cursor_is_argb; 242 } I830CrtcPrivateRec, *I830CrtcPrivatePtr; 243 244 #define I830CrtcPrivate(c) ((I830CrtcPrivatePtr) (c)->driver_private) 245 246 typedef struct _I830OutputPrivateRec { 247 int type; 248 I2CBusPtr pI2CBus; 249 I2CBusPtr pDDCBus; 250 struct _I830DVODriver *i2c_drv; 251 Bool load_detect_temp; 252 Bool needs_tv_clock; 253 uint32_t lvds_bits; 254 int pipe_mask; 255 int clone_mask; 256 /** Output-private structure. Should replace i2c_drv */ 257 void *dev_priv; 258 } I830OutputPrivateRec, *I830OutputPrivatePtr; 259 260 #define I830OutputPrivate(o) ((I830OutputPrivatePtr) (o)->driver_private) 261 262 /** enumeration of 3d consumers so some can maintain invariant state. */ 263 enum last_3d { 264 LAST_3D_OTHER, 265 LAST_3D_VIDEO, 266 LAST_3D_RENDER, 267 LAST_3D_ROTATION 268 }; 269 270 /* 271 * Backlight control has some unfortunate properties: 272 * - many machines won't give us brightness change notifications 273 * o brightness hotkeys 274 * o events like AC plug/unplug (can be controlled via _DOS setting) 275 * o ambient light sensor triggered changes 276 * - some machines use the so-called "legacy" backlight interface 277 * o resulting brightness is a combo of LBB and PWM values 278 * o LBB sits in config space 279 * - some machines have ACPI methods for changing brightness 280 * o one of the few ways the X server and firmware can stay in sync 281 * - new machines have the IGD OpRegion interface available 282 * o a reliable way of keeping the firmware and X in sync 283 * 284 * So the real problem is on machines where ACPI or OpRegion methods aren't 285 * available. In that case, problems can occur: 286 * 1) the BIOS and X will have different ideas of what the brightness is, 287 * leading to unexpected results when the brightness is increased or 288 * decreased via hotkey or X protocol 289 * 2) unless X takes the legacy register into account, machines using it 290 * may prevent X from raising the brightness above 0 if the firmware 291 * set LBB to 0 292 * Given these problems, we provide the user with a selection of methods, 293 * so they can choose an ideal one for their platform (assuming our quirk 294 * code picks the wrong one). 295 * 296 * Four different backlight control methods are available: 297 * BCM_NATIVE: only ever touch the native backlight control registers 298 * This method may be susceptible to problem (2) above if the firmware 299 * modifies the legacy registers. 300 * BCM_LEGACY: only ever touch the legacy backlight control registers 301 * This method may be susceptible to problem (1) above if the firmware 302 * also modifies the legacy registers. 303 * BCM_COMBO: try to use both sets 304 * In this case, the driver will try to modify both sets of registers 305 * if needed. To avoid problem (2) above it may set the LBB register 306 * to a non-zero value if the brightness is to be increased. It's still 307 * susceptible to problem (1), but to a lesser extent than the LEGACY only 308 * method. 309 * BCM_KERNEL: use kernel methods for controlling the backlight 310 * This is only available on some platforms, but where present this can 311 * provide the best user experience. 312 */ 313 314 enum backlight_control { 315 BCM_NATIVE = 0, 316 BCM_LEGACY, 317 BCM_COMBO, 318 BCM_KERNEL, 319 }; 320 321 enum dri_type { 322 DRI_DISABLED, 323 DRI_NONE, 324 DRI_DRI2 325 }; 326 struct sdvo_device_mapping { 327 uint8_t dvo_port; 328 uint8_t slave_addr; 329 uint8_t dvo_wiring; 330 uint8_t initialized; 331 }; 332 typedef struct _I830Rec { 333 unsigned char *MMIOBase; 334 unsigned char *GTTBase; 335 unsigned char *FbBase; 336 int cpp; 337 338 unsigned int bufferOffset; /* for I830SelectBuffer */ 339 340 /* These are set in PreInit and never changed. */ 341 long FbMapSize; 342 long GTTMapSize; 343 344 /** 345 * Linked list of video memory allocations. The head and tail are 346 * dummy entries that bound the allocation area. 347 */ 348 i830_memory *memory_list; 349 /** Linked list of buffer object memory allocations */ 350 i830_memory *bo_list; 351 long stolen_size; /**< bytes of pre-bound stolen memory */ 352 int gtt_acquired; /**< whether we currently own the AGP */ 353 354 i830_memory *front_buffer; 355 i830_memory *compressed_front_buffer; 356 i830_memory *compressed_ll_buffer; 357 /* One big buffer for all cursors for kernels that support this */ 358 i830_memory *cursor_mem; 359 /* separate small buffers for kernels that support this */ 360 i830_memory *cursor_mem_classic[2]; 361 i830_memory *cursor_mem_argb[2]; 362 i830_memory *fake_bufmgr_mem; 363 364 /* Regions allocated either from the above pools, or from agpgart. */ 365 I830RingBuffer ring; 366 367 /** Number of bytes being emitted in the current BEGIN_LP_RING */ 368 unsigned int ring_emitting; 369 /** Number of bytes that have been emitted in the current BEGIN_LP_RING */ 370 unsigned int ring_used; 371 /** Offset in the ring for the next DWORD emit */ 372 uint32_t ring_next; 373 374 dri_bufmgr *bufmgr; 375 376 uint8_t *batch_ptr; 377 /** Byte offset in batch_ptr for the next dword to be emitted. */ 378 unsigned int batch_used; 379 /** Position in batch_ptr at the start of the current BEGIN_BATCH */ 380 unsigned int batch_emit_start; 381 /** Number of bytes to be emitted in the current BEGIN_BATCH. */ 382 uint32_t batch_emitting; 383 dri_bo *batch_bo; 384 dri_bo *last_batch_bo; 385 /** Whether we're in a section of code that can't tolerate flushing */ 386 Bool in_batch_atomic; 387 /** Ending batch_used that was verified by i830_start_batch_atomic() */ 388 int batch_atomic_limit; 389 390 /* For Xvideo */ 391 i830_memory *overlay_regs; 392 void *offscreenImages; /**< remembered memory block for release */ 393 #ifdef INTEL_XVMC 394 /* For XvMC */ 395 Bool XvMCEnabled; 396 #endif 397 398 XF86ModReqInfo shadowReq; /* to test for later libshadow */ 399 400 CreateScreenResourcesProcPtr CreateScreenResources; 401 402 i830_memory *power_context; 403 404 i830_memory *memory_manager; /**< DRI memory manager aperture */ 405 406 Bool have_gem; 407 Bool need_mi_flush; 408 409 Bool tiling; 410 Bool fb_compression; 411 Bool swapbuffers_wait; 412 413 Bool CursorNeedsPhysical; 414 415 int Chipset; 416 unsigned long LinearAddr; 417 unsigned long MMIOAddr; 418 unsigned int MMIOSize; 419 IOADDRESS ioBase; 420 EntityInfoPtr pEnt; 421 struct pci_device *PciInfo; 422 uint8_t variant; 423 424 unsigned int BR[20]; 425 426 Bool fence_used[FENCE_NEW_NR]; 427 428 CloseScreenProcPtr CloseScreen; 429 430 void (*batch_flush_notify)(ScrnInfoPtr pScrn); 431 432 uxa_driver_t *uxa_driver; 433 Bool need_flush; 434 PixmapPtr pSrcPixmap; 435 int accel_pixmap_pitch_alignment; 436 int accel_pixmap_offset_alignment; 437 int accel_max_x; 438 int accel_max_y; 439 int max_gtt_map_size; 440 441 I830WriteIndexedByteFunc writeControl; 442 I830ReadIndexedByteFunc readControl; 443 I830WriteByteFunc writeStandard; 444 I830ReadByteFunc readStandard; 445 446 Bool XvDisabled; /* Xv disabled in PreInit. */ 447 Bool XvEnabled; /* Xv enabled for this generation. */ 448 Bool XvPreferOverlay; 449 450 int colorKey; 451 XF86VideoAdaptorPtr adaptor; 452 ScreenBlockHandlerProcPtr BlockHandler; 453 Bool overlayOn; 454 455 struct { 456 drm_intel_bo *gen4_vs_bo; 457 drm_intel_bo *gen4_sf_bo; 458 drm_intel_bo *gen4_wm_packed_bo; 459 drm_intel_bo *gen4_wm_planar_bo; 460 drm_intel_bo *gen4_cc_bo; 461 drm_intel_bo *gen4_cc_vp_bo; 462 drm_intel_bo *gen4_sampler_bo; 463 drm_intel_bo *gen4_sip_kernel_bo; 464 } video; 465 466 /* Render accel state */ 467 float scale_units[2][2]; 468 /** Transform pointers for src/mask, or NULL if identity */ 469 PictTransform *transform[2]; 470 float dst_coord_adjust; 471 float src_coord_adjust; 472 float mask_coord_adjust; 473 474 /* i830 render accel state */ 475 PixmapPtr render_src, render_mask, render_dst; 476 PicturePtr render_src_picture, render_mask_picture, render_dst_picture; 477 uint32_t render_dst_format; 478 Bool needs_render_state_emit; 479 uint32_t cblend, ablend, s8_blendctl; 480 481 /* i915 render accel state */ 482 uint32_t mapstate[6]; 483 uint32_t samplerstate[6]; 484 485 struct { 486 int op; 487 uint32_t dst_format; 488 Bool needs_emit; 489 } i915_render_state; 490 491 /* 965 render acceleration state */ 492 struct gen4_render_state *gen4_render_state; 493 494 enum dri_type directRenderingType; /* DRI enabled this generation. */ 495 496 Bool directRenderingOpen; 497 int drmSubFD; 498 char deviceName[64]; 499 500 /* Broken-out options. */ 501 OptionInfoPtr Options; 502 503 Bool lvds_24_bit_mode; 504 Bool lvds_use_ssc; 505 int lvds_ssc_freq; /* in MHz */ 506 Bool lvds_dither; 507 DisplayModePtr lvds_fixed_mode; 508 DisplayModePtr sdvo_lvds_fixed_mode; 509 Bool skip_panel_detect; 510 Bool integrated_lvds; /* LVDS config from driver feature BDB */ 511 512 Bool tv_present; /* TV connector present (from VBIOS) */ 513 514 /* Driver phase/state information */ 515 Bool preinit; 516 Bool starting; 517 Bool closing; 518 Bool suspended; 519 Bool leaving; 520 521 unsigned int SaveGeneration; 522 523 OsTimerPtr devicesTimer; 524 525 int ddc2; 526 527 enum backlight_control backlight_control_method; 528 529 uint32_t saveDSPARB; 530 uint32_t saveDSPACNTR; 531 uint32_t saveDSPBCNTR; 532 uint32_t savePIPEACONF; 533 uint32_t savePIPEBCONF; 534 uint32_t savePIPEASRC; 535 uint32_t savePIPEBSRC; 536 uint32_t saveFPA0; 537 uint32_t saveFPA1; 538 uint32_t saveDPLL_A; 539 uint32_t saveDPLL_A_MD; 540 uint32_t saveHTOTAL_A; 541 uint32_t saveHBLANK_A; 542 uint32_t saveHSYNC_A; 543 uint32_t saveVTOTAL_A; 544 uint32_t saveVBLANK_A; 545 uint32_t saveVSYNC_A; 546 uint32_t saveBCLRPAT_A; 547 uint32_t saveDSPASTRIDE; 548 uint32_t saveDSPASIZE; 549 uint32_t saveDSPAPOS; 550 uint32_t saveDSPABASE; 551 uint32_t saveDSPASURF; 552 uint32_t saveDSPATILEOFF; 553 uint32_t saveFPB0; 554 uint32_t saveFPB1; 555 uint32_t saveDPLL_B; 556 uint32_t saveDPLL_B_MD; 557 uint32_t saveHTOTAL_B; 558 uint32_t saveHBLANK_B; 559 uint32_t saveHSYNC_B; 560 uint32_t saveVTOTAL_B; 561 uint32_t saveVBLANK_B; 562 uint32_t saveVSYNC_B; 563 uint32_t saveBCLRPAT_B; 564 uint32_t saveDSPBSTRIDE; 565 uint32_t saveDSPBSIZE; 566 uint32_t saveDSPBPOS; 567 uint32_t saveDSPBBASE; 568 uint32_t saveDSPBSURF; 569 uint32_t saveDSPBTILEOFF; 570 uint32_t saveVCLK_DIVISOR_VGA0; 571 uint32_t saveVCLK_DIVISOR_VGA1; 572 uint32_t saveVCLK_POST_DIV; 573 uint32_t saveVGACNTRL; 574 uint32_t saveCURSOR_A_CONTROL; 575 uint32_t saveCURSOR_A_BASE; 576 uint32_t saveCURSOR_A_POSITION; 577 uint32_t saveCURSOR_B_CONTROL; 578 uint32_t saveCURSOR_B_BASE; 579 uint32_t saveCURSOR_B_POSITION; 580 uint32_t saveADPA; 581 uint32_t saveLVDS; 582 uint32_t saveDVOA; 583 uint32_t saveDVOB; 584 uint32_t saveDVOC; 585 uint32_t savePP_ON; 586 uint32_t savePP_OFF; 587 uint32_t savePP_CONTROL; 588 uint32_t savePP_DIVISOR; 589 uint32_t savePFIT_CONTROL; 590 uint32_t savePaletteA[256]; 591 uint32_t savePaletteB[256]; 592 uint32_t saveSWF[17]; 593 uint32_t saveBLC_PWM_CTL; 594 uint32_t saveBLC_PWM_CTL2; 595 uint32_t saveFBC_CFB_BASE; 596 uint32_t saveFBC_LL_BASE; 597 uint32_t saveFBC_CONTROL2; 598 uint32_t saveFBC_CONTROL; 599 uint32_t saveFBC_FENCE_OFF; 600 uint32_t saveRENCLK_GATE_D1; 601 uint32_t saveRENCLK_GATE_D2; 602 uint32_t saveDSPCLK_GATE_D; 603 uint32_t saveRAMCLK_GATE_D; 604 uint32_t savePWRCTXA; 605 606 enum last_3d last_3d; 607 608 Bool use_drm_mode; 609 Bool kernel_exec_fencing; 610 611 /** Enables logging of debug output related to mode switching. */ 612 Bool debug_modes; 613 unsigned int quirk_flag; 614 615 /** User option to print acceleration fallback info to the server log. */ 616 Bool fallback_debug; 617 struct sdvo_device_mapping sdvo_mappings[2]; 618 } I830Rec; 619 620 #define I830PTR(p) ((I830Ptr)((p)->driverPrivate)) 621 622 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) 623 #define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) 624 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 625 626 #define I830_SELECT_FRONT 0 627 #define I830_SELECT_BACK 1 628 #define I830_SELECT_DEPTH 2 629 #define I830_SELECT_THIRD 3 630 631 unsigned long intel_get_pixmap_offset(PixmapPtr pPix); 632 unsigned long intel_get_pixmap_pitch(PixmapPtr pPix); 633 634 /* Batchbuffer support macros and functions */ 635 #include "i830_batchbuffer.h" 636 637 /* I830 specific functions */ 638 extern int I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis); 639 extern void I830SetPIOAccess(I830Ptr pI830); 640 extern void I830SetMMIOAccess(I830Ptr pI830); 641 extern void I830Sync(ScrnInfoPtr pScrn); 642 extern void I830InitHWCursor(ScrnInfoPtr pScrn); 643 extern void I830SetPipeCursor (xf86CrtcPtr crtc, Bool force); 644 extern Bool I830CursorInit(ScreenPtr pScreen); 645 extern void IntelEmitInvarientState(ScrnInfoPtr pScrn); 646 extern void I830EmitInvarientState(ScrnInfoPtr pScrn); 647 extern void I915EmitInvarientState(ScrnInfoPtr pScrn); 648 extern Bool I830SelectBuffer(ScrnInfoPtr pScrn, int buffer); 649 void i830_update_cursor_offsets(ScrnInfoPtr pScrn); 650 651 /* CRTC-based cursor functions */ 652 void 653 i830_crtc_load_cursor_image (xf86CrtcPtr crtc, unsigned char *src); 654 655 #ifdef ARGB_CURSOR 656 void 657 i830_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image); 658 #endif 659 660 void 661 i830_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y); 662 663 void 664 i830_crtc_show_cursor (xf86CrtcPtr crtc); 665 666 void 667 i830_crtc_hide_cursor (xf86CrtcPtr crtc); 668 669 void 670 i830_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg); 671 672 extern void i830_refresh_ring(ScrnInfoPtr pScrn); 673 extern void I830EmitFlush(ScrnInfoPtr pScrn); 674 675 extern void I830InitVideo(ScreenPtr pScreen); 676 extern void i830_crtc_dpms_video(xf86CrtcPtr crtc, Bool on); 677 extern xf86CrtcPtr i830_covering_crtc (ScrnInfoPtr pScrn, BoxPtr box, 678 xf86CrtcPtr desired, 679 BoxPtr crtc_box_ret); 680 int 681 i830_crtc_pipe (xf86CrtcPtr crtc); 682 683 extern xf86CrtcPtr i830_pipe_to_crtc(ScrnInfoPtr pScrn, int pipe); 684 685 Bool 686 i830_pipe_a_require_activate (ScrnInfoPtr scrn); 687 688 void 689 i830_pipe_a_require_deactivate (ScrnInfoPtr scrn); 690 691 Bool I830DRI2ScreenInit(ScreenPtr pScreen); 692 void I830DRI2CloseScreen(ScreenPtr pScreen); 693 694 extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp); 695 extern int drmmode_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, xf86CrtcPtr crtc); 696 extern void drmmode_closefb(ScrnInfoPtr scrn); 697 extern int drmmode_output_dpms_status(xf86OutputPtr output); 698 void 699 drmmode_crtc_set_cursor_bo(xf86CrtcPtr crtc, dri_bo *cursor); 700 701 extern Bool i830_crtc_on(xf86CrtcPtr crtc); 702 extern int i830_crtc_to_pipe(xf86CrtcPtr crtc); 703 extern Bool I830AccelInit(ScreenPtr pScreen); 704 extern void I830SetupForScreenToScreenCopy(ScrnInfoPtr pScrn, int xdir, 705 int ydir, int rop, 706 unsigned int planemask, 707 int trans_color); 708 extern void I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int srcX, 709 int srcY, int dstX, int dstY, 710 int w, int h); 711 extern void I830SetupForSolidFill(ScrnInfoPtr pScrn, int color, int rop, 712 unsigned int planemask); 713 extern void I830SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, 714 int w, int h); 715 716 Bool i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size); 717 void i830_allocator_fini(ScrnInfoPtr pScrn); 718 i830_memory * i830_allocate_memory(ScrnInfoPtr pScrn, const char *name, 719 unsigned long size, unsigned long pitch, 720 unsigned long alignment, int flags, 721 enum tile_format tile_format); 722 void i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, 723 const char *prefix); 724 void i830_reset_allocations(ScrnInfoPtr pScrn); 725 void i830_free_3d_memory(ScrnInfoPtr pScrn); 726 void i830_free_memory(ScrnInfoPtr pScrn, i830_memory *mem); 727 extern long I830CheckAvailableMemory(ScrnInfoPtr pScrn); 728 Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn); 729 Bool i830_allocate_pwrctx(ScrnInfoPtr pScrn); 730 Bool i830_allocate_3d_memory(ScrnInfoPtr pScrn); 731 void i830_init_bufmgr(ScrnInfoPtr pScrn); 732 #ifdef INTEL_XVMC 733 Bool i830_allocate_xvmc_buffer(ScrnInfoPtr pScrn, const char *name, 734 i830_memory **buffer, unsigned long size, int flags); 735 void i830_free_xvmc_buffer(ScrnInfoPtr pScrn, i830_memory *buffer); 736 #endif 737 extern uint32_t i830_create_new_fb(ScrnInfoPtr pScrn, int width, int height, 738 int *pitch); 739 740 Bool 741 i830_tiled_width(I830Ptr i830, int *width, int cpp); 742 743 int 744 i830_pad_drawable_width(int width, int cpp); 745 746 747 extern Bool I830I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, 748 char *name); 749 750 /* i830_display.c */ 751 Bool 752 i830PipeHasType (xf86CrtcPtr crtc, int type); 753 754 /* i830_crt.c */ 755 void i830_crt_init(ScrnInfoPtr pScrn); 756 757 /* i830_dvo.c */ 758 void i830_dvo_init(ScrnInfoPtr pScrn); 759 760 /* i830_hdmi.c */ 761 void i830_hdmi_init(ScrnInfoPtr pScrn, int output_reg); 762 763 /* i830_lvds.c */ 764 void i830_lvds_init(ScrnInfoPtr pScrn); 765 766 /* i830_memory.c */ 767 Bool i830_bind_all_memory(ScrnInfoPtr pScrn); 768 Bool i830_unbind_all_memory(ScrnInfoPtr pScrn); 769 unsigned long i830_get_fence_size(I830Ptr pI830, unsigned long size); 770 unsigned long i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch, int format); 771 void i830_set_max_gtt_map_size(ScrnInfoPtr pScrn); 772 773 Bool I830BindAGPMemory(ScrnInfoPtr pScrn); 774 Bool I830UnbindAGPMemory(ScrnInfoPtr pScrn); 775 776 i830_memory * 777 i830_allocate_framebuffer(ScrnInfoPtr pScrn); 778 779 /* i830_modes.c */ 780 DisplayModePtr i830_ddc_get_modes(xf86OutputPtr output); 781 782 /* i830_tv.c */ 783 void i830_tv_init(ScrnInfoPtr pScrn); 784 785 /* i830_render.c */ 786 Bool i830_check_composite(int op, PicturePtr pSrc, PicturePtr pMask, 787 PicturePtr pDst); 788 Bool i830_prepare_composite(int op, PicturePtr pSrc, PicturePtr pMask, 789 PicturePtr pDst, PixmapPtr pSrcPixmap, 790 PixmapPtr pMaskPixmap, PixmapPtr pDstPixmap); 791 Bool 792 i830_transform_is_affine (PictTransformPtr t); 793 794 void i830_composite(PixmapPtr pDst, int srcX, int srcY, 795 int maskX, int maskY, int dstX, int dstY, int w, int h); 796 void i830_done_composite(PixmapPtr pDst); 797 /* i915_render.c */ 798 Bool i915_check_composite(int op, PicturePtr pSrc, PicturePtr pMask, 799 PicturePtr pDst); 800 Bool i915_prepare_composite(int op, PicturePtr pSrc, PicturePtr pMask, 801 PicturePtr pDst, PixmapPtr pSrcPixmap, 802 PixmapPtr pMaskPixmap, PixmapPtr pDstPixmap); 803 void i915_composite(PixmapPtr pDst, int srcX, int srcY, 804 int maskX, int maskY, int dstX, int dstY, int w, int h); 805 void i915_batch_flush_notify(ScrnInfoPtr pScrn); 806 void i830_batch_flush_notify(ScrnInfoPtr scrn); 807 /* i965_render.c */ 808 unsigned int gen4_render_state_size(ScrnInfoPtr pScrn); 809 void gen4_render_state_init(ScrnInfoPtr pScrn); 810 void gen4_render_state_cleanup(ScrnInfoPtr pScrn); 811 Bool i965_check_composite(int op, PicturePtr pSrc, PicturePtr pMask, 812 PicturePtr pDst); 813 Bool i965_prepare_composite(int op, PicturePtr pSrc, PicturePtr pMask, 814 PicturePtr pDst, PixmapPtr pSrcPixmap, 815 PixmapPtr pMaskPixmap, PixmapPtr pDstPixmap); 816 void i965_composite(PixmapPtr pDst, int srcX, int srcY, 817 int maskX, int maskY, int dstX, int dstY, int w, int h); 818 819 void 820 i965_batch_flush_notify(ScrnInfoPtr pScrn); 821 822 Bool 823 i830_get_transformed_coordinates(int x, int y, PictTransformPtr transform, 824 float *x_out, float *y_out); 825 826 Bool 827 i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, 828 float *x_out, float *y_out, float *z_out); 829 830 void i830_enter_render(ScrnInfoPtr); 831 832 static inline void 833 i830_wait_ring_idle(ScrnInfoPtr pScrn) 834 { 835 I830Ptr pI830 = I830PTR(pScrn); 836 837 I830WaitLpRing(pScrn, pI830->ring.mem->size - 8, 0); 838 } 839 840 static inline int i830_fb_compression_supported(I830Ptr pI830) 841 { 842 if (!IS_MOBILE(pI830)) 843 return FALSE; 844 if (IS_I810(pI830) || IS_I815(pI830) || IS_I830(pI830)) 845 return FALSE; 846 if (IS_IGD(pI830)) 847 return FALSE; 848 if (IS_IGDNG(pI830)) 849 return FALSE; 850 /* fbc depends on tiled surface. 851 */ 852 if (!pI830->tiling) 853 return FALSE; 854 /* We have not gotten FBC to work consistently on 965GM. Our best 855 * working theory right now is that FBC simply isn't reliable on 856 * that device. See this bug report for more details: 857 * https://bugs.freedesktop.org/show_bug.cgi?id=16257 858 */ 859 if (IS_I965GM(pI830)) 860 return FALSE; 861 return TRUE; 862 } 863 864 #define I830FALLBACK(s, arg...) \ 865 do { \ 866 if (I830PTR(pScrn)->fallback_debug) { \ 867 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 868 "fallback: " s "\n", ##arg); \ 869 } \ 870 return FALSE; \ 871 } while(0) 872 873 Bool i830_pixmap_tiled(PixmapPtr p); 874 875 #define i830_exa_check_pitch_2d(p) do {\ 876 uint32_t pitch = intel_get_pixmap_pitch(p);\ 877 if (pitch > KB(32)) I830FALLBACK("pitch exceeds 2d limit 32K\n");\ 878 } while(0) 879 880 /* For pre-965 chip only, as they have 8KB limit for 3D */ 881 #define i830_exa_check_pitch_3d(p) do {\ 882 uint32_t pitch = intel_get_pixmap_pitch(p);\ 883 if (pitch > KB(8)) I830FALLBACK("pitch exceeds 3d limit 8K\n");\ 884 } while(0) 885 886 /** 887 * Little wrapper around drm_intel_bo_reloc to return the initial value you 888 * should stuff into the relocation entry. 889 * 890 * If only we'd done this before settling on the library API. 891 */ 892 static inline uint32_t 893 intel_emit_reloc(drm_intel_bo *bo, uint32_t offset, 894 drm_intel_bo *target_bo, uint32_t target_offset, 895 uint32_t read_domains, uint32_t write_domain) 896 { 897 drm_intel_bo_emit_reloc(bo, offset, target_bo, target_offset, 898 read_domains, write_domain); 899 900 return target_bo->offset + target_offset; 901 } 902 903 static inline drm_intel_bo * 904 intel_bo_alloc_for_data(ScrnInfoPtr scrn, const void *data, unsigned int size, 905 char *name) 906 { 907 I830Ptr pI830 = I830PTR(scrn); 908 drm_intel_bo *bo; 909 910 bo = drm_intel_bo_alloc(pI830->bufmgr, name, size, 4096); 911 if (!bo) 912 return NULL; 913 drm_intel_bo_subdata(bo, 0, size, data); 914 915 return bo; 916 } 917 918 extern const int I830PatternROP[16]; 919 extern const int I830CopyROP[16]; 920 921 /* Flags for memory allocation function */ 922 #define NEED_PHYSICAL_ADDR 0x00000001 923 #define ALIGN_BOTH_ENDS 0x00000002 924 #define NEED_NON_STOLEN 0x00000004 925 #define NEED_LIFETIME_FIXED 0x00000008 926 #define ALLOW_SHARING 0x00000010 927 #define DISABLE_REUSE 0x00000020 928 929 /* Chipset registers for VIDEO BIOS memory RW access */ 930 #define _855_DRAM_RW_CONTROL 0x58 931 #define _845_DRAM_RW_CONTROL 0x90 932 #define DRAM_WRITE 0x33330000 933 934 /* quirk flag definition */ 935 #define QUIRK_IGNORE_TV 0x00000001 936 #define QUIRK_IGNORE_LVDS 0x00000002 937 #define QUIRK_IGNORE_MACMINI_LVDS 0x00000004 938 #define QUIRK_PIPEA_FORCE 0x00000008 939 #define QUIRK_IVCH_NEED_DVOB 0x00000010 940 #define QUIRK_RESET_MODES 0x00000020 941 #define QUIRK_PFIT_SAFE 0x00000040 942 #define QUIRK_IGNORE_CRT 0x00000080 943 #define QUIRK_BROKEN_ACPI_LID 0x00000100 944 extern void i830_fixup_devices(ScrnInfoPtr); 945 946 /** 947 * Hints to CreatePixmap to tell the driver how the pixmap is going to be 948 * used. 949 * 950 * Compare to CREATE_PIXMAP_USAGE_* in the server. 951 */ 952 enum { 953 INTEL_CREATE_PIXMAP_TILING_X = 0x10000000, 954 INTEL_CREATE_PIXMAP_TILING_Y, 955 }; 956 957 #if (ALWAYS_FLUSH | ALWAYS_SYNC) 958 void 959 i830_debug_sync(ScrnInfoPtr scrn); 960 #else 961 static inline void 962 i830_debug_sync(ScrnInfoPtr scrn) 963 { 964 } 965 #endif 966 967 static inline PixmapPtr 968 get_drawable_pixmap(DrawablePtr drawable) 969 { 970 ScreenPtr screen = drawable->pScreen; 971 972 if (drawable->type == DRAWABLE_PIXMAP) 973 return (PixmapPtr)drawable; 974 else 975 return screen->GetWindowPixmap((WindowPtr)drawable); 976 } 977 978 static inline Bool 979 pixmap_is_scanout(PixmapPtr pixmap) 980 { 981 ScreenPtr screen = pixmap->drawable.pScreen; 982 983 return pixmap == screen->GetScreenPixmap(screen); 984 } 985 986 #endif /* _I830_H_ */ 987
Indexes created Sun Jul 05 00:25:41 UTC 2026