| /src/sys/arch/arm/rockchip/ |
| rk3399_pmucru.c | 179 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); local in function:rk3399_pmucru_pll_get_rate
184 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);
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| rk_cru_pll.c | 63 #define PLL_WRITE_MASK 0xffff0000 /* for CON0 and CON1 */
65 /* RK3288 CON0 */
105 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); local in function:rk_cru_pll_get_rate
115 const u_int nr = __SHIFTOUT(con0, RK3288_CLKR) + 1;
116 const u_int no = __SHIFTOUT(con0, RK3288_CLKOD) + 1;
123 const uint64_t m = __SHIFTOUT(con0, RK3588_PLLCON0_M);
136 const u_int postdiv1 = __SHIFTOUT(con0, PLL_POSTDIV1);
137 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);
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| rk3399_cru.c | 251 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); local in function:rk3399_cru_pll_get_rate
256 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);
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