1 /* $NetBSD: scr.c,v 1.38 2024/03/06 20:02:24 andvar Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** 39 ** FACILITY: 40 ** 41 ** Driver for smart card 42 ** 43 ** ABSTRACT: 44 ** 45 ** The driver provides access to a Smart Card for the DNARD. 46 ** 47 ** There is no Smart Card silicon. Several i/o pins 48 ** connect to the pads on the Smart Card, and the driver is 49 ** is responsible for driving the signals in accordance with 50 ** ISO 7816-3 (the Smart Card spec) 51 ** 52 ** This driver puts a high load on the system due to the need 53 ** to interrupt at a high rate (up to 50 kHz) during bit detection. 54 ** 55 ** 56 ** The driver is dived into the standard top half ioctl, and bottom 57 ** half interrupt. The interrupt is FIQ, which requires its own stack. 58 ** disable_interrupts and restore_interrupts must be used to protect from 59 ** a FIQ. Since splxxx functions do not use this, the bottom half cannot 60 ** use any standard functions (ie like wakeup, timeout, etc. 61 ** Thus the communication from the bottom half 62 ** to the top half uses a "done" bit called masterDone. This bit 63 ** is set by the master state machine when all bottom half work is 64 ** complete. The top half checks/sleeps on this masterDone bit. 65 ** 66 ** The FIQ is driven by Timer 2 (T2)in the sequoia. All times are 67 ** referenced to T2 counts. 68 ** 69 ** The bottom half is done as a several linked state machines. 70 ** The top level machine is the masterSM (ie master State Machine). This 71 ** machine calls mid level protocol machines, ie ATRSM (Answer To Reset 72 ** State Machine), t0SendSM (T=0 Send State Machine), and t0RecvSM (T=0 Recv 73 ** State Machine). These mid level protocol machines in turn call low level 74 ** bit-bashing machines, ie coldResetSM, t0SendByteSM, T0RecvByteSM. 75 ** 76 ** Smart Cards are driven in a command/response mode. Ie you issue a command 77 ** to the Smart Card and it responds. This command/response mode is reflected 78 ** in the structure of the driver. Ie the ioctl gets a command, it 79 ** gives it to the bottom half to execute and goes to sleep. The bottom half 80 ** executes the command and gets the response to from the card and then 81 ** notifies the top half that it has completed. Commands usually complete 82 ** in under a second. 83 ** 84 ** 85 ** 86 ** AUTHORS: 87 ** 88 ** E. J. Grohn 89 ** Digital Equipment Corporation. 90 ** 91 ** CREATION DATE: 92 ** 93 ** 27-July-97 94 ** 95 **-- 96 */ 97 98 /* 99 ** 100 ** INCLUDE FILES 101 ** 102 */ 103 104 #include <sys/cdefs.h> 105 __KERNEL_RCSID(0, "$NetBSD: scr.c,v 1.38 2024/03/06 20:02:24 andvar Exp $"); 106 107 #include "opt_ddb.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/ioctl.h> 112 /* #include <sys/select.h> */ 113 /* #include <sys/tty.h> */ 114 #include <sys/proc.h> 115 #include <sys/conf.h> 116 /* #include <sys/file.h> */ 117 /* #include <sys/uio.h> */ 118 #include <sys/kernel.h> 119 /* #include <sys/syslog.h> */ 120 #include <sys/types.h> 121 #include <sys/device.h> 122 #include <dev/isa/isavar.h> 123 #include <arm/cpufunc.h> 124 125 126 /* SCR_DEBUG is the master switch for turning on debugging */ 127 //#define SCR_DEBUG 1 128 #ifdef SCR_DEBUG 129 #define KERNEL_DEBUG 130 #ifdef DDB 131 #define DEBUGGER printf("file = %s, line = %d\n",__FILE__,__LINE__);Debugger() 132 #else 133 #define DEBUGGER panic("file = %s, line = %d",__FILE__,__LINE__); 134 #endif 135 #else 136 #define DEBUGGER 137 #endif 138 139 140 #include <machine/kerndebug.h> 141 //#include <machine/intr.h> 142 #include <dev/ic/i8253reg.h> 143 #include <shark/shark/hat.h> 144 #include <shark/shark/sequoia.h> 145 #include <machine/scrio.h> 146 147 149 150 151 /* 152 ** 153 ** MACRO DEFINITIONS 154 ** 155 */ 156 157 158 #define scr_lcr scr_cfcr 159 160 /* 161 ** Macro to extract the minor device number from the device Identifier 162 */ 163 #define SCRUNIT(x) (minor(x)) 164 165 /* 166 ** some macros to assist in debugging 167 */ 168 #ifdef SCR_DEBUG 169 #define KERNEL_DEBUG 170 #define ASSERT(f) do { if (!(f)) { DEBUGGER;} }while(0) 171 #define TOGGLE_TEST_PIN() scrToggleTestPin() 172 #define INVALID_STATE_CMD(sc,state,cmd) invalidStateCmd(sc,state,cmd,__LINE__); 173 #else 174 #define ASSERT(f) 175 #define TOGGLE_TEST_PIN() 176 //#define INVALID_STATE_CMD(sc,state,cmd) panic("scr: invalid state/cmd, sc = %X, state = %X, cmd = %X, line = %d",sc,state,cmd,__LINE__); 177 #define INVALID_STATE_CMD(sc,state,cmd) sc->bigTrouble = true; 178 179 #endif 180 181 182 /* 183 ** The first and last bytes of the debug control variables is reserved for 184 ** the standard KERN_DEBUG_xxx macros, so we can tailor the middle two bytes 185 */ 186 #define SCRPROBE_DEBUG_INFO 0x00000100 187 #define SCRATTACH_DEBUG_INFO 0x00000200 188 #define SCROPEN_DEBUG_INFO 0x00000400 189 #define SCRCLOSE_DEBUG_INFO 0x00000800 190 #define SCRREAD_DEBUG_INFO 0x00001000 191 #define SCRWRITE_DEBUG_INFO 0x00002000 192 #define SCRIOCTL_DEBUG_INFO 0x00004000 193 #define MASTER_SM_DEBUG_INFO 0x00008000 194 #define COLD_RESET_SM_DEBUG_INFO 0x00010000 195 #define ATR_SM_DEBUG_INFO 0x00020000 196 #define T0_RECV_BYTE_SM_DEBUG_INFO 0x00040000 197 #define T0_SEND_BYTE_SM_DEBUG_INFO 0x00080000 198 #define T0_RECV_SM_DEBUG_INFO 0x00100000 199 #define T0_SEND_SM_DEBUG_INFO 0x00200000 200 201 202 int scrdebug = //SCRPROBE_DEBUG_INFO | 203 //SCRATTACH_DEBUG_INFO | 204 //SCROPEN_DEBUG_INFO | 205 //SCRCLOSE_DEBUG_INFO | 206 //SCRREAD_DEBUG_INFO | 207 //SCRWRITE_DEBUG_INFO | 208 //SCRIOCTL_DEBUG_INFO | 209 //MASTER_SM_DEBUG_INFO | 210 //COLD_RESET_SM_DEBUG_INFO| 211 //ATR_SM_DEBUG_INFO | 212 //T0_RECV_BYTE_SM_DEBUG_INFO | 213 //T0_SEND_BYTE_SM_DEBUG_INFO | 214 //T0_RECV_SM_DEBUG_INFO | 215 //T0_SEND_SM_DEBUG_INFO | 216 0; 217 218 219 220 221 222 223 /* 224 ** the bottom half of the driver is done as several linked state machines 225 ** below are all the states of the machines, and the commands that are 226 ** sent to each machine 227 */ 228 229 /* commands to Master State Machine from ioctl */ 230 #define mcOn 0x0100 /* ioctl on */ 231 #define mcT0DataSend 0x0102 /* ioctl send */ 232 #define mcT0DataRecv 0x0103 /* ioctl recv */ 233 234 /* commands to Master State Machine from lower state machines */ 235 #define mcColdReset 0x0105 /* cold reset finished */ 236 #define mcATR 0x0106 /* ATR has finished */ 237 #define mcT0Send 0x0108 /* T0 send finished */ 238 #define mcT0Recv 0x010a /* T0 recv finished */ 239 240 /* states in Master state machine (ms = Master State) */ 241 #define msIdleOff 0x0200 /* in idle state, card powered off */ 242 #define msColdReset 0x0201 /* turning on power, clock, reset */ 243 #define msATR 0x0202 /* getting ATR sequence from card */ 244 #define msIdleOn 0x0203 /* idle, put card powered on */ 245 #define msT0Send 0x0204 /* sending T0 data */ 246 #define msT0Recv 0x0205 /* recving T0 data */ 247 248 249 250 251 /* commands to T0 send state machine */ 252 #define t0scStart 0x0300 /* start */ 253 #define t0scTWorkWaiting 0x0301 /* work waiting timeout */ 254 255 /* states in T0 send state machine */ 256 #define t0ssIdle 0x0400 /* idle state */ 257 #define t0ssSendHeader 0x0401 /* send 5 header bytes */ 258 #define t0ssRecvProcedure 0x0402 /* wait for procedure byte */ 259 #define t0ssSendByte 0x0403 /* send 1 byte */ 260 #define t0ssSendData 0x0404 /* send all bytes */ 261 #define t0ssRecvSW1 0x0405 /* wait for sw1 */ 262 #define t0ssRecvSW2 0x0406 /* wait for sw2 */ 263 264 265 266 267 268 /* commands to T0 recv state machine */ 269 #define t0rcStart 0x0500 /* start */ 270 #define t0rcTWorkWaiting 0x0501 /* work waiting timeout */ 271 272 /* states in T0 recv state machine */ 273 #define t0rsIdle 0x0600 /* idle state */ 274 #define t0rsSendHeader 0x0601 /* send 5 header bytes */ 275 #define t0rsRecvProcedure 0x0602 /* wait for procedure byte */ 276 #define t0rsRecvByte 0x0603 /* recv 1 byte */ 277 #define t0rsRecvData 0x0604 /* recv all bytes */ 278 #define t0rsRecvSW1 0x0605 /* wait for sw1 */ 279 #define t0rsRecvSW2 0x0606 /* wait for sw2 */ 280 281 282 283 /* commands to Cold Reset state machine */ 284 #define crcStart 0x0900 /* start */ 285 #define crcT2 0x0902 /* timeout T2 ISO 7816-3, P6, Figure 2 */ 286 287 /* states in cold reset state machine */ 288 #define crsIdle 0x0a00 /* idle */ 289 #define crsT2Wait 0x0a01 /* wait for T2 ISO 7816-3.P6. Figure 2 */ 290 291 292 293 294 295 /* commands to Answer To Reset (ATR) state machine */ 296 #define atrcStart 0x0b00 /* start */ 297 #define atrcT3 0x0b04 /* got T3 timeout */ 298 #define atrcTWorkWaiting 0x0b05 /* work waiting timeout */ 299 300 /* states in Answer To Reset (ATR) state machine */ 301 #define atrsIdle 0x0c00 /* idle */ 302 #define atrsTS 0x0c01 /* looking for TS, (initial bytes) */ 303 #define atrsT0 0x0c02 /* looking for T0, (format bytes) */ 304 #define atrsTABCD 0x0c03 /* looking for TAx (interface bytes)*/ 305 #define atrsTK 0x0c04 /* looking for TK (history bytes) */ 306 #define atrsTCK 0x0c05 /* looking for TCK (check bytes */ 307 308 309 /* commands to T0 Recv Byte state machine */ 310 #define t0rbcStart 0x0d00 /* start */ 311 #define t0rbcAbort 0x0d01 /* abort */ 312 #define t0rbcTFindStartEdge 0x0d02 /* start bit edge search */ 313 #define t0rbcTFindStartMid 0x0d03 /* start bit mid search */ 314 #define t0rbcTClockData 0x0d04 /* data bit search */ 315 #define t0rbcTErrorStart 0x0d05 /* start to send error */ 316 #define t0rbcTErrorStop 0x0d06 /* stop sending error */ 317 318 /* states in T0 Recv Byte state machine */ 319 #define t0rbsIdle 0x0e00 /* idle */ 320 #define t0rbsFindStartEdge 0x0e01 /* looking for start bit */ 321 #define t0rbsFindStartMid 0x0e02 /* looking for start bit */ 322 #define t0rbsClockData 0x0e03 /* looking for data bits */ 323 #define t0rbsSendError 0x0e04 /* output error bit */ 324 325 326 327 328 /* commands to T0 Send Byte state machine */ 329 #define t0sbcStart 0x0f00 /* start the machine */ 330 #define t0sbcAbort 0x0f01 /* abort the machine */ 331 #define t0sbcTGuardTime 0x0f02 /* guard time finished */ 332 #define t0sbcTClockData 0x0f03 /* clock time finished */ 333 #define t0sbcTError 0x0f04 /* start to send error */ 334 #define t0sbcTResend 0x0f05 /* if parity error, then wait unfill we can re-send */ 335 336 337 338 /* states in T0 Send Byte state machine */ 339 #define t0sbsIdle 0x1000 /* idle */ 340 #define t0sbsWaitGuardTime 0x1001 /* wait for guard time to finish */ 341 #define t0sbsClockData 0x1002 /* clocking out data & parity */ 342 #define t0sbsWaitError 0x1003 /* waiting for error indicator */ 343 #define t0sbsWaitResend 0x1004 /* waiting to start re-send if error */ 344 345 346 347 348 /* 349 ** generic middle level state machine commands 350 ** sent by T0 Send Byte & T0 recv Byte to T0 Send and T0 Recv 351 */ 352 #define gcT0RecvByte 0x1100 /* receive finished */ 353 #define gcT0RecvByteErr 0x1101 /* receive got error */ 354 #define gcT0SendByte 0x1102 /* send finished */ 355 #define gcT0SendByteErr 0x1103 /* send got error */ 356 357 358 359 360 361 362 /* 363 ** 364 ** below are definitions associated with Smart Card 365 ** 366 */ 367 368 369 /* 370 ** Frequency of clock sent to card 371 ** NCI's card is running at 1/2 freq, so in debug we can make 372 ** use of this to toggle more debug signals and still be within 373 ** interrupt time budget 374 */ 375 #ifdef SCR_DEBUG 376 #define CARD_FREQ_DEF (3579000/2) 377 #else 378 #define CARD_FREQ_DEF (3579000) 379 #endif 380 381 382 383 /* byte logic level and msb/lsb coding */ 384 #define CONVENTION_UNKNOWN 0 385 #define CONVENTION_INVERSE 1 386 #define CONVENTION_DIRECT 2 387 #define CONVENIONT_INVERSE_ID 0x3f 388 #define CONVENTION_DIRECT_FIX 0x3b 389 #define CONVENTION_DIRECT_ID 0x23 390 391 392 /* macros that help us set the T2 count for bit bashing */ 393 #define CLK_COUNT_START (((372 * TIMER_FREQ) / sc->cardFreq) /5) 394 #define CLK_COUNT_DATA (((372 * TIMER_FREQ) / sc->cardFreq) ) 395 #define START_2_DATA 5 396 397 /* default settings to use if not specified in ATR */ 398 #define N_DEFAULT 0 /* guard time default */ 399 #define Fi_DEFAULT 372 /* clock rate conversion default */ 400 #define Di_DEFAULT 1 /* bit rate adjustment factor */ 401 #define Wi_DEFAULT 10 /* waiting time */ 402 403 404 /* table for clock rate adjustment in ATR */ 405 int FI2Fi[16] = {372, 372, 558, 744,1116,1488,1860, 0, 406 0, 512, 768,1024,1536,2048, 0, 0}; 407 408 /* table for bit rate adjustment in ATR*/ 409 int DI2Di[16] = { 0, 1, 2, 4, 8, 16, 32, 0, 410 12, 20, 0, 0, 0, 0, 0, 0}; 411 412 /* values of atrY in the ATR sequence*/ 413 #define ATR_Y_TA 0x10 414 #define ATR_Y_TB 0x20 415 #define ATR_Y_TC 0x40 416 #define ATR_Y_TD 0x80 417 418 /* T0,T1,etc information in ATR sequence*/ 419 #define PROTOCOL_T0 0x0001 /* bit 0 for T0 */ 420 #define PROTOCOL_T1 0x0002 /* bit 1 for T1 */ 421 #define PROTOCOL_T2 0x0004 /* bit 2 for T2*/ 422 #define PROTOCOL_T3 0x0008 /* bit 3 for T3*/ 423 /* etc */ 424 425 426 /* timeouts for various places - see ISO 7816-3 */ 427 #define T_t2 ((300 * TIMER_FREQ) / sc->cardFreq) 428 #define T_t3 ((40000 * (TIMER_FREQ/1024)) / (sc->cardFreq/1024)) 429 #define T_WORK_WAITING (((960 * sc->Wi * sc->Fi ) / (sc->cardFreq/1024)) * (TIMER_FREQ/1024)) 430 #define PARITY_ERROR_MAX 3 /* maximum parity errors on 1 byte before giving up */ 431 432 /* 433 ** its possible for the HAT to wedge. If that happens, all timing is sick, so 434 ** we use timeout below (driven of system sleeps) as a "watchdog" 435 */ 436 #define MAX_FIQ_TIME 5 /* maximum time we are willing to run the FIQ */ 437 438 439 /* used to decode T0 commands */ 440 #define CMD_BUF_INS_OFF 1 /* offset to INS in header */ 441 #define CMD_BUF_DATA_LEN_OFF 4 /* offset to data length in header */ 442 443 444 /* 445 ** 446 ** DATA STRUCTURES 447 ** 448 */ 449 typedef unsigned char BYTE; 450 451 /* our soft c structure */ 452 struct scr_softc 453 { 454 int open; 455 456 /* configuration information */ 457 int status; /* status to be returned */ 458 int cardFreq; /* freq supplied to card */ 459 int convention; /* ie direct or inverse */ 460 int protocolType; /* bit 0 indicates T0, bit 1 indicates T1,etc */ 461 int N; /* guard time */ 462 int Fi; /* clock rate */ 463 int Di; /* bit rate adjustment */ 464 int Wi; /* work waiting time */ 465 int clkCountStartRecv; /* count for clock start bits on recv */ 466 int clkCountDataRecv; /* count for clock data bits on recv*/ 467 int clkCountDataSend; /* count for clock data bits on send */ 468 469 /* state machines */ 470 int masterS ; 471 int t0RecvS; 472 int t0SendS; 473 int coldResetS; 474 int ATRS; 475 int t0RecvByteS; 476 int t0SendByteS; 477 478 /* extra stuff kept for t0send state machine */ 479 int commandCount; /* number of command bytes sent */ 480 int dataCount; /* number of data bytes send/recv */ 481 int dataMax; /* max number of data bytes to send/recv */ 482 483 /* extra stuff kept for t0RecvByteS, t0SendByteS machines */ 484 void (*t0ByteParent)(struct scr_softc *,int); /* state machine that is controlling this SM */ 485 int shiftBits; /* number of bits shifted */ 486 BYTE shiftByte; /* intermediate value of bit being shifted */ 487 BYTE dataByte; /* actual value of byte */ 488 int shiftParity; /* value of parity */ 489 int shiftParityCount; /* number of retries due to parity error */ 490 491 /* extra stuff kept for ATR machine */ 492 int atrY; /* indicates if TA,TB,TC,TD is to follow */ 493 int atrK; /* number of historical characters*/ 494 int atrKCount; /* progressive could of historical characters*/ 495 int atrTABCDx; /* the 'i' in TA(i), TB(i), TC(i) and TD(i) */ 496 int atrFi; /* value of Fi */ 497 int atrDi; /* value of Di */ 498 499 int masterDone; /* flag used by bottom half to tell top half its done */ 500 int bigTrouble; /* david/jim, remove this when the dust settles */ 501 502 /* pointers used by ioctl */ 503 ScrOn * pIoctlOn; /* pointer to on ioctl data */ 504 ScrT0 * pIoctlT0; /* pointer to T0 ioctl data */ 505 }; 506 507 /* number of devices */ 508 static int devices = 0; 509 510 /* used as reference for tsleep */ 511 static int tsleepIdent; 512 513 514 /* 515 ** only 1 device is using the hat at any one time 516 ** variable below must be acquired using splhigh before using the hat 517 */ 518 static int hatLock = false; 519 520 521 522 523 /* 524 ** data structures associated with our timeout queue that we run for the 525 ** bottom half of the driver 526 */ 527 528 /* timeout callout structure */ 529 typedef struct callout_t 530 { 531 struct callout_t *c_next; /* next callout in queue */ 532 struct scr_softc *c_sc; /* soft c */ 533 int c_arg; /* function argument */ 534 void (*c_func)(struct scr_softc*,int); /* function to call */ 535 int c_time; /* ticks to the event */ 536 }Callout; 537 538 /* actual callout array */ 539 #define SCR_CLK_CALLOUT_COUNT 10 540 static Callout scrClkCalloutArray[SCR_CLK_CALLOUT_COUNT]; 541 542 /* callout lists */ 543 static Callout *scrClkCallFree; /* free queue */ 544 static Callout scrClkCallTodo; /* todo queue */ 545 546 /* 547 ** information kept for the clock/FIQ that drives our timeout queue 548 */ 549 static int scrClkEnable = 0; /* true if clock enabled */ 550 static void myHatWedge(int nFIQs); /* callback that informs us if FIQ has wedged */ 551 static int scrClkCount; /* number used to set t2 that drives FIQ */ 552 553 #define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ 554 static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used during a FIQ */ 555 556 557 558 559 560 561 562 563 564 565 566 567 /* 568 ** 569 ** FUNCTIONAL PROTOTYPES 570 ** 571 */ 572 573 /* 574 ** 575 ** functions in top half of driver 576 ** 577 */ 578 579 /* configure routines */ 580 int scrprobe(device_t, cfdata_t, void *); 581 void scrattach(device_t, device_t, void *); 582 583 static void initStates(struct scr_softc * sc); 584 585 586 587 588 /* 589 ** 590 ** functions in bottom half of driver 591 ** 592 */ 593 594 /* top level state machine */ 595 static void masterSM(struct scr_softc * sc,int cmd); 596 597 /* mid level state machines, ie protocols */ 598 static void t0SendSM(struct scr_softc * sc,int cnd); 599 static void t0RecvSM(struct scr_softc * sc,int cnd); 600 static void ATRSM(struct scr_softc * sc,int cnd); 601 602 /* low level state machines, ie bash hardware bits */ 603 static void coldResetSM(struct scr_softc * sc,int cnd); 604 605 static void t0SendByteSM(struct scr_softc * sc,int cnd); 606 static void t0RecvByteSM(struct scr_softc * sc,int cnd); 607 608 static void cardOff(struct scr_softc * sc); 609 610 /* 611 ** functions used for our own timeout routines. 612 ** we cannot use system ones as we are running at a spl level 613 ** that can interrupt the system timeout routines 614 */ 615 static void scrClkInit(void); 616 static void scrClkStart(struct scr_softc* sc,int countPerTick); 617 static void scrClkAdj(int count); 618 static void scrClkStop(void); 619 static void hatClkIrq(int count); 620 621 static void scrTimeout(void (*func)(struct scr_softc*,int), struct scr_softc*, int arg, int count); 622 static void scrUntimeout(void (*func)(struct scr_softc*,int), struct scr_softc*, int arg); 623 624 625 /* debug functions */ 626 #ifdef SCR_DEBUG 627 static void invalidStateCmd(struct scr_softc* sc,int state,int cmd, int line); 628 static char * getText(int x); 629 #endif 630 631 632 633 634 635 CFATTACH_DECL_NEW(scr, sizeof(struct scr_softc), 636 scrprobe, scrattach, NULL, NULL); 637 638 extern struct cfdriver scr_cd; 639 640 dev_type_open(scropen); 641 dev_type_close(scrclose); 642 dev_type_ioctl(scrioctl); 643 644 const struct cdevsw scr_cdevsw = { 645 .d_open = scropen, 646 .d_close = scrclose, 647 .d_read = noread, 648 .d_write = nowrite, 649 .d_ioctl = scrioctl, 650 .d_stop = nostop, 651 .d_tty = notty, 652 .d_poll = nopoll, 653 .d_mmap = nommap, 654 .d_kqfilter = nokqfilter, 655 .d_discard = nodiscard, 656 .d_flag = D_TTY 657 }; 658 659 /* 660 **++ 661 ** FUNCTIONAL DESCRIPTION: 662 ** 663 ** scrProbe 664 ** 665 ** This is the probe routine for the Smart Card. Because the 666 ** Smart Card is hard wired, there is no probing to perform. The 667 ** function ensures that a successful problem occurs only once. 668 ** 669 ** FORMAL PARAMETERS: 670 ** 671 ** parent - input : pointer to the parent device 672 ** match - not used 673 ** aux - output : pointer to an isa_attach_args structure. 674 ** 675 ** IMPLICIT INPUTS: 676 ** 677 ** none. 678 ** 679 ** IMPLICIT OUTPUTS: 680 ** 681 ** none. 682 ** 683 ** FUNCTION VALUE: 684 ** 685 ** 0 - Probe failed to find the requested device. 686 ** 1 - Probe successfully talked to the device. 687 ** 688 ** SIDE EFFECTS: 689 ** 690 ** none. 691 **-- 692 */ 693 int 694 scrprobe(device_t parent, cfdata_t match, void *aux) 695 { 696 struct isa_attach_args *ia = aux; 697 int rv = 0; 698 699 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: called, name = %s\n", 700 device_cfdata(parent)->cf_name)); 701 702 if (device_is_a(parent, "ofisascr") && devices == 0) 703 { 704 /* set "devices" to ensure that we respond only once */ 705 devices++; 706 707 /* tell the caller that we are not using any resource */ 708 ia->ia_nio = 0; 709 ia->ia_niomem = 0; 710 ia->ia_nirq = 0; 711 ia->ia_ndrq = 0; 712 rv = 1; 713 714 715 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: successful \n")); 716 717 } 718 719 720 return (rv); 721 722 } /* End scrprobe() */ 723 724 725 /* 726 **++ 727 ** FUNCTIONAL DESCRIPTION: 728 ** 729 ** scrattach 730 ** 731 ** Initialize the clock and state machines 732 ** 733 ** FORMAL PARAMETERS: 734 ** 735 ** parent - input : pointer to my parents device structure. 736 ** self - output : pointer to my softc with device structure at front. 737 ** aux - input : pointer to the isa_attach_args structure. 738 ** 739 ** IMPLICIT INPUTS: 740 ** 741 ** nill 742 ** 743 ** IMPLICIT OUTPUTS: 744 ** 745 ** scrconsinit - clock callout functions set 746 ** state machines all at idle 747 ** 748 ** FUNCTION VALUE: 749 ** 750 ** none. 751 ** 752 ** SIDE EFFECTS: 753 ** 754 ** none. 755 **-- 756 */ 757 void 758 scrattach(device_t parent, device_t self, void *aux) 759 { 760 struct scr_softc *sc = device_private(self); 761 762 printf("\n"); 763 if (device_is_a(parent, "ofisascr")) 764 { 765 KERN_DEBUG (scrdebug, SCRATTACH_DEBUG_INFO,("scrattach: called \n")); 766 767 /* set initial state machine values */ 768 scrClkInit(); 769 initStates(sc); 770 sc->open = false; 771 } 772 773 else 774 { 775 panic("scrattach: not on an ISA bus, attach impossible"); 776 } /* End else we aren't on ISA and we can't handle it */ 777 778 779 return; 780 } /* End scrattach() */ 781 782 783 /* 784 **++ 785 ** FUNCTIONAL DESCRIPTION: 786 ** 787 ** initStates 788 ** 789 ** sets the state of all machines to idle 790 ** 791 ** FORMAL PARAMETERS: 792 ** 793 ** sc - Pointer to the softc structure. 794 ** 795 ** IMPLICIT INPUTS: 796 ** 797 ** nill 798 ** 799 ** IMPLICIT OUTPUTS: 800 ** 801 ** nill 802 ** 803 ** FUNCTION VALUE: 804 ** 805 ** nill 806 ** 807 ** SIDE EFFECTS: 808 ** 809 ** nill 810 **-- 811 */ 812 static void initStates(struct scr_softc * sc) 813 { 814 sc->masterS = msIdleOff; 815 sc->t0RecvS = t0rsIdle; 816 sc->t0SendS = t0ssIdle; 817 sc->coldResetS = crsIdle; 818 sc->ATRS = atrsIdle; 819 sc->t0RecvByteS = t0rbsIdle; 820 sc->t0SendByteS = t0sbsIdle; 821 } 822 823 824 825 /* 826 **++ 827 ** FUNCTIONAL DESCRIPTION: 828 ** 829 ** scrOpen 830 ** 831 ** Opens the driver. We only let the device be opened 832 ** once for security reasons 833 ** 834 ** FORMAL PARAMETERS: 835 ** 836 ** dev - input : Device identifier consisting of major and minor numbers. 837 ** flag - input : Indicates if this is a blocking I/O call. 838 ** mode - not used. 839 ** l - input : Pointer to the lwp structure of the light weight process 840 ** performing the open. 841 ** 842 ** IMPLICIT INPUTS: 843 ** 844 ** none. 845 ** 846 ** IMPLICIT OUTPUTS: 847 ** 848 ** none. 849 ** 850 ** FUNCTION VALUE: 851 ** 852 ** ENXIO - invalid device specified for open. 853 ** EBUSY - The unit is already open 854 ** 855 ** SIDE EFFECTS: 856 ** 857 ** none. 858 **-- 859 */ 860 int scropen(dev_t dev, int flag, int mode, struct lwp *l) 861 { 862 struct scr_softc *sc; 863 864 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO, 865 ("scropen: called with minor device %d and flag 0x%x\n", 866 SCRUNIT(dev), flag)); 867 868 sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 869 if (!sc) 870 { 871 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 872 return (ENXIO); 873 } 874 875 876 // david,jim - remove ifdef this when NCI can cope with only 1 open 877 #if 0 878 if (sc->open) 879 { 880 881 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return EBUSY\n")); 882 return (EBUSY); 883 } 884 885 886 /* set all initial conditions */ 887 sc->open = true; 888 #endif 889 890 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("scropen: success \n")); 891 /* Now invoke the line discipline open routine 892 */ 893 894 return 0; 895 896 } /* End scropen() */ 897 898 899 /* 900 **++ 901 ** FUNCTIONAL DESCRIPTION: 902 ** 903 ** This function closed the driver 904 ** 905 ** FORMAL PARAMETERS: 906 ** 907 ** dev - input : Device identifier consisting of major and minor numbers. 908 ** flag - Not used. 909 ** mode - Not used. 910 ** p - Not used. 911 ** 912 ** IMPLICIT INPUTS: 913 ** 914 ** scr_cd - used to locate the softc structure for the device unit 915 ** identified by dev. 916 ** 917 ** IMPLICIT OUTPUTS: 918 ** 919 ** The device is put into an idle state. 920 ** 921 ** FUNCTION VALUE: 922 ** 923 ** 0 - Always returns success. 924 ** 925 ** SIDE EFFECTS: 926 ** 927 ** none. 928 **-- 929 */ 930 int scrclose(dev_t dev, int flag, int mode, struct lwp *l) 931 { 932 #if 0 933 struct scr_softc *sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 934 #endif 935 936 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO, 937 ("scrclose: called for minor device %d flag 0x%x\n", 938 SCRUNIT(dev), flag)); 939 940 // david,jim - remove ifdef this when NCI can cope with only 1 open 941 #if 0 942 /* Check we are open in the first place 943 */ 944 if (sc->open) 945 { 946 /* put everything in the idle state */ 947 scrClkInit(); 948 initStates(sc); 949 sc->open = false; 950 951 } 952 953 954 else 955 { 956 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("\t scrclose, device not open\n")); 957 } 958 #endif 959 960 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("scrclose exiting\n")); 961 return(0); 962 } 963 964 /* 965 **++ 966 ** FUNCTIONAL DESCRIPTION: 967 ** 968 ** This routine is responsible for performing I/O controls. 969 ** 970 ** There are 4 commands. Status, On, T0 and Off. 971 ** 972 ** Status checks to see if the card is inserted. This command 973 ** does not use the state machines 974 ** 975 ** On turns the card on and gets the ATR sequence from the card. 976 ** This command does use the state machines 977 ** 978 ** T0 is used to read and write the card. This command does use 979 ** the state machines 980 ** 981 ** Off turns the card off. This command does not use the state 982 ** machines. 983 ** 984 ** 985 ** FORMAL PARAMETERS: 986 ** 987 ** dev - input : Device identifier consisting of major and minor numbers. 988 ** cmd - input : The requested IOCTL command to be performed. 989 ** See scrio.h for details 990 ** 991 ** 992 ** Bit Position { 3322222222221111111111 993 ** { 10987654321098765432109876543210 994 ** Meaning | DDDLLLLLLLLLLLLLGGGGGGGGCCCCCCCC 995 ** 996 ** D - Command direction, in/out/both. 997 ** L - Command argument length. 998 ** G - Command group, 't' used for tty. 999 ** C - Actual command enumeration. 1000 ** 1001 ** data - input/output : Direction depends on the command. 1002 ** flag - input : Not used by us but passed to line discipline and ttioctl 1003 ** l - input : pointer to lwp structure of user. 1004 ** 1005 ** IMPLICIT INPUTS: 1006 ** 1007 ** none. 1008 ** 1009 ** IMPLICIT OUTPUTS: 1010 ** 1011 ** sc->masterS state of master state machine 1012 ** 1013 ** 1014 ** FUNCTION VALUE: 1015 ** 1016 ** ENOTTY if not correct ioctl 1017 ** 1018 ** 1019 ** SIDE EFFECTS: 1020 ** 1021 **-- 1022 */ 1023 int 1024 scrioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1025 { 1026 struct scr_softc* sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 1027 1028 int error = 0; /* error value returned */ 1029 int masterDoneRetries= 0; /* nuber of times we looked at masterDone */ 1030 int done; /* local copy of masterDone */ 1031 1032 ScrStatus * pIoctlStatus; /* pointer to status ioctl */ 1033 ScrOff * pIoctlOff; /* pointer to off ioctl */ 1034 1035 u_int savedInts; /* saved interrupts */ 1036 int s; /* saved spl value */ 1037 1038 1039 1040 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1041 ("scrioctl: called for device 0x%x, command 0x%lx, " 1042 "flag 0x%x\n", 1043 SCRUNIT(dev), cmd, flag)); 1044 1045 1046 1047 switch (cmd) 1048 { 1049 /* 1050 ** get the status of the card, ie is it in, in but off, in and on 1051 */ 1052 case SCRIOSTATUS: 1053 pIoctlStatus = (ScrStatus*)data; 1054 if (scrGetDetect()) 1055 { 1056 savedInts = disable_interrupts(I32_bit | F32_bit); 1057 if (sc->masterS == msIdleOn) 1058 { 1059 pIoctlStatus->status = CARD_ON; 1060 } 1061 else 1062 { 1063 ASSERT(sc->masterS == msIdleOff); 1064 pIoctlStatus->status = CARD_INSERTED; 1065 } 1066 restore_interrupts(savedInts); 1067 } 1068 1069 else 1070 { 1071 pIoctlStatus->status = CARD_REMOVED; 1072 } 1073 break; 1074 1075 1076 1077 /* 1078 ** turn the card on and get the ATR sequence 1079 */ 1080 case SCRIOON: 1081 sc->pIoctlOn = (ScrOn*)data; 1082 // acquire the hat lock. 1083 while (1) 1084 { 1085 s = splhigh(); 1086 if(!hatLock) 1087 { 1088 hatLock = true; 1089 splx(s); 1090 break; 1091 } 1092 splx(s); 1093 1094 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1095 } 1096 1097 1098 // check to see if the card is in 1099 if(!scrGetDetect()) 1100 { 1101 initStates(sc); 1102 cardOff(sc); 1103 // do not call scrClkInit() as it is idle already 1104 sc->pIoctlOn->status = ERROR_CARD_REMOVED; 1105 } 1106 1107 1108 // check to see if we are already on 1109 else if(sc->masterS == msIdleOn) 1110 { 1111 sc->pIoctlOn->status = ERROR_CARD_ON; 1112 } 1113 1114 // card was in, card is off, so lets start it 1115 else 1116 { 1117 // set up the top half 1118 sc->masterDone = false; 1119 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1120 1121 1122 1123 // start bottom half 1124 scrClkStart (sc,400); 1125 savedInts = disable_interrupts(I32_bit | F32_bit); 1126 masterSM(sc,mcOn); 1127 restore_interrupts(savedInts); 1128 1129 1130 1131 // see if bottom half done 1132 while (1) 1133 { 1134 // check that we have not looped too many times 1135 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1136 { 1137 //printf("MAX_FIQ_TIME reached \n"); 1138 // big problems, so reset bottom 1139 savedInts = disable_interrupts(I32_bit | F32_bit); 1140 scrClkInit(); 1141 initStates(sc); 1142 cardOff(sc); 1143 sc->status = ERROR_CARD_REMOVED; 1144 sc->masterDone = true; 1145 restore_interrupts(savedInts); 1146 // dont stop clock, done at bottom of case 1147 } 1148 masterDoneRetries++; 1149 1150 // get done bit 1151 savedInts = disable_interrupts(I32_bit | F32_bit); 1152 done = sc->masterDone; 1153 restore_interrupts(savedInts); 1154 1155 // see if all done 1156 if(done) 1157 { 1158 break; 1159 } 1160 1161 1162 // wait for a while 1163 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1164 } 1165 1166 1167 // stop bottom half 1168 scrClkStop(); 1169 1170 1171 /* need to fix up count bits in non hat interrupt time, so */ 1172 if (sc->status == ERROR_OK) 1173 { 1174 sc->clkCountStartRecv = CLK_COUNT_START; 1175 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1176 sc->clkCountDataSend = CLK_COUNT_DATA; 1177 } 1178 1179 1180 1181 /* takes while to turn off all lines, so keep out of hat */ 1182 if (sc->masterS != msIdleOn) 1183 { 1184 cardOff(sc); 1185 } 1186 // get the status back from the state machine 1187 sc->pIoctlOn->status = sc->status; 1188 1189 1190 } 1191 1192 1193 // release the hat lock. 1194 s = splhigh(); 1195 ASSERT(hatlock); 1196 hatLock = false; 1197 splx(s); 1198 1199 // david,jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1200 if (sc->pIoctlOn->status != ERROR_OK) 1201 { 1202 sc->pIoctlOn->atrLen = 0; 1203 } 1204 break; 1205 1206 1207 /* 1208 ** turn the card off 1209 */ 1210 case SCRIOOFF: 1211 pIoctlOff = (ScrOff*)data; 1212 // card off does not requires any state processing, so do work here 1213 initStates(sc); 1214 cardOff(sc); 1215 // do not call scrClkInit() as it is idle already 1216 pIoctlOff->status = ERROR_OK; 1217 break; 1218 1219 1220 /* 1221 ** do a T0 read or write 1222 */ 1223 case SCRIOT0: 1224 sc->pIoctlT0 = (ScrT0*)data; 1225 1226 // acquire the hat lock. 1227 while (1) 1228 { 1229 s = splhigh(); 1230 if(!hatLock) 1231 { 1232 hatLock = true; 1233 splx(s); 1234 break; 1235 } 1236 splx(s); 1237 1238 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1239 } 1240 1241 // check to see if the card is in 1242 if(!scrGetDetect()) 1243 { 1244 initStates(sc); 1245 cardOff(sc); 1246 // do not call scrClkInit() as it is idle already 1247 sc->pIoctlT0->status = ERROR_CARD_REMOVED; 1248 } 1249 1250 1251 // check to see if card is off 1252 else if(sc->masterS == msIdleOff) 1253 { 1254 sc->pIoctlT0->status = ERROR_CARD_OFF; 1255 } 1256 1257 // card was in, card is on, lets do command 1258 else 1259 1260 { 1261 // set up the top half 1262 sc->masterDone = false; 1263 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1264 1265 // start bottom half 1266 scrClkStart (sc,sc->clkCountDataSend); 1267 savedInts = disable_interrupts(I32_bit | F32_bit); 1268 if (sc->pIoctlT0->writeBuffer) 1269 { 1270 masterSM(sc,mcT0DataSend); 1271 } 1272 else 1273 { 1274 masterSM(sc,mcT0DataRecv); 1275 } 1276 restore_interrupts(savedInts); 1277 1278 1279 // see if bottom half done 1280 while (1) 1281 { 1282 // check that we have not looped too many times 1283 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1284 { 1285 //printf("MAX_FIQ_TIME reached \n"); 1286 // big problems, so reset bottom 1287 savedInts = disable_interrupts(I32_bit | F32_bit); 1288 scrClkInit(); 1289 initStates(sc); 1290 cardOff(sc); 1291 sc->status = ERROR_CARD_REMOVED; 1292 sc->masterDone = true; 1293 restore_interrupts(savedInts); 1294 } 1295 masterDoneRetries++; 1296 1297 1298 // get done bit 1299 savedInts = disable_interrupts(I32_bit | F32_bit); 1300 done = sc->masterDone; 1301 restore_interrupts(savedInts); 1302 1303 1304 // see if all done 1305 if(done) 1306 { 1307 break; 1308 } 1309 1310 1311 // wait for a while 1312 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1313 } 1314 1315 // stop bottom half 1316 scrClkStop(); 1317 1318 1319 1320 // get the status back from the state machine 1321 sc->pIoctlT0->status = sc->status; 1322 } 1323 1324 1325 // release the hat lock. 1326 s = splhigh(); 1327 hatLock = false; 1328 splx(s); 1329 1330 1331 1332 // david, jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1333 if (sc->pIoctlT0->status != ERROR_OK) 1334 { 1335 sc->pIoctlT0->dataLen = 0; 1336 } 1337 break; 1338 1339 default: 1340 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO,("\t scrioctl: unknown command, ENOTTY \n")); 1341 error = ENOTTY; 1342 break; 1343 } 1344 1345 1346 1347 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1348 ("scrioctl: exiting with sc->status %d\n", error)); 1349 return (error); 1350 } /* End scrioctl */ 1351 1352 1353 1354 1355 1356 1357 /* 1358 ** 1359 ** All functions below this point are the bottom half of the driver 1360 ** 1361 ** All are called during a FIQ, except for some functions in masterSM which 1362 ** provides the interface between the bottom half and top half of 1363 ** the driver (nb masterDone() helps masterSM() out with this interface 1364 ** between top and bottom parts of the driver. 1365 ** 1366 */ 1367 1368 1369 /* 1370 **++ 1371 ** FUNCTIONAL DESCRIPTION: 1372 ** 1373 ** masterSM 1374 ** 1375 ** This state machine implements the top level state control It 1376 ** receives commands to turn the card on, and do T0 reads and T0 writes 1377 ** from the scrioctl. It then calls mid level state machine to action 1378 ** these commands. 1379 ** 1380 ** This machine is the only machine to keep state between scrioctl calls. 1381 ** Between calls, the state will be either msIdleOff, or msIdleOn. msIdleOff 1382 ** indicates that no signals are applied to the card. msidleOn indicates that 1383 ** power and clock are supplied to the card, and that the card has performed 1384 ** a successful ATR sequence. 1385 ** 1386 ** This routine gets called during FIQ interrupts and from scrioctl. It is a 1387 ** requirement that the scrioctl disables interrupts before calling this function. 1388 ** 1389 ** NB:- there is no way for the machine to get from msIdleOn to msIdleOff. Since 1390 ** this is just a matter of turning all signals off and resetting state machines, 1391 ** scrioctl takes a shortcut and resets everything itself. Ie it hits everything 1392 ** with a big hammer!! 1393 ** 1394 ** FORMAL PARAMETERS: 1395 ** 1396 ** sc - Pointer to the softc structure. 1397 ** cmd - command to the state machine, can be from ioctl, or mid level SM 1398 ** 1399 ** IMPLICIT INPUTS: 1400 ** 1401 ** sc->masterS state of this machine 1402 ** sc->pIoctlT0 pointer to T0 ioctl 1403 ** 1404 ** IMPLICIT OUTPUTS: 1405 ** 1406 ** 1407 ** FUNCTION VALUE: 1408 ** 1409 ** nill 1410 ** 1411 ** SIDE EFFECTS: 1412 ** 1413 ** power and clock applied to card if successful ATR 1414 **-- 1415 */ 1416 static void masterSM(struct scr_softc * sc,int cmd) 1417 { 1418 1419 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1420 1421 switch (sc->masterS) 1422 { 1423 case msIdleOff: 1424 switch (cmd) 1425 { 1426 case mcOn: 1427 if (scrGetDetect()) 1428 { 1429 /* 1430 ** the card is off, and we want it on 1431 */ 1432 1433 /* set initial values */ 1434 sc->status = 0; 1435 sc->convention = CONVENTION_UNKNOWN; 1436 sc->protocolType = 0; 1437 sc->N = N_DEFAULT; 1438 sc->Fi = Fi_DEFAULT; 1439 sc->Di = Di_DEFAULT; 1440 sc->Wi = Wi_DEFAULT; 1441 sc->cardFreq = CARD_FREQ_DEF; 1442 sc->clkCountStartRecv = CLK_COUNT_START; 1443 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1444 sc->clkCountDataSend = CLK_COUNT_DATA; 1445 1446 /* get coldResetSM to turn on power, clock, reset */ 1447 sc->masterS = msColdReset; 1448 coldResetSM(sc,crcStart); 1449 } 1450 else 1451 { 1452 /* card not inserted, so just set status and give up */ 1453 sc->status = ERROR_CARD_REMOVED; 1454 sc->masterDone = true; 1455 } 1456 break; 1457 1458 default: 1459 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1460 break; 1461 } 1462 break; 1463 1464 case msColdReset: 1465 switch (cmd) 1466 { 1467 case mcColdReset: 1468 /* 1469 ** coldResetSM has turned on power, clock , reset 1470 ** tell ATRSM to get the ATR sequence from the card 1471 */ 1472 sc->masterS = msATR; 1473 ATRSM(sc,atrcStart); 1474 break; 1475 1476 default: 1477 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1478 break; 1479 } 1480 break; 1481 1482 case msATR: 1483 switch (cmd) 1484 { 1485 case mcATR: 1486 /* 1487 ** ATRSM has tried to get ATR sequence, so give 1488 ** back results to scrioctl. ATR sequence data 1489 ** was copied directly into ioctl data area, so 1490 ** no need to copy data 1491 */ 1492 if(sc->status == ERROR_OK) 1493 { 1494 sc->masterS = msIdleOn; 1495 } 1496 else 1497 { 1498 sc->masterS = msIdleOff; 1499 } 1500 sc->masterDone = true; 1501 break; 1502 1503 1504 default: 1505 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1506 break; 1507 } 1508 break; 1509 1510 case msIdleOn: 1511 switch (cmd) 1512 { 1513 // nb there is no command to go to the IdleOff state. This 1514 // is a reset of the state machine, so is done in ioctl 1515 1516 case mcT0DataSend: 1517 /* 1518 ** card is on, and we want to T0 Send, so 1519 ** as t0SendSM to do work 1520 */ 1521 sc->status = ERROR_OK; 1522 sc->masterS = msT0Send; 1523 t0SendSM(sc,t0scStart); 1524 break; 1525 1526 case mcT0DataRecv: 1527 /* 1528 ** card is on, and we want to T0 Recv, so 1529 ** as t0RecvSM to do work 1530 */ 1531 sc->status = ERROR_OK; 1532 sc->masterS = msT0Recv; 1533 t0RecvSM(sc,t0rcStart); 1534 break; 1535 1536 default: 1537 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1538 break; 1539 } 1540 1541 break; 1542 1543 case msT0Send: 1544 switch (cmd) 1545 { 1546 case mcT0Send: 1547 /* 1548 ** t0SendSM has tried to send , so lets give back results 1549 */ 1550 sc->masterS = msIdleOn; 1551 sc->masterDone = true; 1552 break; 1553 1554 default: 1555 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1556 break; 1557 } 1558 break; 1559 1560 case msT0Recv: 1561 switch (cmd) 1562 { 1563 case mcT0Recv: 1564 /* 1565 ** t0RecvSM has tried to recv , so lets give back results 1566 ** data was written directly into ioctl data area, so we 1567 ** do not need to copy any data 1568 */ 1569 sc->pIoctlT0->dataLen = sc->dataCount; 1570 sc->masterS = msIdleOn; 1571 sc->masterDone = true; 1572 break; 1573 1574 default: 1575 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1576 break; 1577 } 1578 break; 1579 1580 default: 1581 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1582 break; 1583 1584 } 1585 } 1586 1587 1588 1589 1590 /* 1591 **++ 1592 ** FUNCTIONAL DESCRIPTION: 1593 ** 1594 ** t0SendSM 1595 ** 1596 ** This is the T=0 Send State Machine. It is responsible 1597 ** for performing the send part of the ISO 7816-3 T=0 1598 ** protocol. It is mid level protocol state machine. 1599 ** 1600 ** Once started, this machine is driven entirely via the 1601 ** FIQ/timeout structure . 1602 ** 1603 ** 1604 ** 1605 ** FORMAL PARAMETERS: 1606 ** 1607 ** sc - Pointer to the softc structure. 1608 ** cmd - command to this machine 1609 ** 1610 ** IMPLICIT INPUTS: 1611 ** 1612 ** sc->t0SendS state of this machine 1613 ** sc->pIoctlT0->command command to send to card 1614 ** sc->pIoctlT0->data data to send to card 1615 ** 1616 ** IMPLICIT OUTPUTS: 1617 ** 1618 ** sc->status error status from this machine 1619 ** sc->pIoctlT0->sw1 command status from card 1620 ** sc->pIoctlT0->sw2 command status from card 1621 ** sc->status error status from this machine 1622 ** 1623 ** FUNCTION VALUE: 1624 ** 1625 ** nill 1626 ** 1627 ** SIDE EFFECTS: 1628 ** 1629 ** nill 1630 **-- 1631 */ 1632 static void t0SendSM (struct scr_softc * sc, int cmd) 1633 { 1634 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1635 /* 1636 ** check for major failures that are common to most states 1637 */ 1638 if (cmd == t0scTWorkWaiting || 1639 cmd == gcT0RecvByteErr || 1640 cmd == gcT0SendByteErr 1641 ) 1642 { 1643 switch(cmd) 1644 { 1645 case t0scTWorkWaiting: 1646 ASSERT(sc->t0SendS != t0ssIdle); 1647 1648 /* kill all lower machines */ 1649 t0SendByteSM(sc,t0sbcAbort); 1650 t0RecvByteSM(sc,t0rbcAbort); 1651 1652 /* set status */ 1653 sc->status = ERROR_WORK_WAITING; 1654 break; 1655 1656 case gcT0RecvByteErr: // fall through 1657 case gcT0SendByteErr: 1658 scrUntimeout(t0SendSM, sc, t0scTWorkWaiting); 1659 // done set status, already set in lower machine 1660 break; 1661 1662 default: 1663 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1664 break; 1665 } 1666 1667 /* change states */ 1668 sc->t0SendS = t0ssIdle; 1669 masterSM(sc,mcT0Send); 1670 return; 1671 } 1672 1673 switch (sc->t0SendS) 1674 { 1675 case t0ssIdle: 1676 switch (cmd) 1677 { 1678 case t0scStart: 1679 /* set initial values */ 1680 sc->t0SendS = t0ssSendHeader; 1681 sc->t0ByteParent = t0SendSM; 1682 sc->commandCount = 0; 1683 sc->dataCount = 0; 1684 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1685 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1686 1687 // get a byte 1688 t0SendByteSM(sc,t0sbcStart); 1689 break; 1690 1691 default: 1692 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1693 break; 1694 } 1695 break; 1696 1697 case t0ssSendHeader: 1698 switch (cmd) 1699 { 1700 case gcT0SendByte: 1701 sc->commandCount++; 1702 if (sc->commandCount < CMD_BUF_LEN) 1703 { 1704 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1705 t0SendByteSM(sc,t0sbcStart); 1706 } 1707 else 1708 { 1709 ASSERT(sc->commandCount == CMD_BUF_LEN); 1710 1711 sc->t0SendS = t0ssRecvProcedure; 1712 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1713 t0RecvByteSM(sc,t0rbcStart); 1714 } 1715 break; 1716 1717 default: 1718 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1719 break; 1720 } 1721 break; 1722 1723 case t0ssRecvProcedure: 1724 switch (cmd) 1725 { 1726 case gcT0RecvByte: 1727 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1728 /* see if we should send all remaining bytes */ 1729 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 1730 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 1731 { 1732 ASSERT(sc->dataCount < sc->dataMax); 1733 sc->t0SendS = t0ssSendData; 1734 sc->dataByte = sc->pIoctlT0->data[sc->dataCount]; 1735 t0SendByteSM(sc,t0sbcStart); 1736 sc->dataCount++; 1737 } 1738 1739 /* see if we should send one data byte */ 1740 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 1741 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 1742 { 1743 ASSERT(sc->dataCount < sc->dataMax); 1744 sc->t0SendS = t0ssSendByte; 1745 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1746 t0SendByteSM(sc,t0sbcStart); 1747 sc->dataCount++; 1748 } 1749 1750 /* see if we should extend the work waiting period */ 1751 else if (sc->dataByte == 0x60) 1752 { 1753 t0RecvByteSM(sc,t0rbcStart); 1754 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1755 } 1756 1757 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 1758 /* see if we have a SW1 byte */ 1759 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 1760 && 1761 sc->dataByte != 0x60) 1762 #else /* XXX XXX XXX cgd */ 1763 /* see if we have a SW1 byte */ 1764 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 1765 && 1766 sc->dataByte != 0x60) 1767 #endif /* XXX XXX XXX cgd */ 1768 { 1769 sc->pIoctlT0->sw1 = sc->dataByte; 1770 sc->t0SendS = t0ssRecvSW2; 1771 t0RecvByteSM(sc,t0rbcStart); 1772 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1773 } 1774 1775 /* got bad data byte, log error and get out */ 1776 else 1777 { 1778 sc->status = ERROR_BAD_PROCEDURE_BYTE; 1779 1780 /* change state */ 1781 sc->t0SendS = t0ssIdle; 1782 masterSM(sc,mcT0Send); 1783 } 1784 break; 1785 1786 default: 1787 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1788 break; 1789 } 1790 break; 1791 1792 case t0ssSendByte: 1793 switch (cmd) 1794 { 1795 case gcT0SendByte: 1796 if (sc->dataCount < sc->dataMax) 1797 { 1798 sc->t0SendS = t0ssRecvProcedure; 1799 } 1800 1801 /* wait for sw1 byte */ 1802 else 1803 { 1804 ASSERT(sc->dataCount == sc->dataMax); 1805 sc->t0SendS = t0ssRecvSW1; 1806 } 1807 1808 // ask for another byte 1809 t0RecvByteSM(sc,t0rbcStart); 1810 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1811 break; 1812 1813 default: 1814 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1815 break; 1816 } 1817 break; 1818 1819 case t0ssSendData: 1820 switch (cmd) 1821 { 1822 case gcT0SendByte: 1823 /* send data */ 1824 if (sc->dataCount < sc->dataMax) 1825 { 1826 sc->t0SendS = t0ssSendData; 1827 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1828 t0SendByteSM(sc,t0sbcStart); 1829 sc->dataCount++; 1830 } 1831 1832 /* wait for sw1 byte */ 1833 else 1834 { 1835 ASSERT(sc->dataCount == sc->dataMax); 1836 sc->t0SendS = t0ssRecvSW1; 1837 t0RecvByteSM(sc,t0rbcStart); 1838 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1839 } 1840 break; 1841 1842 default: 1843 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1844 break; 1845 } 1846 break; 1847 1848 case t0ssRecvSW1: 1849 switch (cmd) 1850 { 1851 case gcT0RecvByte: 1852 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1853 sc->pIoctlT0->sw1 = sc->dataByte; 1854 sc->t0SendS = t0ssRecvSW2; 1855 t0RecvByteSM(sc,t0rbcStart); 1856 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1857 break; 1858 default: 1859 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1860 break; 1861 } 1862 break; 1863 1864 case t0ssRecvSW2: 1865 switch (cmd) 1866 { 1867 case gcT0RecvByte: 1868 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1869 sc->pIoctlT0->sw2 = sc->dataByte; 1870 sc->t0SendS = t0ssIdle; 1871 masterSM(sc,mcT0Send); 1872 break; 1873 1874 default: 1875 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1876 break; 1877 } 1878 break; 1879 1880 default: 1881 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1882 break; 1883 } 1884 } 1885 1886 1887 1888 /* 1889 **++ 1890 ** FUNCTIONAL DESCRIPTION: 1891 ** 1892 ** t0RecvSM 1893 ** 1894 ** This is the T=0 Recv State Machine. It is responsible 1895 ** for performing the recv part of the ISO 7816-3 T=0 1896 ** protocol. It is mid level protocol state machine. 1897 ** 1898 ** Once started, this machine is driven entirely via the 1899 ** FIQ/timeout structure . 1900 ** 1901 ** FORMAL PARAMETERS: 1902 ** 1903 ** sc - Pointer to the softc structure. 1904 ** cmd - command to this machine 1905 ** 1906 ** IMPLICIT INPUTS: 1907 ** 1908 ** sc->t0RecvS state of this machine 1909 ** sc->pIoctlT0->command command to send to card 1910 ** 1911 ** IMPLICIT OUTPUTS: 1912 ** 1913 ** sc->pIoctlT0->data data from card 1914 ** sc->pIoctlT0->dataLen size of data from card 1915 ** sc->pIoctlT0->sw1 command status from card 1916 ** sc->pIoctlT0->sw2 command status from card 1917 ** sc->status error status from this machine 1918 ** 1919 ** FUNCTION VALUE: 1920 ** 1921 ** nill 1922 ** 1923 ** SIDE EFFECTS: 1924 ** 1925 ** nill 1926 **-- 1927 */ 1928 static void t0RecvSM (struct scr_softc * sc,int cmd) 1929 { 1930 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1931 1932 /* 1933 ** check for major failures that are common to most states 1934 */ 1935 if (cmd == t0rcTWorkWaiting || 1936 cmd == gcT0RecvByteErr || 1937 cmd == gcT0SendByteErr ) 1938 1939 { 1940 switch(cmd) 1941 { 1942 1943 case t0rcTWorkWaiting: 1944 ASSERT(sc->t0RecvS != t0rsIdle); 1945 1946 /* kill all lower level machines */ 1947 t0SendByteSM(sc,t0sbcAbort); 1948 t0RecvByteSM(sc,t0rbcAbort); 1949 1950 /* set status */ 1951 sc->status = ERROR_WORK_WAITING; 1952 break; 1953 1954 case gcT0RecvByteErr: // fall through 1955 case gcT0SendByteErr: 1956 /* kill all the timers */ 1957 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 1958 break; 1959 1960 default: 1961 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1962 break; 1963 1964 } 1965 1966 1967 1968 /* change state */ 1969 sc->t0RecvS = t0rsIdle; 1970 masterSM(sc,mcT0Recv); 1971 1972 /* all done */ 1973 return; 1974 } 1975 1976 switch (sc->t0RecvS) 1977 { 1978 case t0rsIdle: 1979 switch (cmd) 1980 { 1981 case t0rcStart: 1982 /* set initial values */ 1983 sc->t0RecvS = t0rsSendHeader; 1984 sc->t0ByteParent = t0RecvSM; 1985 sc->commandCount = 0; 1986 sc->dataCount = 0; 1987 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1988 if (sc->dataMax == 0) 1989 { 1990 sc->dataMax = 256; 1991 } 1992 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1993 t0SendByteSM(sc,t0sbcStart); 1994 break; 1995 1996 default: 1997 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1998 break; 1999 } 2000 break; 2001 2002 case t0rsSendHeader: 2003 switch (cmd) 2004 { 2005 case gcT0SendByte: 2006 sc->commandCount++; 2007 if (sc->commandCount < CMD_BUF_LEN) 2008 { 2009 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2010 t0SendByteSM(sc,t0sbcStart); 2011 } 2012 else 2013 { 2014 ASSERT(sc->commandCount == CMD_BUF_LEN); 2015 2016 sc->t0RecvS = t0rsRecvProcedure; 2017 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2018 t0RecvByteSM(sc,t0rbcStart); 2019 } 2020 break; 2021 2022 default: 2023 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2024 break; 2025 } 2026 break; 2027 2028 case t0rsRecvProcedure: 2029 switch (cmd) 2030 { 2031 case gcT0RecvByte: 2032 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2033 2034 /* see if we should recv all remaining bytes */ 2035 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 2036 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 2037 { 2038 ASSERT(sc->dataCount < sc->dataMax); 2039 2040 sc->t0RecvS = t0rsRecvData; 2041 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2042 t0RecvByteSM(sc,t0rbcStart); 2043 } 2044 2045 /* see if we should send one data byte */ 2046 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 2047 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 2048 { 2049 ASSERT(sc->dataCount < sc->dataMax); 2050 sc->t0RecvS = t0rsRecvByte; 2051 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2052 t0RecvByteSM(sc,t0rbcStart); 2053 } 2054 2055 /* see if we should extend the work waiting period */ 2056 else if (sc->dataByte == 0x60) 2057 { 2058 t0RecvByteSM(sc,t0rbcStart); 2059 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2060 } 2061 2062 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 2063 /* see if we have a SW1 byte */ 2064 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 2065 && 2066 sc->dataByte != 0x60) 2067 #else /* XXX XXX XXX cgd */ 2068 /* see if we have a SW1 byte */ 2069 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 2070 && 2071 sc->dataByte != 0x60) 2072 #endif /* XXX XXX XXX cgd */ 2073 { 2074 sc->pIoctlT0->sw1 = sc->dataByte; 2075 sc->t0RecvS = t0rsRecvSW2; 2076 t0RecvByteSM(sc,t0rbcStart); 2077 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2078 } 2079 2080 /* got bad data byte, log error and get out */ 2081 else 2082 { 2083 sc->status = ERROR_BAD_PROCEDURE_BYTE; 2084 2085 /* change state */ 2086 sc->t0RecvS = t0rsIdle; 2087 masterSM(sc,mcT0Recv); 2088 } 2089 break; 2090 2091 default: 2092 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2093 break; 2094 } 2095 break; 2096 2097 case t0rsRecvByte: 2098 switch (cmd) 2099 { 2100 case gcT0RecvByte: 2101 /* clock in byte */ 2102 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2103 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2104 sc->dataCount++; 2105 2106 2107 if (sc->dataCount < sc->dataMax) 2108 { 2109 /* get procedure byte */ 2110 sc->t0RecvS = t0rsRecvProcedure; 2111 } 2112 2113 else 2114 { 2115 ASSERT(sc->dataCount == sc->dataMax); 2116 sc->t0RecvS = t0rsRecvSW1; 2117 } 2118 2119 // ask for another byte 2120 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2121 t0RecvByteSM(sc,t0rbcStart); 2122 break; 2123 2124 default: 2125 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2126 break; 2127 } 2128 break; 2129 2130 case t0rsRecvData: 2131 switch (cmd) 2132 { 2133 case gcT0RecvByte: 2134 /* clock in data */ 2135 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2136 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2137 sc->dataCount++; 2138 2139 /* decide if we have all data */ 2140 if (sc->dataCount >= sc->dataMax) 2141 { 2142 KERN_DEBUG (scrdebug, T0_RECV_SM_DEBUG_INFO,("\t\tt0RecvSM: changing state to t0rsRecvSW1\n")); 2143 ASSERT(sc->dataCount == sc->dataMax); 2144 sc->t0RecvS = t0rsRecvSW1; 2145 } 2146 2147 /* ask for another byte */ 2148 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2149 t0RecvByteSM(sc,t0rbcStart); 2150 break; 2151 2152 default: 2153 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2154 break; 2155 } 2156 break; 2157 2158 case t0rsRecvSW1: 2159 switch (cmd) 2160 { 2161 case gcT0RecvByte: 2162 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2163 sc->pIoctlT0->sw1 = sc->dataByte; 2164 2165 sc->t0RecvS = t0rsRecvSW2; 2166 t0RecvByteSM(sc,t0rbcStart); 2167 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2168 break; 2169 default: 2170 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2171 break; 2172 } 2173 break; 2174 2175 case t0rsRecvSW2: 2176 switch (cmd) 2177 { 2178 case gcT0RecvByte: 2179 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2180 sc->pIoctlT0->sw2 = sc->dataByte; 2181 2182 sc->t0RecvS = t0rsIdle; 2183 masterSM(sc,mcT0Recv); 2184 break; 2185 2186 default: 2187 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2188 break; 2189 } 2190 break; 2191 2192 default: 2193 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2194 break; 2195 } 2196 } 2197 2198 2199 /* 2200 **++ 2201 ** FUNCTIONAL DESCRIPTION: 2202 ** 2203 ** coldResetSM 2204 ** 2205 ** This state machine switches on the power, clock and reset pins 2206 ** in the correct order/timing. 2207 ** It is a low level bit-bashing state machine. 2208 ** 2209 ** 2210 ** FORMAL PARAMETERS: 2211 ** 2212 ** sc - Pointer to the softc structure. 2213 ** cmd - command to this machine 2214 ** 2215 ** IMPLICIT INPUTS: 2216 ** 2217 ** sc->coldResetS state of this machine 2218 ** 2219 ** IMPLICIT OUTPUTS: 2220 ** 2221 ** nill 2222 ** 2223 ** FUNCTION VALUE: 2224 ** 2225 ** nill 2226 ** 2227 ** SIDE EFFECTS: 2228 ** 2229 ** signals to card are on 2230 **-- 2231 */ 2232 static void coldResetSM(struct scr_softc * sc,int cmd) 2233 { 2234 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2235 2236 switch (sc->coldResetS) 2237 { 2238 case crsIdle: 2239 switch (cmd) 2240 { 2241 case crcStart: 2242 scrSetReset(true); 2243 scrSetClock(true); 2244 scrSetDataHighZ(); 2245 scrSetPower(true); 2246 2247 /* start a t2 timer */ 2248 scrTimeout(coldResetSM,sc,crcT2,T_t2); 2249 sc->coldResetS = crsT2Wait; 2250 break; 2251 2252 default: 2253 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2254 break; 2255 } 2256 break; 2257 2258 case crsT2Wait: 2259 switch (cmd) 2260 { 2261 case crcT2: 2262 /* turn off rst */ 2263 scrSetReset(false); 2264 2265 /* tell master state machine that we are all done */ 2266 sc->coldResetS = crsIdle; 2267 masterSM(sc,mcColdReset); 2268 break; 2269 2270 default: 2271 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2272 break; 2273 } 2274 break; 2275 2276 2277 default: 2278 INVALID_STATE_CMD(sc,sc->coldResetS,cmd); 2279 break; 2280 } 2281 } 2282 2283 /* 2284 **++ 2285 ** FUNCTIONAL DESCRIPTION: 2286 ** 2287 ** ATRSM 2288 ** 2289 ** This is the Answer To Reset State Machine. It is responsible 2290 ** for performing the Answer To Reset as specified in ISO 7816-3. 2291 ** It is mid level protocol state machine. 2292 ** 2293 ** Once started, this machine is driven entirely via the 2294 ** FIQ/timeout structure. 2295 ** 2296 ** 2297 ** During the first byte, we have to check if the card is operating 2298 ** at full speed or half speed. The first couple of bits are 2299 ** checked to see if it is 1/2 speed, and if so, the clock is changed 2300 ** and the state adjustes 2301 ** 2302 ** At the end of the first byte we have to determine the logic being 2303 ** used by the card, ie is it active high/low and msb/lsb. 2304 ** 2305 ** 2306 ** FORMAL PARAMETERS: 2307 ** 2308 ** sc - Pointer to the softc structure. 2309 ** cmd - command to this machine 2310 ** 2311 ** IMPLICIT INPUTS: 2312 ** 2313 ** sc->pIoctlAtr->atr data from card 2314 ** sc->pIoctlT0->sw1 command status from card 2315 ** sc->pIoctlT0->sw2 command status from card 2316 ** sc->status error status from this machine 2317 ** 2318 ** IMPLICIT OUTPUTS: 2319 ** 2320 ** sc->pIoctlOn->atrBuf data from ATR sequence 2321 ** sc->pIoctlOn->atrLen size of data from ATR sequence 2322 ** sc->status error status from this machine 2323 ** 2324 ** 2325 ** FUNCTION VALUE: 2326 ** 2327 ** nill 2328 ** 2329 ** SIDE EFFECTS: 2330 ** 2331 ** nill 2332 **-- 2333 */ 2334 static void ATRSM (struct scr_softc * sc,int cmd) 2335 { 2336 int lc; 2337 int tck; 2338 2339 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2340 2341 /* 2342 ** check for major failures that are common to most states 2343 */ 2344 if (cmd == atrcT3 || 2345 cmd == atrcTWorkWaiting || 2346 cmd == gcT0RecvByteErr 2347 ) 2348 { 2349 switch(cmd) 2350 { 2351 case atrcT3: 2352 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2353 sc->status = ERROR_ATR_T3; 2354 t0RecvByteSM(sc,t0rbcAbort); 2355 break; 2356 2357 case atrcTWorkWaiting: 2358 scrUntimeout (ATRSM,sc,atrcT3); 2359 sc->status = ERROR_WORK_WAITING; 2360 t0RecvByteSM(sc,t0rbcAbort); 2361 break; 2362 2363 case gcT0RecvByteErr: 2364 scrUntimeout (ATRSM,sc,atrcT3); 2365 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2366 /* done set status, its already set */ 2367 break; 2368 2369 default: 2370 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2371 break; 2372 } 2373 2374 /* change state */ 2375 sc->ATRS = atrsIdle; 2376 masterSM(sc,mcATR); 2377 return; 2378 } 2379 2380 switch (sc->ATRS) 2381 { 2382 case atrsIdle: 2383 switch (cmd) 2384 { 2385 case atrcStart: 2386 /* lets start looking */ 2387 sc->ATRS = atrsTS; 2388 sc->pIoctlOn->atrLen = 0; 2389 sc->t0ByteParent = ATRSM; 2390 scrTimeout(ATRSM,sc,atrcT3,T_t3 *2); /* by 2 to accommodate 1/2 freq cards */ 2391 t0RecvByteSM(sc,t0rbcStart); 2392 break; 2393 2394 default: 2395 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2396 break; 2397 } 2398 break; 2399 2400 case atrsTS: 2401 switch (cmd) 2402 { 2403 case gcT0RecvByte: 2404 scrUntimeout(ATRSM,sc,atrcT3); 2405 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2406 sc->pIoctlOn->atrLen++; 2407 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2408 { 2409 #ifdef SCR_DEBUG 2410 DEBUGGER; 2411 #endif 2412 sc->status = ERROR_ATR_TCK; 2413 sc->ATRS = atrsIdle; 2414 masterSM(sc,mcATR); 2415 } 2416 else 2417 { 2418 /* move onto recv T0 */ 2419 sc->ATRS = atrsT0; 2420 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2421 t0RecvByteSM(sc,t0rbcStart); 2422 } 2423 break; 2424 2425 default: 2426 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2427 break; 2428 } 2429 break; 2430 2431 case atrsT0: 2432 switch (cmd) 2433 { 2434 case gcT0RecvByte: 2435 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2436 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2437 sc->pIoctlOn->atrLen++; 2438 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2439 { 2440 #ifdef SCR_DEBUG 2441 printf("atrLen >= ATR_BUF_MAX\n"); 2442 DEBUGGER; 2443 #endif 2444 sc->status = ERROR_ATR_TCK; 2445 sc->ATRS = atrsIdle; 2446 masterSM(sc,mcATR); 2447 } 2448 else 2449 { 2450 /* store Y & K */ 2451 sc->atrY = sc->dataByte & 0xf0; 2452 sc->atrK = sc->dataByte & 0x0f; 2453 2454 sc->atrTABCDx = 1; 2455 sc->atrKCount = 1; 2456 2457 /* if there are no TDx following set T0 protocol */ 2458 if (!ISSET(sc->atrY,ATR_Y_TD)) 2459 { 2460 sc->protocolType = PROTOCOL_T0; 2461 } 2462 2463 2464 if (sc->atrY) 2465 { 2466 2467 sc->ATRS = atrsTABCD; 2468 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2469 t0RecvByteSM(sc,t0rbcStart); 2470 } 2471 2472 else if (sc->atrK) 2473 { 2474 sc->ATRS = atrsTK; 2475 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2476 t0RecvByteSM(sc,t0rbcStart); 2477 } 2478 2479 else if (sc->protocolType != PROTOCOL_T0) 2480 { 2481 sc->ATRS = atrsTCK; 2482 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2483 t0RecvByteSM(sc,t0rbcStart); 2484 } 2485 2486 else /* got all of ATR */ 2487 { 2488 sc->ATRS = atrsIdle; 2489 masterSM(sc,mcATR); 2490 } 2491 } 2492 break; 2493 2494 2495 default: 2496 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2497 break; 2498 } 2499 break; 2500 2501 2502 case atrsTABCD: 2503 switch (cmd) 2504 { 2505 case gcT0RecvByte: 2506 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2507 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2508 sc->pIoctlOn->atrLen++; 2509 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2510 { 2511 #ifdef SCR_DEBUG 2512 printf("atrLen >= ATR_BUF_MAX\n"); 2513 DEBUGGER; 2514 #endif 2515 sc->status = ERROR_ATR_TCK; 2516 sc->ATRS = atrsIdle; 2517 masterSM(sc,mcATR); 2518 } 2519 else 2520 { 2521 if (sc->atrY & ATR_Y_TA) 2522 { 2523 sc->atrY &= ~ATR_Y_TA; 2524 if (sc->atrTABCDx == 1) 2525 { 2526 sc->Fi = FI2Fi[((sc->dataByte >> 4) & 0x0f)]; 2527 if (sc->Fi == 0) 2528 { 2529 sc->status = ERROR_ATR_FI_INVALID; 2530 sc->Fi = Fi_DEFAULT; 2531 } 2532 2533 sc->Di = DI2Di[(sc->dataByte & 0x0f)]; 2534 if (sc->Di == 0) 2535 { 2536 sc->status = ERROR_ATR_DI_INVALID; 2537 sc->Di = Di_DEFAULT; 2538 } 2539 2540 } 2541 } 2542 2543 else if (sc->atrY & ATR_Y_TB) 2544 { 2545 sc->atrY &= ~ATR_Y_TB; 2546 } 2547 2548 else if (sc->atrY & ATR_Y_TC) 2549 { 2550 sc->atrY &= ~ATR_Y_TC; 2551 if (sc->atrTABCDx == 1) 2552 { 2553 sc->N = sc->dataByte; 2554 } 2555 2556 if (sc->atrTABCDx == 2) 2557 { 2558 sc->Wi = sc->dataByte; 2559 } 2560 } 2561 2562 else 2563 { 2564 ASSERT(sc->atrY & ATR_Y_TD); 2565 sc->atrY &= ~ATR_Y_TD; 2566 2567 /* copy across the y section of TD */ 2568 sc->atrY = sc->dataByte; 2569 sc->atrY &= 0xf0; 2570 2571 /* step to the next group of TABCD */ 2572 sc->atrTABCDx++; 2573 2574 /* store protocols */ 2575 sc->protocolType = (1 << (sc->dataByte &0x0f)); 2576 } 2577 2578 2579 /* see what we should do next */ 2580 if (sc->atrY) 2581 { 2582 /* just stay in the same state */ 2583 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2584 t0RecvByteSM(sc,t0rbcStart); 2585 } 2586 2587 else if (sc->atrK) 2588 { 2589 sc->ATRS = atrsTK; 2590 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2591 t0RecvByteSM(sc,t0rbcStart); 2592 } 2593 2594 else if (sc->protocolType != PROTOCOL_T0) 2595 { 2596 sc->ATRS = atrsTCK; 2597 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2598 t0RecvByteSM(sc,t0rbcStart); 2599 } 2600 2601 else /* got all of ATR */ 2602 { 2603 sc->ATRS = atrsIdle; 2604 masterSM(sc,mcATR); 2605 } 2606 } 2607 2608 break; 2609 2610 2611 default: 2612 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2613 break; 2614 } 2615 break; 2616 2617 case atrsTK: 2618 switch (cmd) 2619 { 2620 case gcT0RecvByte: 2621 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2622 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2623 sc->pIoctlOn->atrLen++; 2624 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2625 { 2626 #ifdef SCR_DEBUG 2627 printf("atrLen >= ATR_BUF_MAX\n"); 2628 DEBUGGER; 2629 #endif 2630 sc->status = ERROR_ATR_TCK; 2631 sc->ATRS = atrsIdle; 2632 masterSM(sc,mcATR); 2633 } 2634 else 2635 { 2636 2637 if (sc->atrKCount < sc->atrK) 2638 { 2639 sc->atrKCount++; 2640 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2641 t0RecvByteSM(sc,t0rbcStart); 2642 } 2643 2644 2645 else if (sc->protocolType != PROTOCOL_T0) 2646 { 2647 sc->ATRS = atrsTCK; 2648 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2649 t0RecvByteSM(sc,t0rbcStart); 2650 } 2651 2652 else /* got all of ATR */ 2653 { 2654 sc->ATRS = atrsIdle; 2655 masterSM(sc,mcATR); 2656 } 2657 } 2658 break; 2659 2660 default: 2661 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2662 break; 2663 } 2664 break; 2665 2666 case atrsTCK: 2667 switch (cmd) 2668 { 2669 case gcT0RecvByte: 2670 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2671 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2672 sc->pIoctlOn->atrLen++; 2673 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2674 { 2675 #ifdef SCR_DEBUG 2676 printf("atrLen >= ATR_BUF_MAX\n"); 2677 DEBUGGER; 2678 #endif 2679 sc->status = ERROR_ATR_TCK; 2680 sc->ATRS = atrsIdle; 2681 masterSM(sc,mcATR); 2682 } 2683 else 2684 { 2685 tck = 0; 2686 for (lc = 1; lc < sc->pIoctlOn->atrLen-1; lc++) 2687 { 2688 tck ^= sc->pIoctlOn->atrBuf[lc]; 2689 } 2690 2691 if (tck == sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen-1]) 2692 { 2693 sc->ATRS = atrsIdle; 2694 masterSM(sc,mcATR); 2695 } 2696 else 2697 { 2698 sc->status = ERROR_ATR_TCK; 2699 sc->ATRS = atrsIdle; 2700 masterSM(sc,mcATR); 2701 } 2702 } 2703 break; 2704 2705 default: 2706 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2707 break; 2708 } 2709 break; 2710 2711 2712 2713 default: 2714 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2715 break; 2716 } 2717 } 2718 2719 2720 2721 /* 2722 **++ 2723 ** FUNCTIONAL DESCRIPTION: 2724 ** 2725 ** t0RecvByteSM 2726 ** 2727 ** This state machine attempts to read 1 byte from a card. 2728 ** It is a low level bit-bashing state machine. 2729 ** 2730 ** Data from the card is async, so the machine scans at 2731 ** 5 times the data rate looking for a state bit. Once 2732 ** a start bit has been found, it waits for the middle of 2733 ** the bit and starts sampling at the bit rate. 2734 ** 2735 ** Several mid level machines can use this machine, so the value 2736 ** sc->t0ByteParent is used to point to back to the mid level machine 2737 ** 2738 ** 2739 ** FORMAL PARAMETERS: 2740 ** 2741 ** sc - Pointer to the softc structure. 2742 ** cmd - command to this machine 2743 ** 2744 ** IMPLICIT INPUTS: 2745 ** 2746 ** sc->t0RecvByteS state of this machine 2747 ** sc->t0ByteParent mid level machine that started this machine 2748 ** 2749 ** IMPLICIT OUTPUTS: 2750 ** 2751 ** sc->shiftByte byte read from the card 2752 ** sc->status error value if could not read byte 2753 ** 2754 ** FUNCTION VALUE: 2755 ** 2756 ** nill 2757 ** 2758 ** SIDE EFFECTS: 2759 ** 2760 ** nill 2761 **-- 2762 */ 2763 static void t0RecvByteSM(struct scr_softc* sc,int cmd) 2764 { 2765 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2766 2767 if (cmd == t0rbcAbort) 2768 { 2769 /* kill all the timers */ 2770 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartEdge); 2771 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartMid); 2772 scrUntimeout(t0RecvByteSM, sc,t0rbcTClockData); 2773 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStart); 2774 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStop); 2775 2776 scrSetDataHighZ(); 2777 sc->t0RecvByteS = t0rbsIdle; 2778 return; 2779 } 2780 2781 2782 switch (sc->t0RecvByteS) 2783 { 2784 case t0rbsIdle: 2785 switch (cmd) 2786 { 2787 case t0rbcStart: 2788 /* set initial conditions */ 2789 sc->shiftBits = 0; 2790 sc->shiftByte = 0; 2791 sc->shiftParity = 0; 2792 sc->shiftParityCount = 0; 2793 scrClkAdj(sc->clkCountStartRecv); /* recv data clock running at 5 times */ 2794 2795 /* check if start bit is already here */ 2796 //if (scrGetData()) 2797 if (1) 2798 { 2799 /* didn't find it, keep looking */ 2800 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2801 sc->t0RecvByteS = t0rbsFindStartEdge; 2802 } 2803 else 2804 { 2805 /* found start bit, look for mid bit */ 2806 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv); 2807 sc->t0RecvByteS = t0rbsFindStartMid; 2808 } 2809 break; 2810 2811 2812 2813 default: 2814 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2815 break; 2816 } 2817 break; 2818 2819 2820 case t0rbsFindStartEdge: 2821 switch (cmd) 2822 { 2823 case t0rbcTFindStartEdge: 2824 if (scrGetData()) 2825 { 2826 /* didn't find it, keep looking */ 2827 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2828 } 2829 else 2830 { 2831 /* found start bit, look for mid bit */ 2832 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv * 2); 2833 sc->t0RecvByteS = t0rbsFindStartMid; 2834 } 2835 break; 2836 2837 2838 default: 2839 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2840 break; 2841 } 2842 break; 2843 2844 case t0rbsFindStartMid: 2845 switch (cmd) 2846 { 2847 case t0rbcTFindStartMid: 2848 if (scrGetData()) 2849 { 2850 /* found glitch, so just go back to hunting */ 2851 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2852 sc->t0RecvByteS = t0rbsFindStartEdge; 2853 } 2854 else 2855 { 2856 /* found start bit, start clocking in data */ 2857 TOGGLE_TEST_PIN(); 2858 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2859 sc->t0RecvByteS = t0rbsClockData; 2860 } 2861 break; 2862 2863 2864 default: 2865 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2866 break; 2867 } 2868 break; 2869 2870 2871 case t0rbsClockData: 2872 TOGGLE_TEST_PIN(); 2873 switch (cmd) 2874 { 2875 case t0rbcTClockData: 2876 if (sc->shiftBits < 8) 2877 { 2878 if (sc->convention == CONVENTION_INVERSE || 2879 sc->convention == CONVENTION_UNKNOWN) 2880 { 2881 /* logic 1 is low, msb is first */ 2882 sc->shiftByte <<= 1; 2883 sc->shiftByte &= 0xfe; 2884 if (!scrGetData()) 2885 { 2886 sc->shiftByte |= 0x01; 2887 sc->shiftParity++; 2888 } 2889 } 2890 else 2891 { 2892 ASSERT(sc->convention == CONVENTION_DIRECT); 2893 /* logic 1 is high, lsb is first */ 2894 sc->shiftByte = sc->shiftByte >> 1; 2895 sc->shiftByte &= 0x7f; 2896 if (scrGetData()) 2897 { 2898 sc->shiftParity++; 2899 sc->shiftByte |= 0x80; 2900 } 2901 } 2902 sc->shiftBits++; 2903 2904 2905 /* in TS byte, check if we have a card that works at 1/2 freq */ 2906 if (sc->convention == CONVENTION_UNKNOWN && /* in TS byte */ 2907 sc->shiftBits == 3 && /* test at bit 3 in word */ 2908 sc->shiftByte == 4 && /* check for 1/2 freq pattern */ 2909 sc->cardFreq == CARD_FREQ_DEF) /* only do this if at full freq */ 2910 { 2911 /* adjust counts down to 1/2 freq */ 2912 sc->cardFreq = CARD_FREQ_DEF / 2; 2913 sc->clkCountStartRecv = sc->clkCountStartRecv *2; 2914 sc->clkCountDataRecv = sc->clkCountDataRecv *2; 2915 sc->clkCountDataSend = sc->clkCountDataSend *2; 2916 2917 2918 /* adjust this so that we have clocked in only first bit of TS */ 2919 sc->shiftParity = 0; 2920 sc->shiftByte = 0; 2921 sc->shiftBits = 1; 2922 2923 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,(sc->clkCountDataRecv * 3) /4); 2924 } 2925 else 2926 { 2927 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2928 } 2929 } 2930 2931 /* clock in parity bit */ 2932 else if (sc->shiftBits == 8) 2933 { 2934 if (sc->convention == CONVENTION_INVERSE) 2935 { 2936 if (!scrGetData()) 2937 { 2938 sc->shiftParity++; 2939 } 2940 } 2941 else if (sc->convention == CONVENTION_DIRECT) 2942 { 2943 if (scrGetData()) 2944 { 2945 sc->shiftParity++; 2946 } 2947 } 2948 2949 2950 else 2951 { 2952 /* sc->convention not set so sort it out */ 2953 ASSERT(sc->convention == CONVENTION_UNKNOWN); 2954 if (sc->shiftByte == CONVENIONT_INVERSE_ID && scrGetData()) 2955 { 2956 sc->convention = CONVENTION_INVERSE; 2957 sc->shiftParity = 0; /* force good parity */ 2958 } 2959 2960 else if (sc->shiftByte == CONVENTION_DIRECT_ID && scrGetData()) 2961 { 2962 sc->shiftByte = CONVENTION_DIRECT_FIX; 2963 sc->convention = CONVENTION_DIRECT; 2964 sc->shiftParity = 0; /* force good parity */ 2965 } 2966 2967 else 2968 { 2969 sc->shiftParity = 1; /* force bad parity */ 2970 } 2971 } 2972 2973 2974 if ((sc->shiftParity & 01) == 0) 2975 { 2976 sc->shiftBits++; 2977 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2978 } 2979 else 2980 { 2981 /* got parity error */ 2982 if (sc->shiftParityCount < PARITY_ERROR_MAX) 2983 { 2984 sc->shiftParityCount++; 2985 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStart,sc->clkCountDataRecv); 2986 sc->t0RecvByteS = t0rbsSendError; 2987 } 2988 else 2989 2990 { 2991 /* too many parity errors, just give up on this sc->dataByte */ 2992 sc->status = ERROR_PARITY; 2993 sc->t0RecvByteS = t0rbsIdle; 2994 sc->t0ByteParent(sc,gcT0RecvByteErr); 2995 } 2996 } 2997 } 2998 2999 else 3000 { 3001 sc->dataByte = sc->shiftByte; 3002 sc->t0RecvByteS = t0rbsIdle; 3003 sc->t0ByteParent(sc,gcT0RecvByte); 3004 } 3005 break; 3006 3007 default: 3008 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3009 break; 3010 } 3011 break; 3012 3013 3014 case t0rbsSendError: 3015 TOGGLE_TEST_PIN(); 3016 switch (cmd) 3017 { 3018 case t0rbcTErrorStart: 3019 /* start sending error bit */ 3020 scrSetData(false); 3021 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStop,sc->clkCountDataRecv * 2); 3022 break; 3023 3024 case t0rbcTErrorStop: 3025 /* stop sending parity error & reset information*/ 3026 scrSetData(true); 3027 sc->shiftBits = 0; 3028 sc->shiftByte = 0; 3029 sc->shiftParity = 0; 3030 3031 /* start looking for start bit */ 3032 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,1); 3033 sc->t0RecvByteS = t0rbsFindStartEdge; 3034 break; 3035 3036 default: 3037 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3038 break; 3039 } 3040 break; 3041 3042 3043 default: 3044 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3045 break; 3046 } 3047 } 3048 3049 /* 3050 **++ 3051 ** FUNCTIONAL DESCRIPTION: 3052 ** 3053 ** t0SendByteSM 3054 ** 3055 ** This state machine writes 1 byte to a card. 3056 ** It is a low level bit-bashing state machine. 3057 ** 3058 ** 3059 ** Several mid level machines can use this machine, so the value 3060 ** sc->t0ByteParent is used to point to back to the mid level machine 3061 ** 3062 ** FORMAL PARAMETERS: 3063 ** 3064 ** sc - Pointer to the softc structure. 3065 ** cmd - command to this machine 3066 ** 3067 ** IMPLICIT INPUTS: 3068 ** 3069 ** sc->t0SendByteS state of this machine 3070 ** sc->shiftByte byte to write to the card 3071 ** 3072 ** IMPLICIT OUTPUTS: 3073 ** 3074 ** sc->status error value if could not read byte 3075 ** 3076 ** FUNCTION VALUE: 3077 ** 3078 ** nill 3079 ** 3080 ** SIDE EFFECTS: 3081 ** 3082 ** nill 3083 **-- 3084 */ 3085 //int bigTroubleTest = 0; 3086 static void t0SendByteSM (struct scr_softc * sc,int cmd) 3087 { 3088 //if(bigTroubleTest == 2000) 3089 //{ 3090 // INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3091 // bigTroubleTest = 0; 3092 //} 3093 // 3094 //bigTroubleTest++; 3095 3096 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 3097 3098 if (cmd == t0sbcAbort) 3099 { 3100 /* kill all the timers */ 3101 scrUntimeout(t0SendByteSM, sc, t0sbcTGuardTime); 3102 scrUntimeout(t0SendByteSM, sc, t0sbcTClockData); 3103 scrUntimeout(t0SendByteSM, sc, t0sbcTError); 3104 3105 scrSetDataHighZ(); 3106 return; 3107 } 3108 3109 3110 switch (sc->t0SendByteS) 3111 { 3112 case t0sbsIdle: 3113 switch (cmd) 3114 { 3115 case t0sbcStart: 3116 /* set initial conditions */ 3117 sc->shiftBits = 0; 3118 sc->shiftParity = 0; 3119 sc->shiftParityCount = 0; 3120 sc->shiftByte = sc->dataByte; 3121 3122 scrClkAdj(sc->clkCountDataSend); /* send data clock running at 1 ETU */ 3123 3124 /* check if we have to wait for guard time */ 3125 if (0) /* possible optimization here */ 3126 { 3127 /* can send start bit now */ 3128 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3129 scrSetData(false); 3130 sc->t0SendByteS = t0sbsClockData; 3131 } 3132 else 3133 { 3134 /* need to wait for guard time */ 3135 scrTimeout(t0SendByteSM,sc,t0sbcTGuardTime,sc->clkCountDataSend * (12 + sc->N)); 3136 sc->t0SendByteS = t0sbsWaitGuardTime; 3137 3138 } 3139 break; 3140 3141 default: 3142 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3143 break; 3144 } 3145 break; 3146 3147 3148 case t0sbsWaitGuardTime: 3149 switch (cmd) 3150 { 3151 case t0sbcTGuardTime: 3152 TOGGLE_TEST_PIN(); 3153 /* set start bit */ 3154 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3155 scrSetData(false); 3156 sc->t0SendByteS = t0sbsClockData; 3157 break; 3158 3159 default: 3160 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3161 break; 3162 } 3163 break; 3164 3165 3166 case t0sbsClockData: 3167 switch (cmd) 3168 { 3169 case t0sbcTClockData: 3170 TOGGLE_TEST_PIN(); 3171 /* clock out data bit */ 3172 if (sc->shiftBits < 8) 3173 { 3174 if (sc->convention == CONVENTION_INVERSE) 3175 { 3176 if (sc->shiftByte & 0x80) 3177 { 3178 scrSetData(false); 3179 sc->shiftParity++; 3180 } 3181 else 3182 { 3183 scrSetData(true); 3184 } 3185 sc->shiftByte = sc->shiftByte << 1; 3186 } 3187 else 3188 { 3189 ASSERT(sc->convention == CONVENTION_DIRECT); 3190 if (sc->shiftByte & 0x01) 3191 { 3192 scrSetData(true); 3193 sc->shiftParity++; 3194 } 3195 else 3196 { 3197 scrSetData(false); 3198 } 3199 sc->shiftByte = sc->shiftByte >> 1; 3200 } 3201 sc->shiftBits++; 3202 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3203 } 3204 3205 /* clock out parity bit */ 3206 else if (sc->shiftBits == 8) 3207 { 3208 if ( ((sc->shiftParity & 0x01) && (sc->convention == CONVENTION_INVERSE)) || 3209 (!(sc->shiftParity & 0x01) && (sc->convention == CONVENTION_DIRECT)) ) 3210 { 3211 scrSetData(false); 3212 } 3213 else 3214 { 3215 scrSetData(true); 3216 } 3217 sc->shiftBits++; 3218 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3219 } 3220 3221 /* all data shifted out, move onto next state */ 3222 else 3223 { 3224 ASSERT(sc->shiftBits > 8); 3225 scrSetData(true); 3226 scrTimeout(t0SendByteSM,sc,t0sbcTError,sc->clkCountDataSend); 3227 sc->t0SendByteS = t0sbsWaitError; 3228 } 3229 break; 3230 3231 default: 3232 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3233 break; 3234 } 3235 break; 3236 3237 case t0sbsWaitError: 3238 switch (cmd) 3239 { 3240 case t0sbcTError: 3241 /* no error indicated*/ 3242 if (scrGetData()) 3243 { 3244 sc->t0SendByteS = t0sbsIdle; 3245 sc->t0ByteParent(sc,gcT0SendByte); 3246 } 3247 3248 /* got error */ 3249 else 3250 { 3251 /* got parity error */ 3252 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3253 { 3254 sc->shiftParityCount++; 3255 scrTimeout(t0SendByteSM,sc,t0sbcTResend,sc->clkCountDataSend * 2); 3256 sc->t0SendByteS = t0sbsWaitResend; 3257 } 3258 else 3259 { 3260 /* too many parity errors, just give up on this sc->dataByte */ 3261 sc->status = ERROR_PARITY; 3262 sc->t0SendByteS = t0sbsIdle; 3263 sc->t0ByteParent(sc,gcT0SendByteErr); 3264 } 3265 } 3266 break; 3267 3268 default: 3269 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3270 break; 3271 } 3272 break; 3273 3274 case t0sbsWaitResend: 3275 switch (cmd) 3276 { 3277 case t0sbcTResend: 3278 sc->shiftBits = 0; 3279 sc->shiftParity = 0; 3280 sc->shiftByte = sc->dataByte; 3281 /* set start bit */ 3282 3283 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3284 scrSetData(false); 3285 sc->t0SendByteS = t0sbsClockData; 3286 break; 3287 3288 default: 3289 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3290 break; 3291 } 3292 break; 3293 3294 3295 default: 3296 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3297 break; 3298 } 3299 } 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 /* 3312 **++ 3313 ** FUNCTIONAL DESCRIPTION: 3314 ** 3315 ** cardOff 3316 ** 3317 ** Turn all signals to the card off 3318 ** 3319 ** FORMAL PARAMETERS: 3320 ** 3321 ** sc - Pointer to the softc structure. 3322 ** 3323 ** IMPLICIT INPUTS: 3324 ** 3325 ** nill 3326 ** 3327 ** IMPLICIT OUTPUTS: 3328 ** 3329 ** nill 3330 ** 3331 ** FUNCTION VALUE: 3332 ** 3333 ** nill 3334 ** 3335 ** SIDE EFFECTS: 3336 ** 3337 ** nill 3338 **-- 3339 */ 3340 static void cardOff (struct scr_softc * sc) 3341 { 3342 scrSetReset(true); 3343 scrSetDataHighZ(); 3344 scrSetClock(false); 3345 scrSetPower(false); 3346 } 3347 3348 3349 3350 3351 /* 3352 ** 3353 ** 3354 ** **************** timer routines *************** 3355 ** 3356 */ 3357 3358 /* 3359 **++ 3360 ** FUNCTIONAL DESCRIPTION: 3361 ** 3362 ** scrClkInit 3363 ** 3364 ** Init the callout queues. The callout queues are used 3365 ** by the timeout/untimeout queues 3366 ** 3367 ** FORMAL PARAMETERS: 3368 ** 3369 ** nill 3370 ** 3371 ** IMPLICIT INPUTS: 3372 ** 3373 ** nill 3374 ** 3375 ** IMPLICIT OUTPUTS: 3376 ** 3377 ** nill 3378 ** 3379 ** FUNCTION VALUE: 3380 ** 3381 ** nill 3382 ** 3383 ** SIDE EFFECTS: 3384 ** 3385 ** nill 3386 **-- 3387 */ 3388 static void scrClkInit(void) 3389 { 3390 3391 int lc; 3392 Callout *c; 3393 Callout *new; 3394 3395 scrClkCallTodo.c_next = NULL; 3396 scrClkCallFree = &scrClkCalloutArray[0]; 3397 c = scrClkCallFree; 3398 3399 for (lc = 1; lc < SCR_CLK_CALLOUT_COUNT; lc++) 3400 { 3401 new = &scrClkCalloutArray[lc]; 3402 c->c_next = new; 3403 c = new; 3404 } 3405 3406 c->c_next = NULL; 3407 } 3408 3409 3410 /* 3411 **++ 3412 ** FUNCTIONAL DESCRIPTION: 3413 ** 3414 ** scrClkStart 3415 ** 3416 ** This function starts the clock running. The clock is reall the 3417 ** HAT clock (High Available Timer) that is using a FIQ (fast interrupt 3418 ** request). 3419 ** 3420 ** FORMAL PARAMETERS: 3421 ** 3422 ** sc - Pointer to the softc structure. 3423 ** countPerTick - value for T2 timer that drives FIQ 3424 ** 3425 ** IMPLICIT INPUTS: 3426 ** 3427 ** nill 3428 ** 3429 ** IMPLICIT OUTPUTS: 3430 ** 3431 ** nill 3432 ** 3433 ** FUNCTION VALUE: 3434 ** 3435 ** nill 3436 ** 3437 ** SIDE EFFECTS: 3438 ** 3439 ** nill 3440 **-- 3441 */ 3442 static void scrClkStart(struct scr_softc * sc,int countPerTick) 3443 { 3444 u_int savedInts; 3445 3446 savedInts = disable_interrupts(I32_bit | F32_bit); 3447 3448 3449 3450 ASSERT(scrClkCallTodo.c_next == NULL); 3451 ASSERT(!scrClkEnable); 3452 scrClkEnable = 1; 3453 scrClkCount = countPerTick; 3454 3455 hatClkOn(countPerTick, 3456 hatClkIrq, 3457 0xdeadbeef, 3458 hatStack + HATSTACKSIZE - sizeof(unsigned), 3459 myHatWedge); 3460 3461 restore_interrupts(savedInts); 3462 } 3463 3464 /* 3465 **++ 3466 ** FUNCTIONAL DESCRIPTION: 3467 ** 3468 ** scrClkAdj 3469 ** 3470 ** Adjusts the frequency of the clock 3471 ** 3472 ** FORMAL PARAMETERS: 3473 ** 3474 ** count - new value for T2 timer that drives FIQ 3475 ** 3476 ** IMPLICIT INPUTS: 3477 ** 3478 ** nill 3479 ** 3480 ** IMPLICIT OUTPUTS: 3481 ** 3482 ** nill 3483 ** 3484 ** FUNCTION VALUE: 3485 ** 3486 ** nill 3487 ** 3488 ** SIDE EFFECTS: 3489 ** 3490 ** nill 3491 **-- 3492 */ 3493 static void scrClkAdj (int count) 3494 { 3495 u_int savedInts; 3496 3497 if (count != scrClkCount) 3498 { 3499 savedInts = disable_interrupts(I32_bit | F32_bit); 3500 3501 ASSERT(scrClkEnable); 3502 3503 scrClkCount = count; 3504 hatClkAdjust(count); 3505 3506 restore_interrupts(savedInts); 3507 } 3508 } 3509 3510 /* 3511 **++ 3512 ** FUNCTIONAL DESCRIPTION: 3513 ** 3514 ** scrClkStop 3515 ** 3516 ** Stops the clock 3517 ** 3518 ** FORMAL PARAMETERS: 3519 ** 3520 ** nill 3521 ** 3522 ** 3523 ** IMPLICIT INPUTS: 3524 ** 3525 ** nill 3526 ** 3527 ** IMPLICIT OUTPUTS: 3528 ** 3529 ** nill 3530 ** 3531 ** FUNCTION VALUE: 3532 ** 3533 ** nill 3534 ** 3535 ** SIDE EFFECTS: 3536 ** 3537 ** nill 3538 **-- 3539 */ 3540 static void scrClkStop(void) 3541 { 3542 u_int savedInts; 3543 savedInts = disable_interrupts(I32_bit | F32_bit); 3544 3545 ASSERT(scrClkEnable); 3546 scrClkEnable = 0; 3547 ASSERT(scrClkCallTodo.c_next == NULL); 3548 hatClkOff(); 3549 3550 restore_interrupts(savedInts); 3551 } 3552 3553 3554 3555 /* 3556 **++ 3557 ** FUNCTIONAL DESCRIPTION: 3558 ** 3559 ** hatClkIrq 3560 ** 3561 ** This is what the HAT clock calls. This call drives 3562 ** the timeout queues, which in turn drive the state machines 3563 ** 3564 ** Be very carefully when calling a timeout as the function 3565 ** that is called may in turn do timeout/untimeout calls 3566 ** before returning 3567 ** 3568 ** FORMAL PARAMETERS: 3569 ** 3570 ** int x - not used 3571 ** 3572 ** IMPLICIT INPUTS: 3573 ** 3574 ** nill 3575 ** 3576 ** IMPLICIT OUTPUTS: 3577 ** 3578 ** nill 3579 ** 3580 ** FUNCTION VALUE: 3581 ** 3582 ** nill 3583 ** 3584 ** SIDE EFFECTS: 3585 ** 3586 ** a timeout may be called if it is due 3587 **-- 3588 */ 3589 static void hatClkIrq(int x) 3590 { 3591 register Callout *p1; 3592 register int needsoft =0; 3593 register Callout *c; 3594 register int arg; 3595 register void (*func)(struct scr_softc*,int); 3596 struct scr_softc * sc; 3597 3598 ASSERT(scrClkEnable); 3599 for (p1 = scrClkCallTodo.c_next; p1 != NULL; p1 = p1->c_next) 3600 { 3601 p1->c_time -= scrClkCount; 3602 3603 if (p1->c_time > 0) 3604 { 3605 break; 3606 } 3607 needsoft = 1; 3608 if (p1->c_time == 0) 3609 { 3610 break; 3611 } 3612 } 3613 3614 3615 if (needsoft) 3616 { 3617 while ((c = scrClkCallTodo.c_next) != NULL && c->c_time <= 0) 3618 { 3619 func = c->c_func; 3620 sc = c->c_sc; 3621 arg = c->c_arg; 3622 scrClkCallTodo.c_next = c->c_next; 3623 c->c_next = scrClkCallFree; 3624 scrClkCallFree = c; 3625 (*func)(sc,arg); 3626 } 3627 } 3628 } 3629 3630 /* 3631 **++ 3632 ** FUNCTIONAL DESCRIPTION: 3633 ** 3634 ** myHatWedge 3635 ** 3636 ** Called if the HAT timer becomes clogged/wedged. Not 3637 ** used by this driver, we let upper layers recover 3638 ** from this condition 3639 ** 3640 ** FORMAL PARAMETERS: 3641 ** 3642 ** int nFIQs - not used 3643 ** 3644 ** IMPLICIT INPUTS: 3645 ** 3646 ** nill 3647 ** 3648 ** IMPLICIT OUTPUTS: 3649 ** 3650 ** nill 3651 ** 3652 ** FUNCTION VALUE: 3653 ** 3654 ** nill 3655 ** 3656 ** SIDE EFFECTS: 3657 ** 3658 ** nill 3659 **-- 3660 */ 3661 static void myHatWedge(int nFIQs) 3662 { 3663 #ifdef DEBUG 3664 printf("myHatWedge: nFIQ = %d\n",nFIQs); 3665 #endif 3666 } 3667 3668 3669 3670 /* 3671 **++ 3672 ** FUNCTIONAL DESCRIPTION: 3673 ** 3674 ** scrTimeout 3675 ** 3676 ** Execute a function after a specified length of time. 3677 ** 3678 ** 3679 ** FORMAL PARAMETERS: 3680 ** 3681 ** ftn - function to execute 3682 ** sc - pointer to soft c 3683 ** arg - argument passed to function 3684 ** count - number of T2 counts for timeout 3685 ** 3686 ** IMPLICIT INPUTS: 3687 ** 3688 ** nill 3689 ** 3690 ** IMPLICIT OUTPUTS: 3691 ** 3692 ** nill 3693 ** 3694 ** FUNCTION VALUE: 3695 ** 3696 ** nill 3697 ** 3698 ** SIDE EFFECTS: 3699 ** 3700 ** nill 3701 **-- 3702 */ 3703 3704 static void 3705 scrTimeout( 3706 void (*ftn)(struct scr_softc*,int), 3707 struct scr_softc* sc, 3708 int arg, 3709 int count) 3710 { 3711 3712 register Callout *new, *p, *t; 3713 ASSERT(scrClkEnable); 3714 3715 3716 if (count <= 0) 3717 { 3718 count = 1; 3719 } 3720 3721 3722 /* Fill in the next free fcallout structure. */ 3723 if (scrClkCallFree == NULL) 3724 { 3725 panic("timeout table full"); 3726 } 3727 3728 new = scrClkCallFree; 3729 scrClkCallFree = new->c_next; 3730 new->c_sc = sc; 3731 new->c_arg = arg; 3732 new->c_func = ftn; 3733 3734 /* 3735 * The time for each event is stored as a difference from the time 3736 * of the previous event on the queue. Walk the queue, correcting 3737 * the counts argument for queue entries passed. Correct the counts 3738 * value for the queue entry immediately after the insertion point 3739 * as well. Watch out for negative c_time values; these represent 3740 * overdue events. 3741 */ 3742 for (p = &scrClkCallTodo; (t = p->c_next) != NULL && count > t->c_time; p = t) 3743 { 3744 if (t->c_time > 0) 3745 { 3746 count -= t->c_time; 3747 } 3748 } 3749 3750 3751 new->c_time = count; 3752 if (t != NULL) 3753 { 3754 t->c_time -= count; 3755 } 3756 3757 /* Insert the new entry into the queue. */ 3758 p->c_next = new; 3759 new->c_next = t; 3760 } 3761 3762 /* 3763 **++ 3764 ** FUNCTIONAL DESCRIPTION: 3765 ** 3766 ** scrUntimeout 3767 ** 3768 ** Cancel previous timeout function call. 3769 ** 3770 ** FORMAL PARAMETERS: 3771 ** 3772 ** ftn - function of timeout to cancel 3773 ** sc - sc of timeout to cancel 3774 ** arg - arg of timeout to cancel 3775 ** 3776 ** IMPLICIT INPUTS: 3777 ** 3778 ** nill 3779 ** 3780 ** IMPLICIT OUTPUTS: 3781 ** 3782 ** nill 3783 ** 3784 ** FUNCTION VALUE: 3785 ** 3786 ** nill 3787 ** 3788 ** SIDE EFFECTS: 3789 ** 3790 ** nill 3791 **-- 3792 */ 3793 static void 3794 scrUntimeout( 3795 void (*ftn)(struct scr_softc*, int), 3796 struct scr_softc* sc, 3797 int arg) 3798 { 3799 register Callout *p, *t; 3800 ASSERT(scrClkEnable); 3801 3802 for (p = &scrClkCallTodo; (t = p->c_next) != NULL; p = t) 3803 { 3804 if (t->c_func == ftn && t->c_sc == sc && t->c_arg == arg) 3805 { 3806 /* Increment next entry's count. */ 3807 if (t->c_next && t->c_time > 0) 3808 { 3809 t->c_next->c_time += t->c_time; 3810 } 3811 3812 /* Move entry from fcallout queue to scrClkCallFree queue. */ 3813 p->c_next = t->c_next; 3814 t->c_next = scrClkCallFree; 3815 scrClkCallFree = t; 3816 break; 3817 } 3818 } 3819 } 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 /******************* routines used only during debugging */ 3836 #ifdef SCR_DEBUG 3837 3838 /* 3839 **++ 3840 ** FUNCTIONAL DESCRIPTION: 3841 ** 3842 ** invalidStateCmd 3843 ** 3844 ** Debugging function. Printout information about problem 3845 ** and then kick in the debugger or panic 3846 ** 3847 ** FORMAL PARAMETERS: 3848 ** 3849 ** sc - pointer to soft c 3850 ** state - state of machine 3851 ** cmd - command of machine 3852 ** line - line that problem was detected 3853 ** 3854 ** 3855 ** IMPLICIT INPUTS: 3856 ** 3857 ** nill 3858 ** 3859 ** IMPLICIT OUTPUTS: 3860 ** 3861 ** nill 3862 ** 3863 ** FUNCTION VALUE: 3864 ** 3865 ** nill 3866 ** 3867 ** SIDE EFFECTS: 3868 ** 3869 ** nill 3870 **-- 3871 */ 3872 void invalidStateCmd (struct scr_softc* sc,int state,int cmd,int line) 3873 { 3874 printf("INVALID_STATE_CMD: sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,line); 3875 DEBUGGER; 3876 } 3877 3878 /* 3879 **++ 3880 ** FUNCTIONAL DESCRIPTION: 3881 ** 3882 ** getText 3883 ** 3884 ** Get text representation of state or command 3885 ** 3886 ** FORMAL PARAMETERS: 3887 ** 3888 ** x - state or command 3889 ** 3890 ** IMPLICIT INPUTS: 3891 ** 3892 ** nill 3893 ** 3894 ** IMPLICIT OUTPUTS: 3895 ** 3896 ** nill 3897 ** 3898 ** FUNCTION VALUE: 3899 ** 3900 ** nill 3901 ** 3902 ** SIDE EFFECTS: 3903 ** 3904 ** nill 3905 **-- 3906 */ 3907 char * getText(int x) 3908 { 3909 switch (x) 3910 { 3911 /* commands to Master State Machine (mc = Master Command )*/ 3912 case mcOn: return "mcOn"; 3913 case mcT0DataSend: return "mcT0DataSend"; 3914 case mcT0DataRecv: return "mcT0DataRecv"; 3915 case mcColdReset: return "mcColdReset"; 3916 case mcATR: return "mcATR"; 3917 case mcT0Send: return "mcT0Send"; 3918 case mcT0Recv: return "mcT0Recv"; 3919 3920 /* states in Master state machine (ms = Master State) */ 3921 case msIdleOff: return "msIdleOff"; 3922 case msColdReset: return "msColdReset"; 3923 case msATR: return "msATR"; 3924 case msIdleOn: return "msIdleOn"; 3925 case msT0Send: return "msT0Send"; 3926 case msT0Recv: return "msT0Recv"; 3927 3928 3929 3930 /* commands to T0 send state machine */ 3931 case t0scStart: return "t0scStart"; 3932 case t0scTWorkWaiting: return "t0scTWorkWaiting"; 3933 3934 3935 /* states in T0 send state machine */ 3936 case t0ssIdle: return "t0ssIdle"; 3937 case t0ssSendHeader: return "t0ssSendHeader"; 3938 case t0ssRecvProcedure: return "t0ssRecvProcedu"; 3939 case t0ssSendByte: return "t0ssSendByte"; 3940 case t0ssSendData: return "t0ssSendData"; 3941 case t0ssRecvSW1: return "t0ssRecvSW1"; 3942 case t0ssRecvSW2: return "t0ssRecvSW2"; 3943 3944 3945 /* commands to T0 recv state machine */ 3946 case t0rcStart: return "t0rcStart"; 3947 case t0rcTWorkWaiting: return "t0rcTWorkWaiting"; 3948 3949 /* states in T0 recv state machine */ 3950 case t0rsIdle: return "t0rsIdle"; 3951 case t0rsSendHeader: return "t0rsSendHeader"; 3952 case t0rsRecvProcedure: return "t0rsRecvProcedure"; 3953 case t0rsRecvByte: return "t0rsRecvByte"; 3954 case t0rsRecvData: return "t0rsRecvData"; 3955 case t0rsRecvSW1: return "t0rsRecvSW1"; 3956 case t0rsRecvSW2: return "t0rsRecvSW2"; 3957 3958 3959 3960 3961 3962 /* commands to Answer To Reset (ATR) state machine */ 3963 case atrcStart: return "atrcStart"; 3964 case atrcT3: return "0x0b04"; 3965 case atrcTWorkWaiting: return "atrcTWorkWaiting"; 3966 3967 3968 /* states in in Anser To Reset (ATR) state machine */ 3969 case atrsIdle: return "atrsIdle"; 3970 case atrsTS: return "atrsTS"; 3971 case atrsT0: return "atrsT0"; 3972 case atrsTABCD: return "atrsTABCD"; 3973 case atrsTK: return "atrsTK"; 3974 case atrsTCK: return "atrsTCK"; 3975 3976 3977 3978 /* commands to T0 Recv Byte state machine */ 3979 case t0rbcStart: return "t0rbcStart"; 3980 case t0rbcAbort: return "t0rbcAbort"; 3981 3982 case t0rbcTFindStartEdge:return "t0rbcTFindStartEdge"; 3983 case t0rbcTFindStartMid: return "t0rbcTFindStartMid"; 3984 case t0rbcTClockData: return "t0rbcTClockData"; 3985 case t0rbcTErrorStart: return "t0rbcTErrorStart"; 3986 case t0rbcTErrorStop: return "t0rbcTErrorStop"; 3987 3988 /* states in in TO Recv Byte state machine */ 3989 case t0rbsIdle: return "t0rbsIdle"; 3990 case t0rbsFindStartEdge: return "t0rbcFindStartEdge"; 3991 case t0rbsFindStartMid: return "t0rbcFindStartMid"; 3992 case t0rbsClockData: return "t0rbcClockData"; 3993 case t0rbsSendError: return "t0rbcSendError"; 3994 3995 3996 /* commands to T0 Send Byte state machine */ 3997 case t0sbcStart: return "t0sbcStart"; 3998 case t0sbcAbort: return "t0sbcAbort"; 3999 case t0sbcTGuardTime: return "t0sbcTGuardTime"; 4000 case t0sbcTClockData: return "t0sbcTClockData"; 4001 case t0sbcTError: return "t0sbcTError"; 4002 case t0sbcTResend: return "t0sbcTResend"; 4003 4004 /* states in in T0 Send Byte state machine */ 4005 case t0sbsIdle: return "t0sbsIdle"; 4006 case t0sbsClockData: return "t0sbsClockData"; 4007 case t0sbsWaitError: return "t0sbsWaitError"; 4008 case t0sbsWaitResend: return "t0sbsWaitResend"; 4009 case t0sbsWaitGuardTime: return "t0sbsWaitGuardTime"; 4010 4011 4012 case gcT0RecvByte: return "gcT0RecvByte"; 4013 case gcT0RecvByteErr: return "gcT0RecvByteErr"; 4014 case gcT0SendByte: return "gcT0SendByte"; 4015 case gcT0SendByteErr: return "gcT0SendByteErr"; 4016 4017 4018 case crcStart: return "crcStart"; 4019 case crcT2: return "crcT2"; 4020 4021 4022 default: 4023 printf("unknown case, %x\n",x); 4024 break; 4025 } 4026 return "???"; 4027 } 4028 4029 #endif /* SCR_DEBUG */ 4030
Indexes created Sat Sep 20 22:09:52 GMT 2025