1 /* $NetBSD: cortex_pmc.c,v 1.9 2025/12/19 13:03:51 nia Exp $ */ 2 3 /* Copyright (c) 2007 Microsoft 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 29 /* 30 * support for ARM cortex Performance Monitor Counters 31 * based on arm11_pmc.c 32 */ 33 34 #include <sys/cdefs.h> 35 /* __KERNEL_RCSID(0, "$NetBSD: cortex_pmc.c,v 1.9 2025/12/19 13:03:51 nia Exp $"); */ 36 37 #include <sys/param.h> 38 #include <sys/types.h> 39 40 #include <sys/kernel.h> 41 #include <sys/systm.h> 42 #include <sys/time.h> 43 #include <sys/timetc.h> 44 45 #include <dev/clock_subr.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <arm/armreg.h> 50 #include <arm/cpufunc.h> 51 #include <arm/arm32/machdep.h> 52 53 #ifndef CORTEX_PMC_CCNT_HZ 54 # define CORTEX_PMC_CCNT_HZ 400000000 /* 400MHz */ 55 #endif 56 57 #define COUNTS_PER_USEC (curcpu()->ci_data.cpu_cc_freq / (1000*1000)) 58 59 static const uint32_t counts_per_wrap = ~0UL - 1; 60 61 /* 62 * enable the PMC CCNT for delay() 63 */ 64 void 65 cortex_pmc_ccnt_init(void) 66 { 67 if (curcpu()->ci_data.cpu_cc_freq == 0) { 68 curcpu()->ci_data.cpu_cc_freq = CORTEX_PMC_CCNT_HZ; 69 } 70 } 71 72 /* 73 * delay - for "at least" arg usec 74 * 75 * NOTE: at 400MHz we are restricted to (uint32_t)~0 "counts" 76 * if this is a problem, accumulate counts in LL vars 77 */ 78 void 79 delay(u_int arg) 80 { 81 uint32_t ctrl; 82 uint32_t cur; 83 uint32_t last; 84 uint32_t delta = 0; 85 uint32_t usecs = 0; 86 const uint32_t counts_per_usec = COUNTS_PER_USEC; 87 const uint32_t delay_arg_limit = ~0UL / counts_per_usec; /* about 10 sec */ 88 89 if (arg > delay_arg_limit) 90 panic("%s: arg %u overflow, limit is %u usec\n", 91 __func__, arg, delay_arg_limit); 92 93 last = armreg_pmccntr_read(); 94 delta = usecs = 0; 95 while (arg > usecs) { 96 cur = armreg_pmccntr_read(); 97 98 /* 99 * overflow flag is moved to a separate register 100 * and is not read from PMC Control Register 101 */ 102 ctrl = armreg_pmovsr_read(); 103 if (ctrl & CORTEX_CNTOFL_C) { 104 /* 105 * Reset overflow flag for cycle counter in overflow 106 * register 107 */ 108 armreg_pmovsr_write(CORTEX_CNTOFL_C); 109 delta += (cur + (counts_per_wrap - last)); 110 } else { 111 delta += (cur - last); 112 } 113 last = cur; 114 if (delta >= counts_per_usec) { 115 usecs += delta / counts_per_usec; 116 delta %= counts_per_usec; 117 } 118 } 119 } 120