1 /* $NetBSD: cpc700.c,v 1.24 2022/09/25 18:43:32 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * The IBM CPC700 is a bridge chip for the PowerPC. It contains 34 * - CPU interface 35 * - DRAM controller 36 * - PCI bus master & slave controller 37 * - interrupt controller 38 * - timer 39 * - two UARTs 40 * - two IIC ports 41 * 42 * This driver handles the overall device and enumeration of the 43 * supported subdevices. NetBSD knows how to handle: 44 * - PCI master 45 * - interrupt controller 46 * - UARTs 47 * Skeleton drivers are provided for the timer and IIC. 48 * 49 * XXX This driver assumes that there is only one instance of it. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.24 2022/09/25 18:43:32 thorpej Exp $"); 54 55 #include "pci.h" 56 #include "opt_pci.h" 57 58 #include <sys/param.h> 59 #include <sys/device.h> 60 #include <sys/systm.h> 61 62 #include <sys/bus.h> 63 #include "locators.h" 64 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pciconf.h> 68 69 #include <dev/ic/cpc700reg.h> 70 #include <dev/ic/cpc700var.h> 71 #include <dev/ic/cpc700uic.h> 72 73 union attach_args { 74 struct pcibus_attach_args pba; 75 struct cpcbus_attach_args cba; 76 }; 77 78 79 void 80 cpc_attach(device_t self, pci_chipset_tag_t pc, bus_space_tag_t mem, 81 bus_space_tag_t pciio, bus_dma_tag_t tag, int attachpci, 82 uint freq); 83 84 static bus_space_tag_t the_cpc_tag; 85 static bus_space_handle_t the_cpc_handle; 86 #define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a)) 87 #define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d) 88 89 #define PCI_IO_START CPC_PCI_IO_START 90 #define PCI_IO_END CPC_PCI_IO_END 91 #define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 92 93 #define PCI_MEM_START CPC_PCI_MEM_BASE 94 #define PCI_MEM_END CPC_PCI_MEM_END 95 #define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1) 96 97 static int 98 cpc_print(void *aux, const char *pnp) 99 { 100 struct cpcbus_attach_args *caa = aux; 101 102 if (pnp) 103 aprint_normal("%s at %s", caa->cpca_name, pnp); 104 105 aprint_normal(" addr 0x%08x", caa->cpca_addr); 106 if (caa->cpca_irq != CPCBUSCF_IRQ_DEFAULT) 107 aprint_normal(" irq %d", caa->cpca_irq); 108 109 return (UNCONF); 110 } 111 112 static int 113 cpc_submatch(device_t parent, cfdata_t cf, 114 const int *ldesc, void *aux) 115 { 116 struct cpcbus_attach_args *caa = aux; 117 118 if (cf->cf_loc[CPCBUSCF_ADDR] != caa->cpca_addr) 119 return (0); 120 121 return (config_match(parent, cf, aux)); 122 } 123 124 /* 125 * Attach the cpc. 126 */ 127 void 128 cpc_attach(device_t self, pci_chipset_tag_t pc, bus_space_tag_t mem, 129 bus_space_tag_t pciio, bus_dma_tag_t dma, int attachpci, 130 uint freq) 131 { 132 union attach_args aa; 133 int i; 134 pcitag_t tag; 135 pcireg_t erren; 136 pcireg_t v; 137 static struct { 138 const char *name; 139 bus_addr_t addr; 140 int irq; 141 } devs[] = { 142 { "com", CPC_COM0, CPC_IB_UART_0 }, 143 { "com", CPC_COM1, CPC_IB_UART_1 }, 144 { "cpctim", CPC_TIMER, CPCBUSCF_IRQ_DEFAULT }, 145 { "cpciic", CPC_IIC0, CPC_IB_IIC_0 }, 146 { "cpciic", CPC_IIC1, CPC_IB_IIC_1 }, 147 { NULL, 0 } 148 }; 149 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 150 #ifdef PCI_CONFIGURE_VERBOSE 151 extern int pci_conf_debug; 152 153 pci_conf_debug = 1; 154 #endif 155 #endif 156 157 printf(": IBM CPC700\n"); 158 159 the_cpc_tag = mem; 160 if (bus_space_map(mem, CPC_UIC_BASE, CPC_UIC_SIZE, 0, 161 &the_cpc_handle)) { 162 aprint_error_dev(self, "can't map i/o space\n"); 163 return; 164 } 165 166 aa.cba.cpca_tag = mem; 167 aa.cba.cpca_freq = freq; 168 for (i = 0; devs[i].name; i++) { 169 aa.cba.cpca_name = devs[i].name; 170 aa.cba.cpca_addr = devs[i].addr; 171 aa.cba.cpca_irq = devs[i].irq; 172 config_found(self, &aa.cba, cpc_print, 173 CFARGS(.submatch = cpc_submatch, 174 .iattr = "cpcbus")); 175 } 176 177 tag = pci_make_tag(pc, 0, 0, 0); 178 179 aa.pba.pba_iot = pciio; 180 aa.pba.pba_memt = mem; 181 aa.pba.pba_dmat = dma; 182 aa.pba.pba_pc = pc; 183 aa.pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 184 aa.pba.pba_bus = 0; 185 186 /* Save PCI error condition reg. */ 187 erren = pci_conf_read(pc, tag, CPC_PCI_BRDGERR); 188 /* Don't generate errors during probe. */ 189 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, 0); 190 191 /* Program MITL */ 192 v = pci_conf_read(pc, tag, CPC_BRIDGE_OPTIONS2); 193 v &= ~(CPC_BRIDGE_O2_ILAT_MASK | CPC_BRIDGE_O2_SLAT_MASK); 194 v |= (CPC_BRIDGE_O2_ILAT_PRIM_ASYNC << CPC_BRIDGE_O2_ILAT_SHIFT) | 195 (CPC_BRIDGE_O2_2LAT_PRIM_ASYNC << CPC_BRIDGE_O2_SLAT_SHIFT); 196 pci_conf_write(pc, tag, CPC_BRIDGE_OPTIONS2, v); 197 198 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 199 struct pciconf_resources *pcires = pciconf_resource_init(); 200 201 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 202 PCI_IO_START, PCI_IO_SIZE); 203 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 204 PCI_MEM_START, PCI_MEM_SIZE); 205 206 pci_configure_bus(0, pcires, 0, 32); 207 #endif 208 209 config_found(self, &aa.pba, pcibusprint, 210 CFARGS(.iattr = "pcibus")); 211 212 /* Restore error triggers, and clear errors */ 213 pci_conf_write(pc, tag, CPC_PCI_BRDGERR, erren | CPC_PCI_CLEARERR); 214 } 215 216 /***************************************************************************/ 217 218 /* 219 * Interrupt controller. 220 */ 221 222 void 223 cpc700_init_intr(bus_space_tag_t bt, bus_space_handle_t bh, 224 u_int32_t active, u_int32_t level) 225 { 226 /* XXX */ 227 the_cpc_tag = bt; 228 the_cpc_handle = bh; 229 /* 230 * See CPC700 manual for information about what 231 * interrupts have which properties. 232 */ 233 OUTL(CPC_UIC_SR, 0xffffffff); /* clear all intrs */ 234 OUTL(CPC_UIC_ER, 0x00000000); /* disable all intrs */ 235 OUTL(CPC_UIC_CR, 0xffffffff); /* gen INT not MCP */ 236 OUTL(CPC_UIC_PR, 0xffff8000 | active); /* 0 = active low */ 237 OUTL(CPC_UIC_TR, 0xc0000000 | level); /* 0 = level intr */ 238 OUTL(CPC_UIC_VR, CPC_UIC_CVR_PRI); /* intr 0 is highest */ 239 } 240 241 int 242 cpc700_read_irq(void) 243 { 244 int irq; 245 u_int32_t irqs; 246 247 irqs = INL(CPC_UIC_MSR); 248 for (irq = 0; irq < ICU_LEN; irq++) { 249 if (irqs & CPC_INTR_MASK(irq)) 250 return (irq); 251 } 252 return (-1); 253 } 254 255 void 256 cpc700_eoi(int irq) 257 { 258 OUTL(CPC_UIC_SR, CPC_INTR_MASK(irq)); 259 } 260 261 void 262 cpc700_disable_irq(int irq) 263 { 264 u_int32_t reg; 265 266 reg = INL(CPC_UIC_ER); 267 reg &= ~CPC_INTR_MASK(irq); 268 OUTL(CPC_UIC_ER, reg); 269 } 270 271 void 272 cpc700_enable_irq(int irq) 273 { 274 u_int32_t reg; 275 276 reg = INL(CPC_UIC_ER); 277 reg |= CPC_INTR_MASK(irq); 278 OUTL(CPC_UIC_ER, reg); 279 } 280
Indexes created Sun Sep 21 18:09:52 GMT 2025