1 /* $NetBSD: tegra124_cpu.c,v 1.6 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 #include "opt_multiprocessor.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra124_cpu.c,v 1.6 2021/01/27 03:10:19 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arm/cpufunc.h> 45 46 #include <arm/nvidia/tegra_reg.h> 47 #include <arm/nvidia/tegra_pmcreg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 51 #define FUSE_SKU_INFO_REG 0x010 52 #define FUSE_CPU_SPEEDO_0_REG 0x014 53 #define FUSE_CPU_IDDQ_REG 0x018 54 #define FUSE_FT_REV_REG 0x028 55 #define FUSE_CPU_SPEEDO_1_REG 0x02c 56 #define FUSE_CPU_SPEEDO_2_REG 0x030 57 #define FUSE_SOC_SPEEDO_0_REG 0x034 58 #define FUSE_SOC_SPEEDO_1_REG 0x038 59 #define FUSE_SOC_SPEEDO_2_REG 0x03c 60 #define FUSE_SOC_IDDQ_REG 0x040 61 #define FUSE_GPU_IDDQ_REG 0x128 62 63 static void tegra124_speedo_init(void); 64 static int tegra124_speedo_init_ids(uint32_t); 65 static bool tegra124_speedo_rate_ok(u_int); 66 67 static u_int tegra124_cpufreq_set_rate(u_int); 68 static u_int tegra124_cpufreq_get_rate(void); 69 static size_t tegra124_cpufreq_get_available(u_int *, size_t); 70 71 static int tegra124_cpu_match(device_t, cfdata_t, void *); 72 static void tegra124_cpu_attach(device_t, device_t, void *); 73 static int tegra124_cpu_init_cpufreq(device_t); 74 75 CFATTACH_DECL_NEW(tegra124_cpu, 0, tegra124_cpu_match, tegra124_cpu_attach, 76 NULL, NULL); 77 78 static const struct tegra_cpufreq_func tegra124_cpufreq_func = { 79 .set_rate = tegra124_cpufreq_set_rate, 80 .get_rate = tegra124_cpufreq_get_rate, 81 .get_available = tegra124_cpufreq_get_available, 82 }; 83 84 static struct tegra124_cpufreq_rate { 85 u_int rate; 86 u_int divm; 87 u_int divn; 88 u_int divp; 89 u_int uvol; 90 } tegra124_cpufreq_rates[] = { 91 { 2316, 1, 193, 0, 1360000 }, 92 { 2100, 1, 175, 0, 1260000 }, 93 { 1896, 1, 158, 0, 1180000 }, 94 { 1692, 1, 141, 0, 1100000 }, 95 { 1500, 1, 125, 0, 1020000 }, 96 { 1296, 1, 108, 0, 960000 }, 97 { 1092, 1, 91, 0, 900000 }, 98 { 900, 1, 75, 0, 840000 }, 99 { 696, 1, 58, 0, 800000 } 100 }; 101 102 static const u_int tegra124_cpufreq_max[] = { 103 2014, 104 2320, 105 2116, 106 2524 107 }; 108 109 static struct tegra124_speedo { 110 u_int cpu_speedo_id; 111 u_int soc_speedo_id; 112 u_int gpu_speedo_id; 113 } tegra124_speedo = { 114 .cpu_speedo_id = 0, 115 .soc_speedo_id = 0, 116 .gpu_speedo_id = 0 117 }; 118 119 static struct clk *tegra124_clk_pllx = NULL; 120 static struct fdtbus_regulator *tegra124_reg_vddcpu = NULL; 121 122 static const struct device_compatible_entry compat_data[] = { 123 { .compat = "nvidia,tegra124" }, 124 DEVICE_COMPAT_EOL 125 }; 126 127 static int 128 tegra124_cpu_match(device_t parent, cfdata_t cf, void *aux) 129 { 130 struct fdt_attach_args *faa = aux; 131 132 if (OF_finddevice("/cpus/cpu@0") != faa->faa_phandle) 133 return 0; 134 135 return of_compatible_match(OF_finddevice("/"), compat_data); 136 } 137 138 static void 139 tegra124_cpu_attach(device_t parent, device_t self, void *aux) 140 { 141 aprint_naive("\n"); 142 aprint_normal(": DVFS\n"); 143 144 config_finalize_register(self, tegra124_cpu_init_cpufreq); 145 } 146 147 static bool tegra124_cpu_init_done = false; 148 149 static int 150 tegra124_cpu_init_cpufreq(device_t dev) 151 { 152 if (tegra124_cpu_init_done) 153 return 0; 154 155 tegra124_speedo_init(); 156 157 int cpu_node = OF_finddevice("/cpus/cpu@0"); 158 if (cpu_node != -1) { 159 tegra124_clk_pllx = fdtbus_clock_get(cpu_node, "pll_x"); 160 tegra124_reg_vddcpu = fdtbus_regulator_acquire(cpu_node, 161 "vdd-cpu-supply"); 162 } 163 if (tegra124_clk_pllx == NULL) { 164 aprint_error_dev(dev, "couldn't find clock pll_x\n"); 165 return 0; 166 } 167 if (tegra124_reg_vddcpu == NULL) { 168 aprint_error_dev(dev, "couldn't find voltage regulator\n"); 169 return 0; 170 } 171 172 tegra_cpufreq_register(&tegra124_cpufreq_func); 173 174 tegra124_cpu_init_done = true; 175 176 return 0; 177 } 178 179 static void 180 tegra124_speedo_init(void) 181 { 182 uint32_t sku_id; 183 184 sku_id = tegra_fuse_read(FUSE_SKU_INFO_REG); 185 tegra124_speedo_init_ids(sku_id); 186 } 187 188 static int 189 tegra124_speedo_init_ids(uint32_t sku_id) 190 { 191 int threshold = 0; 192 193 switch (sku_id) { 194 case 0x00: 195 case 0x0f: 196 case 0x23: 197 break; /* use default */ 198 case 0x83: 199 tegra124_speedo.cpu_speedo_id = 2; 200 break; 201 case 0x1f: 202 case 0x87: 203 case 0x27: 204 tegra124_speedo.cpu_speedo_id = 2; 205 tegra124_speedo.soc_speedo_id = 0; 206 tegra124_speedo.gpu_speedo_id = 1; 207 break; 208 case 0x81: 209 case 0x21: 210 case 0x07: 211 tegra124_speedo.cpu_speedo_id = 1; 212 tegra124_speedo.soc_speedo_id = 1; 213 tegra124_speedo.gpu_speedo_id = 1; 214 threshold = 1; 215 break; 216 case 0x49: 217 case 0x4a: 218 case 0x48: 219 tegra124_speedo.cpu_speedo_id = 4; 220 tegra124_speedo.soc_speedo_id = 2; 221 tegra124_speedo.gpu_speedo_id = 3; 222 threshold = 1; 223 break; 224 default: 225 aprint_error("tegra124: unknown SKU ID %#x\n", sku_id); 226 break; /* use default */ 227 } 228 229 return threshold; 230 } 231 232 static bool 233 tegra124_speedo_rate_ok(u_int rate) 234 { 235 u_int tbl = 0; 236 237 if (tegra124_speedo.cpu_speedo_id < __arraycount(tegra124_cpufreq_max)) 238 tbl = tegra124_speedo.cpu_speedo_id; 239 240 return rate <= tegra124_cpufreq_max[tbl]; 241 } 242 243 244 static u_int 245 tegra124_cpufreq_set_rate(u_int rate) 246 { 247 const u_int nrates = __arraycount(tegra124_cpufreq_rates); 248 const struct tegra124_cpufreq_rate *r = NULL; 249 CPU_INFO_ITERATOR cii; 250 struct cpu_info *ci; 251 u_int cur_uvol; 252 int error; 253 254 if (tegra124_speedo_rate_ok(rate) == false) 255 return EINVAL; 256 257 for (int i = 0; i < nrates; i++) { 258 if (tegra124_cpufreq_rates[i].rate == rate) { 259 r = &tegra124_cpufreq_rates[i]; 260 break; 261 } 262 } 263 if (r == NULL) 264 return EINVAL; 265 266 error = fdtbus_regulator_get_voltage(tegra124_reg_vddcpu, &cur_uvol); 267 if (error != 0) 268 return error; 269 270 if (cur_uvol < r->uvol) { 271 error = fdtbus_regulator_set_voltage(tegra124_reg_vddcpu, 272 r->uvol, r->uvol); 273 if (error != 0) 274 return error; 275 } 276 277 error = clk_set_rate(tegra124_clk_pllx, r->rate * 1000000); 278 if (error == 0) { 279 rate = tegra124_cpufreq_get_rate(); 280 for (CPU_INFO_FOREACH(cii, ci)) { 281 ci->ci_data.cpu_cc_freq = rate * 1000000; 282 } 283 } 284 285 if (cur_uvol > r->uvol) { 286 (void)fdtbus_regulator_set_voltage(tegra124_reg_vddcpu, 287 r->uvol, r->uvol); 288 } 289 290 return error; 291 } 292 293 static u_int 294 tegra124_cpufreq_get_rate(void) 295 { 296 return clk_get_rate(tegra124_clk_pllx) / 1000000; 297 } 298 299 static size_t 300 tegra124_cpufreq_get_available(u_int *pavail, size_t maxavail) 301 { 302 const u_int nrates = __arraycount(tegra124_cpufreq_rates); 303 u_int n, cnt; 304 305 KASSERT(nrates <= maxavail); 306 307 for (n = 0, cnt = 0; n < nrates; n++) { 308 if (tegra124_speedo_rate_ok(tegra124_cpufreq_rates[n].rate)) { 309 pavail[cnt++] = tegra124_cpufreq_rates[n].rate; 310 } 311 } 312 313 return cnt; 314 } 315
Indexes created Sun Sep 21 16:09:51 GMT 2025